1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#ifndef __SOC_MEDIATEK_MTK_MMSYS_H
4#define __SOC_MEDIATEK_MTK_MMSYS_H
5
6#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
7#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
8#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
9#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
10#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
11#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
12#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
13#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
14#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
15#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
16#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
17#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
18#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
19#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
20
21#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
22#define DISP_REG_CONFIG_OUT_SEL			0x04c
23#define DISP_REG_CONFIG_DSI_SEL			0x050
24#define DISP_REG_CONFIG_DPI_SEL			0x064
25
26#define OVL0_MOUT_EN_COLOR0			0x1
27#define OD_MOUT_EN_RDMA0			0x1
28#define OD1_MOUT_EN_RDMA1			BIT(16)
29#define UFOE_MOUT_EN_DSI0			0x1
30#define COLOR0_SEL_IN_OVL0			0x1
31#define OVL1_MOUT_EN_COLOR1			0x1
32#define GAMMA_MOUT_EN_RDMA1			0x1
33#define RDMA0_SOUT_DPI0				0x2
34#define RDMA0_SOUT_DPI1				0x3
35#define RDMA0_SOUT_DSI1				0x1
36#define RDMA0_SOUT_DSI2				0x4
37#define RDMA0_SOUT_DSI3				0x5
38#define RDMA0_SOUT_MASK				0x7
39#define RDMA1_SOUT_DPI0				0x2
40#define RDMA1_SOUT_DPI1				0x3
41#define RDMA1_SOUT_DSI1				0x1
42#define RDMA1_SOUT_DSI2				0x4
43#define RDMA1_SOUT_DSI3				0x5
44#define RDMA1_SOUT_MASK				0x7
45#define RDMA2_SOUT_DPI0				0x2
46#define RDMA2_SOUT_DPI1				0x3
47#define RDMA2_SOUT_DSI1				0x1
48#define RDMA2_SOUT_DSI2				0x4
49#define RDMA2_SOUT_DSI3				0x5
50#define RDMA2_SOUT_MASK				0x7
51#define DPI0_SEL_IN_RDMA1			0x1
52#define DPI0_SEL_IN_RDMA2			0x3
53#define DPI0_SEL_IN_MASK			0x3
54#define DPI1_SEL_IN_RDMA1			(0x1 << 8)
55#define DPI1_SEL_IN_RDMA2			(0x3 << 8)
56#define DPI1_SEL_IN_MASK			(0x3 << 8)
57#define DSI0_SEL_IN_RDMA1			0x1
58#define DSI0_SEL_IN_RDMA2			0x4
59#define DSI0_SEL_IN_MASK			0x7
60#define DSI1_SEL_IN_RDMA1			0x1
61#define DSI1_SEL_IN_RDMA2			0x4
62#define DSI1_SEL_IN_MASK			0x7
63#define DSI2_SEL_IN_RDMA1			(0x1 << 16)
64#define DSI2_SEL_IN_RDMA2			(0x4 << 16)
65#define DSI2_SEL_IN_MASK			(0x7 << 16)
66#define DSI3_SEL_IN_RDMA1			(0x1 << 16)
67#define DSI3_SEL_IN_RDMA2			(0x4 << 16)
68#define DSI3_SEL_IN_MASK			(0x7 << 16)
69#define COLOR1_SEL_IN_OVL1			0x1
70
71#define OVL_MOUT_EN_RDMA			0x1
72#define BLS_TO_DSI_RDMA1_TO_DPI1		0x8
73#define BLS_TO_DPI_RDMA1_TO_DSI			0x2
74#define BLS_RDMA1_DSI_DPI_MASK			0xf
75#define DSI_SEL_IN_BLS				0x0
76#define DPI_SEL_IN_BLS				0x0
77#define DPI_SEL_IN_MASK				0x1
78#define DSI_SEL_IN_RDMA				0x1
79#define DSI_SEL_IN_MASK				0x1
80
81struct mtk_mmsys_routes {
82	u32 from_comp;
83	u32 to_comp;
84	u32 addr;
85	u32 mask;
86	u32 val;
87};
88
89struct mtk_mmsys_driver_data {
90	const char *clk_driver;
91	const struct mtk_mmsys_routes *routes;
92	const unsigned int num_routes;
93	const u16 sw0_rst_offset;
94	const u32 num_resets;
95	const bool is_vppsys;
96};
97
98/*
99 * Routes in mt2701 and mt2712 are different. That means
100 * in the same register address, it controls different input/output
101 * selection for each SoC. But, right now, they use the same table as
102 * default routes meet their requirements. But we don't have the complete
103 * route information for these three SoC, so just keep them in the same
104 * table. After we've more information, we could separate mt2701, mt2712
105 * to an independent table.
106 */
107static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {
108	{
109		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
110		DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
111		BLS_TO_DSI_RDMA1_TO_DPI1
112	}, {
113		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
114		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
115		DSI_SEL_IN_BLS
116	}, {
117		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
118		DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
119		BLS_TO_DPI_RDMA1_TO_DSI
120	}, {
121		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
122		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
123		DSI_SEL_IN_RDMA
124	}, {
125		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
126		DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
127		DPI_SEL_IN_BLS
128	}, {
129		DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
130		DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
131		GAMMA_MOUT_EN_RDMA1
132	}, {
133		DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
134		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
135		OD_MOUT_EN_RDMA0
136	}, {
137		DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,
138		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
139		OD1_MOUT_EN_RDMA1
140	}, {
141		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
142		DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
143		OVL0_MOUT_EN_COLOR0
144	}, {
145		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
146		DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
147		COLOR0_SEL_IN_OVL0
148	}, {
149		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
150		DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
151		OVL_MOUT_EN_RDMA
152	}, {
153		DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
154		DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
155		OVL1_MOUT_EN_COLOR1
156	}, {
157		DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
158		DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
159		COLOR1_SEL_IN_OVL1
160	}, {
161		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0,
162		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
163		RDMA0_SOUT_DPI0
164	}, {
165		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1,
166		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
167		RDMA0_SOUT_DPI1
168	}, {
169		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1,
170		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
171		RDMA0_SOUT_DSI1
172	}, {
173		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2,
174		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
175		RDMA0_SOUT_DSI2
176	}, {
177		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3,
178		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
179		RDMA0_SOUT_DSI3
180	}, {
181		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
182		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
183		RDMA1_SOUT_DPI0
184	}, {
185		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
186		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
187		DPI0_SEL_IN_RDMA1
188	}, {
189		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
190		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
191		RDMA1_SOUT_DPI1
192	}, {
193		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
194		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
195		DPI1_SEL_IN_RDMA1
196	}, {
197		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0,
198		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
199		DSI0_SEL_IN_RDMA1
200	}, {
201		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
202		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
203		RDMA1_SOUT_DSI1
204	}, {
205		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
206		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
207		DSI1_SEL_IN_RDMA1
208	}, {
209		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
210		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
211		RDMA1_SOUT_DSI2
212	}, {
213		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
214		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
215		DSI2_SEL_IN_RDMA1
216	}, {
217		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
218		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
219		RDMA1_SOUT_DSI3
220	}, {
221		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
222		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
223		DSI3_SEL_IN_RDMA1
224	}, {
225		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
226		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
227		RDMA2_SOUT_DPI0
228	}, {
229		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
230		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
231		DPI0_SEL_IN_RDMA2
232	}, {
233		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
234		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
235		RDMA2_SOUT_DPI1
236	}, {
237		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
238		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
239		DPI1_SEL_IN_RDMA2
240	}, {
241		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0,
242		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
243		DSI0_SEL_IN_RDMA2
244	}, {
245		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
246		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
247		RDMA2_SOUT_DSI1
248	}, {
249		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
250		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
251		DSI1_SEL_IN_RDMA2
252	}, {
253		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
254		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
255		RDMA2_SOUT_DSI2
256	}, {
257		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
258		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
259		DSI2_SEL_IN_RDMA2
260	}, {
261		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
262		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
263		RDMA2_SOUT_DSI3
264	}, {
265		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
266		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
267		DSI3_SEL_IN_RDMA2
268	}, {
269		DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
270		DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0,
271		UFOE_MOUT_EN_DSI0
272	}
273};
274
275#endif /* __SOC_MEDIATEK_MTK_MMSYS_H */
276