162306a36Sopenharmony_ci/* 262306a36Sopenharmony_ci * This file is part of the Chelsio FCoE driver for Linux. 362306a36Sopenharmony_ci * 462306a36Sopenharmony_ci * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved. 562306a36Sopenharmony_ci * 662306a36Sopenharmony_ci * This software is available to you under a choice of one of two 762306a36Sopenharmony_ci * licenses. You may choose to be licensed under the terms of the GNU 862306a36Sopenharmony_ci * General Public License (GPL) Version 2, available from the file 962306a36Sopenharmony_ci * OpenIB.org BSD license below: 1062306a36Sopenharmony_ci * 1162306a36Sopenharmony_ci * Redistribution and use in source and binary forms, with or 1262306a36Sopenharmony_ci * without modification, are permitted provided that the following 1362306a36Sopenharmony_ci * conditions are met: 1462306a36Sopenharmony_ci * 1562306a36Sopenharmony_ci * - Redistributions of source code must retain the above 1662306a36Sopenharmony_ci * copyright notice, this list of conditions and the following 1762306a36Sopenharmony_ci * disclaimer. 1862306a36Sopenharmony_ci * 1962306a36Sopenharmony_ci * - Redistributions in binary form must reproduce the above 2062306a36Sopenharmony_ci * copyright notice, this list of conditions and the following 2162306a36Sopenharmony_ci * disclaimer in the documentation and/or other materials 2262306a36Sopenharmony_ci * provided with the distribution. 2362306a36Sopenharmony_ci * 2462306a36Sopenharmony_ci * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 2562306a36Sopenharmony_ci * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 2662306a36Sopenharmony_ci * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 2762306a36Sopenharmony_ci * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 2862306a36Sopenharmony_ci * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 2962306a36Sopenharmony_ci * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 3062306a36Sopenharmony_ci * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 3162306a36Sopenharmony_ci * SOFTWARE. 3262306a36Sopenharmony_ci */ 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ci#include "csio_hw.h" 3562306a36Sopenharmony_ci#include "csio_init.h" 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_cistatic int 3862306a36Sopenharmony_cicsio_t5_set_mem_win(struct csio_hw *hw, uint32_t win) 3962306a36Sopenharmony_ci{ 4062306a36Sopenharmony_ci u32 mem_win_base; 4162306a36Sopenharmony_ci /* 4262306a36Sopenharmony_ci * Truncation intentional: we only read the bottom 32-bits of the 4362306a36Sopenharmony_ci * 64-bit BAR0/BAR1 ... We use the hardware backdoor mechanism to 4462306a36Sopenharmony_ci * read BAR0 instead of using pci_resource_start() because we could be 4562306a36Sopenharmony_ci * operating from within a Virtual Machine which is trapping our 4662306a36Sopenharmony_ci * accesses to our Configuration Space and we need to set up the PCI-E 4762306a36Sopenharmony_ci * Memory Window decoders with the actual addresses which will be 4862306a36Sopenharmony_ci * coming across the PCI-E link. 4962306a36Sopenharmony_ci */ 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_ci /* For T5, only relative offset inside the PCIe BAR is passed */ 5262306a36Sopenharmony_ci mem_win_base = MEMWIN_BASE; 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ci /* 5562306a36Sopenharmony_ci * Set up memory window for accessing adapter memory ranges. (Read 5662306a36Sopenharmony_ci * back MA register to ensure that changes propagate before we attempt 5762306a36Sopenharmony_ci * to use the new values.) 5862306a36Sopenharmony_ci */ 5962306a36Sopenharmony_ci csio_wr_reg32(hw, mem_win_base | BIR_V(0) | 6062306a36Sopenharmony_ci WINDOW_V(ilog2(MEMWIN_APERTURE) - 10), 6162306a36Sopenharmony_ci PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win)); 6262306a36Sopenharmony_ci csio_rd_reg32(hw, 6362306a36Sopenharmony_ci PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win)); 6462306a36Sopenharmony_ci 6562306a36Sopenharmony_ci return 0; 6662306a36Sopenharmony_ci} 6762306a36Sopenharmony_ci 6862306a36Sopenharmony_ci/* 6962306a36Sopenharmony_ci * Interrupt handler for the PCIE module. 7062306a36Sopenharmony_ci */ 7162306a36Sopenharmony_cistatic void 7262306a36Sopenharmony_cicsio_t5_pcie_intr_handler(struct csio_hw *hw) 7362306a36Sopenharmony_ci{ 7462306a36Sopenharmony_ci static struct intr_info pcie_intr_info[] = { 7562306a36Sopenharmony_ci { MSTGRPPERR_F, "Master Response Read Queue parity error", 7662306a36Sopenharmony_ci -1, 1 }, 7762306a36Sopenharmony_ci { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 }, 7862306a36Sopenharmony_ci { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 }, 7962306a36Sopenharmony_ci { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 }, 8062306a36Sopenharmony_ci { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 }, 8162306a36Sopenharmony_ci { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 }, 8262306a36Sopenharmony_ci { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 }, 8362306a36Sopenharmony_ci { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error", 8462306a36Sopenharmony_ci -1, 1 }, 8562306a36Sopenharmony_ci { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error", 8662306a36Sopenharmony_ci -1, 1 }, 8762306a36Sopenharmony_ci { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 }, 8862306a36Sopenharmony_ci { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 }, 8962306a36Sopenharmony_ci { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 }, 9062306a36Sopenharmony_ci { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 }, 9162306a36Sopenharmony_ci { DREQWRPERR_F, "PCI DMA channel write request parity error", 9262306a36Sopenharmony_ci -1, 1 }, 9362306a36Sopenharmony_ci { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 }, 9462306a36Sopenharmony_ci { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 }, 9562306a36Sopenharmony_ci { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 }, 9662306a36Sopenharmony_ci { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 }, 9762306a36Sopenharmony_ci { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 }, 9862306a36Sopenharmony_ci { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 }, 9962306a36Sopenharmony_ci { FIDPERR_F, "PCI FID parity error", -1, 1 }, 10062306a36Sopenharmony_ci { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 }, 10162306a36Sopenharmony_ci { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 }, 10262306a36Sopenharmony_ci { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 }, 10362306a36Sopenharmony_ci { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error", 10462306a36Sopenharmony_ci -1, 1 }, 10562306a36Sopenharmony_ci { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error", 10662306a36Sopenharmony_ci -1, 1 }, 10762306a36Sopenharmony_ci { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 }, 10862306a36Sopenharmony_ci { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 }, 10962306a36Sopenharmony_ci { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 }, 11062306a36Sopenharmony_ci { READRSPERR_F, "Outbound read error", -1, 0 }, 11162306a36Sopenharmony_ci { 0, NULL, 0, 0 } 11262306a36Sopenharmony_ci }; 11362306a36Sopenharmony_ci 11462306a36Sopenharmony_ci int fat; 11562306a36Sopenharmony_ci fat = csio_handle_intr_status(hw, PCIE_INT_CAUSE_A, pcie_intr_info); 11662306a36Sopenharmony_ci if (fat) 11762306a36Sopenharmony_ci csio_hw_fatal_err(hw); 11862306a36Sopenharmony_ci} 11962306a36Sopenharmony_ci 12062306a36Sopenharmony_ci/* 12162306a36Sopenharmony_ci * csio_t5_flash_cfg_addr - return the address of the flash configuration file 12262306a36Sopenharmony_ci * @hw: the HW module 12362306a36Sopenharmony_ci * 12462306a36Sopenharmony_ci * Return the address within the flash where the Firmware Configuration 12562306a36Sopenharmony_ci * File is stored. 12662306a36Sopenharmony_ci */ 12762306a36Sopenharmony_cistatic unsigned int 12862306a36Sopenharmony_cicsio_t5_flash_cfg_addr(struct csio_hw *hw) 12962306a36Sopenharmony_ci{ 13062306a36Sopenharmony_ci return FLASH_CFG_START; 13162306a36Sopenharmony_ci} 13262306a36Sopenharmony_ci 13362306a36Sopenharmony_ci/* 13462306a36Sopenharmony_ci * csio_t5_mc_read - read from MC through backdoor accesses 13562306a36Sopenharmony_ci * @hw: the hw module 13662306a36Sopenharmony_ci * @idx: index to the register 13762306a36Sopenharmony_ci * @addr: address of first byte requested 13862306a36Sopenharmony_ci * @data: 64 bytes of data containing the requested address 13962306a36Sopenharmony_ci * @ecc: where to store the corresponding 64-bit ECC word 14062306a36Sopenharmony_ci * 14162306a36Sopenharmony_ci * Read 64 bytes of data from MC starting at a 64-byte-aligned address 14262306a36Sopenharmony_ci * that covers the requested address @addr. If @parity is not %NULL it 14362306a36Sopenharmony_ci * is assigned the 64-bit ECC word for the read data. 14462306a36Sopenharmony_ci */ 14562306a36Sopenharmony_cistatic int 14662306a36Sopenharmony_cicsio_t5_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data, 14762306a36Sopenharmony_ci uint64_t *ecc) 14862306a36Sopenharmony_ci{ 14962306a36Sopenharmony_ci int i; 15062306a36Sopenharmony_ci uint32_t mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 15162306a36Sopenharmony_ci uint32_t mc_bist_data_pattern_reg; 15262306a36Sopenharmony_ci 15362306a36Sopenharmony_ci mc_bist_cmd_reg = MC_REG(MC_P_BIST_CMD_A, idx); 15462306a36Sopenharmony_ci mc_bist_cmd_addr_reg = MC_REG(MC_P_BIST_CMD_ADDR_A, idx); 15562306a36Sopenharmony_ci mc_bist_cmd_len_reg = MC_REG(MC_P_BIST_CMD_LEN_A, idx); 15662306a36Sopenharmony_ci mc_bist_data_pattern_reg = MC_REG(MC_P_BIST_DATA_PATTERN_A, idx); 15762306a36Sopenharmony_ci 15862306a36Sopenharmony_ci if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST_F) 15962306a36Sopenharmony_ci return -EBUSY; 16062306a36Sopenharmony_ci csio_wr_reg32(hw, addr & ~0x3fU, mc_bist_cmd_addr_reg); 16162306a36Sopenharmony_ci csio_wr_reg32(hw, 64, mc_bist_cmd_len_reg); 16262306a36Sopenharmony_ci csio_wr_reg32(hw, 0xc, mc_bist_data_pattern_reg); 16362306a36Sopenharmony_ci csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F | BIST_CMD_GAP_V(1), 16462306a36Sopenharmony_ci mc_bist_cmd_reg); 16562306a36Sopenharmony_ci i = csio_hw_wait_op_done_val(hw, mc_bist_cmd_reg, START_BIST_F, 16662306a36Sopenharmony_ci 0, 10, 1, NULL); 16762306a36Sopenharmony_ci if (i) 16862306a36Sopenharmony_ci return i; 16962306a36Sopenharmony_ci 17062306a36Sopenharmony_ci#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA_A, i) 17162306a36Sopenharmony_ci 17262306a36Sopenharmony_ci for (i = 15; i >= 0; i--) 17362306a36Sopenharmony_ci *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i))); 17462306a36Sopenharmony_ci if (ecc) 17562306a36Sopenharmony_ci *ecc = csio_rd_reg64(hw, MC_DATA(16)); 17662306a36Sopenharmony_ci#undef MC_DATA 17762306a36Sopenharmony_ci return 0; 17862306a36Sopenharmony_ci} 17962306a36Sopenharmony_ci 18062306a36Sopenharmony_ci/* 18162306a36Sopenharmony_ci * csio_t5_edc_read - read from EDC through backdoor accesses 18262306a36Sopenharmony_ci * @hw: the hw module 18362306a36Sopenharmony_ci * @idx: which EDC to access 18462306a36Sopenharmony_ci * @addr: address of first byte requested 18562306a36Sopenharmony_ci * @data: 64 bytes of data containing the requested address 18662306a36Sopenharmony_ci * @ecc: where to store the corresponding 64-bit ECC word 18762306a36Sopenharmony_ci * 18862306a36Sopenharmony_ci * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 18962306a36Sopenharmony_ci * that covers the requested address @addr. If @parity is not %NULL it 19062306a36Sopenharmony_ci * is assigned the 64-bit ECC word for the read data. 19162306a36Sopenharmony_ci */ 19262306a36Sopenharmony_cistatic int 19362306a36Sopenharmony_cicsio_t5_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data, 19462306a36Sopenharmony_ci uint64_t *ecc) 19562306a36Sopenharmony_ci{ 19662306a36Sopenharmony_ci int i; 19762306a36Sopenharmony_ci uint32_t edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 19862306a36Sopenharmony_ci uint32_t edc_bist_cmd_data_pattern; 19962306a36Sopenharmony_ci 20062306a36Sopenharmony_ci/* 20162306a36Sopenharmony_ci * These macro are missing in t4_regs.h file. 20262306a36Sopenharmony_ci */ 20362306a36Sopenharmony_ci#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 20462306a36Sopenharmony_ci#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 20562306a36Sopenharmony_ci 20662306a36Sopenharmony_ci edc_bist_cmd_reg = EDC_REG_T5(EDC_H_BIST_CMD_A, idx); 20762306a36Sopenharmony_ci edc_bist_cmd_addr_reg = EDC_REG_T5(EDC_H_BIST_CMD_ADDR_A, idx); 20862306a36Sopenharmony_ci edc_bist_cmd_len_reg = EDC_REG_T5(EDC_H_BIST_CMD_LEN_A, idx); 20962306a36Sopenharmony_ci edc_bist_cmd_data_pattern = EDC_REG_T5(EDC_H_BIST_DATA_PATTERN_A, idx); 21062306a36Sopenharmony_ci#undef EDC_REG_T5 21162306a36Sopenharmony_ci#undef EDC_STRIDE_T5 21262306a36Sopenharmony_ci 21362306a36Sopenharmony_ci if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST_F) 21462306a36Sopenharmony_ci return -EBUSY; 21562306a36Sopenharmony_ci csio_wr_reg32(hw, addr & ~0x3fU, edc_bist_cmd_addr_reg); 21662306a36Sopenharmony_ci csio_wr_reg32(hw, 64, edc_bist_cmd_len_reg); 21762306a36Sopenharmony_ci csio_wr_reg32(hw, 0xc, edc_bist_cmd_data_pattern); 21862306a36Sopenharmony_ci csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F | BIST_CMD_GAP_V(1), 21962306a36Sopenharmony_ci edc_bist_cmd_reg); 22062306a36Sopenharmony_ci i = csio_hw_wait_op_done_val(hw, edc_bist_cmd_reg, START_BIST_F, 22162306a36Sopenharmony_ci 0, 10, 1, NULL); 22262306a36Sopenharmony_ci if (i) 22362306a36Sopenharmony_ci return i; 22462306a36Sopenharmony_ci 22562306a36Sopenharmony_ci#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA_A, i) + idx) 22662306a36Sopenharmony_ci 22762306a36Sopenharmony_ci for (i = 15; i >= 0; i--) 22862306a36Sopenharmony_ci *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i))); 22962306a36Sopenharmony_ci if (ecc) 23062306a36Sopenharmony_ci *ecc = csio_rd_reg64(hw, EDC_DATA(16)); 23162306a36Sopenharmony_ci#undef EDC_DATA 23262306a36Sopenharmony_ci return 0; 23362306a36Sopenharmony_ci} 23462306a36Sopenharmony_ci 23562306a36Sopenharmony_ci/* 23662306a36Sopenharmony_ci * csio_t5_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window 23762306a36Sopenharmony_ci * @hw: the csio_hw 23862306a36Sopenharmony_ci * @win: PCI-E memory Window to use 23962306a36Sopenharmony_ci * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_MC0 (or MEM_MC) or MEM_MC1 24062306a36Sopenharmony_ci * @addr: address within indicated memory type 24162306a36Sopenharmony_ci * @len: amount of memory to transfer 24262306a36Sopenharmony_ci * @buf: host memory buffer 24362306a36Sopenharmony_ci * @dir: direction of transfer 1 => read, 0 => write 24462306a36Sopenharmony_ci * 24562306a36Sopenharmony_ci * Reads/writes an [almost] arbitrary memory region in the firmware: the 24662306a36Sopenharmony_ci * firmware memory address, length and host buffer must be aligned on 24762306a36Sopenharmony_ci * 32-bit boundaries. The memory is transferred as a raw byte sequence 24862306a36Sopenharmony_ci * from/to the firmware's memory. If this memory contains data 24962306a36Sopenharmony_ci * structures which contain multi-byte integers, it's the callers 25062306a36Sopenharmony_ci * responsibility to perform appropriate byte order conversions. 25162306a36Sopenharmony_ci */ 25262306a36Sopenharmony_cistatic int 25362306a36Sopenharmony_cicsio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr, 25462306a36Sopenharmony_ci u32 len, uint32_t *buf, int dir) 25562306a36Sopenharmony_ci{ 25662306a36Sopenharmony_ci u32 pos, start, offset, memoffset; 25762306a36Sopenharmony_ci u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base; 25862306a36Sopenharmony_ci 25962306a36Sopenharmony_ci /* 26062306a36Sopenharmony_ci * Argument sanity checks ... 26162306a36Sopenharmony_ci */ 26262306a36Sopenharmony_ci if ((addr & 0x3) || (len & 0x3)) 26362306a36Sopenharmony_ci return -EINVAL; 26462306a36Sopenharmony_ci 26562306a36Sopenharmony_ci /* Offset into the region of memory which is being accessed 26662306a36Sopenharmony_ci * MEM_EDC0 = 0 26762306a36Sopenharmony_ci * MEM_EDC1 = 1 26862306a36Sopenharmony_ci * MEM_MC = 2 -- T4 26962306a36Sopenharmony_ci * MEM_MC0 = 2 -- For T5 27062306a36Sopenharmony_ci * MEM_MC1 = 3 -- For T5 27162306a36Sopenharmony_ci */ 27262306a36Sopenharmony_ci edc_size = EDRAM0_SIZE_G(csio_rd_reg32(hw, MA_EDRAM0_BAR_A)); 27362306a36Sopenharmony_ci if (mtype != MEM_MC1) 27462306a36Sopenharmony_ci memoffset = (mtype * (edc_size * 1024 * 1024)); 27562306a36Sopenharmony_ci else { 27662306a36Sopenharmony_ci mc_size = EXT_MEM_SIZE_G(csio_rd_reg32(hw, 27762306a36Sopenharmony_ci MA_EXT_MEMORY_BAR_A)); 27862306a36Sopenharmony_ci memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024; 27962306a36Sopenharmony_ci } 28062306a36Sopenharmony_ci 28162306a36Sopenharmony_ci /* Determine the PCIE_MEM_ACCESS_OFFSET */ 28262306a36Sopenharmony_ci addr = addr + memoffset; 28362306a36Sopenharmony_ci 28462306a36Sopenharmony_ci /* 28562306a36Sopenharmony_ci * Each PCI-E Memory Window is programmed with a window size -- or 28662306a36Sopenharmony_ci * "aperture" -- which controls the granularity of its mapping onto 28762306a36Sopenharmony_ci * adapter memory. We need to grab that aperture in order to know 28862306a36Sopenharmony_ci * how to use the specified window. The window is also programmed 28962306a36Sopenharmony_ci * with the base address of the Memory Window in BAR0's address 29062306a36Sopenharmony_ci * space. For T4 this is an absolute PCI-E Bus Address. For T5 29162306a36Sopenharmony_ci * the address is relative to BAR0. 29262306a36Sopenharmony_ci */ 29362306a36Sopenharmony_ci mem_reg = csio_rd_reg32(hw, 29462306a36Sopenharmony_ci PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win)); 29562306a36Sopenharmony_ci mem_aperture = 1 << (WINDOW_V(mem_reg) + 10); 29662306a36Sopenharmony_ci mem_base = PCIEOFST_G(mem_reg) << 10; 29762306a36Sopenharmony_ci 29862306a36Sopenharmony_ci start = addr & ~(mem_aperture-1); 29962306a36Sopenharmony_ci offset = addr - start; 30062306a36Sopenharmony_ci win_pf = PFNUM_V(hw->pfn); 30162306a36Sopenharmony_ci 30262306a36Sopenharmony_ci csio_dbg(hw, "csio_t5_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n", 30362306a36Sopenharmony_ci mem_reg, mem_aperture); 30462306a36Sopenharmony_ci csio_dbg(hw, "csio_t5_memory_rw: mem_base: 0x%x, mem_offset: 0x%x\n", 30562306a36Sopenharmony_ci mem_base, memoffset); 30662306a36Sopenharmony_ci csio_dbg(hw, "csio_t5_memory_rw: start:0x%x, offset:0x%x, win_pf:%d\n", 30762306a36Sopenharmony_ci start, offset, win_pf); 30862306a36Sopenharmony_ci csio_dbg(hw, "csio_t5_memory_rw: mtype: %d, addr: 0x%x, len: %d\n", 30962306a36Sopenharmony_ci mtype, addr, len); 31062306a36Sopenharmony_ci 31162306a36Sopenharmony_ci for (pos = start; len > 0; pos += mem_aperture, offset = 0) { 31262306a36Sopenharmony_ci /* 31362306a36Sopenharmony_ci * Move PCI-E Memory Window to our current transfer 31462306a36Sopenharmony_ci * position. Read it back to ensure that changes propagate 31562306a36Sopenharmony_ci * before we attempt to use the new value. 31662306a36Sopenharmony_ci */ 31762306a36Sopenharmony_ci csio_wr_reg32(hw, pos | win_pf, 31862306a36Sopenharmony_ci PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win)); 31962306a36Sopenharmony_ci csio_rd_reg32(hw, 32062306a36Sopenharmony_ci PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win)); 32162306a36Sopenharmony_ci 32262306a36Sopenharmony_ci while (offset < mem_aperture && len > 0) { 32362306a36Sopenharmony_ci if (dir) 32462306a36Sopenharmony_ci *buf++ = csio_rd_reg32(hw, mem_base + offset); 32562306a36Sopenharmony_ci else 32662306a36Sopenharmony_ci csio_wr_reg32(hw, *buf++, mem_base + offset); 32762306a36Sopenharmony_ci 32862306a36Sopenharmony_ci offset += sizeof(__be32); 32962306a36Sopenharmony_ci len -= sizeof(__be32); 33062306a36Sopenharmony_ci } 33162306a36Sopenharmony_ci } 33262306a36Sopenharmony_ci return 0; 33362306a36Sopenharmony_ci} 33462306a36Sopenharmony_ci 33562306a36Sopenharmony_ci/* 33662306a36Sopenharmony_ci * csio_t5_dfs_create_ext_mem - setup debugfs for MC0 or MC1 to read the values 33762306a36Sopenharmony_ci * @hw: the csio_hw 33862306a36Sopenharmony_ci * 33962306a36Sopenharmony_ci * This function creates files in the debugfs with external memory region 34062306a36Sopenharmony_ci * MC0 & MC1. 34162306a36Sopenharmony_ci */ 34262306a36Sopenharmony_cistatic void 34362306a36Sopenharmony_cicsio_t5_dfs_create_ext_mem(struct csio_hw *hw) 34462306a36Sopenharmony_ci{ 34562306a36Sopenharmony_ci u32 size; 34662306a36Sopenharmony_ci int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A); 34762306a36Sopenharmony_ci 34862306a36Sopenharmony_ci if (i & EXT_MEM_ENABLE_F) { 34962306a36Sopenharmony_ci size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR_A); 35062306a36Sopenharmony_ci csio_add_debugfs_mem(hw, "mc0", MEM_MC0, 35162306a36Sopenharmony_ci EXT_MEM_SIZE_G(size)); 35262306a36Sopenharmony_ci } 35362306a36Sopenharmony_ci if (i & EXT_MEM1_ENABLE_F) { 35462306a36Sopenharmony_ci size = csio_rd_reg32(hw, MA_EXT_MEMORY1_BAR_A); 35562306a36Sopenharmony_ci csio_add_debugfs_mem(hw, "mc1", MEM_MC1, 35662306a36Sopenharmony_ci EXT_MEM_SIZE_G(size)); 35762306a36Sopenharmony_ci } 35862306a36Sopenharmony_ci} 35962306a36Sopenharmony_ci 36062306a36Sopenharmony_ci/* T5 adapter specific function */ 36162306a36Sopenharmony_cistruct csio_hw_chip_ops t5_ops = { 36262306a36Sopenharmony_ci .chip_set_mem_win = csio_t5_set_mem_win, 36362306a36Sopenharmony_ci .chip_pcie_intr_handler = csio_t5_pcie_intr_handler, 36462306a36Sopenharmony_ci .chip_flash_cfg_addr = csio_t5_flash_cfg_addr, 36562306a36Sopenharmony_ci .chip_mc_read = csio_t5_mc_read, 36662306a36Sopenharmony_ci .chip_edc_read = csio_t5_edc_read, 36762306a36Sopenharmony_ci .chip_memory_rw = csio_t5_memory_rw, 36862306a36Sopenharmony_ci .chip_dfs_create_ext_mem = csio_t5_dfs_create_ext_mem, 36962306a36Sopenharmony_ci}; 370