162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-or-later
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Reset driver for the StarFive JH7100 SoC
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
662306a36Sopenharmony_ci */
762306a36Sopenharmony_ci
862306a36Sopenharmony_ci#include <linux/mod_devicetable.h>
962306a36Sopenharmony_ci#include <linux/platform_device.h>
1062306a36Sopenharmony_ci
1162306a36Sopenharmony_ci#include "reset-starfive-jh71x0.h"
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ci#include <dt-bindings/reset/starfive-jh7100.h>
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_ci/* register offsets */
1662306a36Sopenharmony_ci#define JH7100_RESET_ASSERT0	0x00
1762306a36Sopenharmony_ci#define JH7100_RESET_ASSERT1	0x04
1862306a36Sopenharmony_ci#define JH7100_RESET_ASSERT2	0x08
1962306a36Sopenharmony_ci#define JH7100_RESET_ASSERT3	0x0c
2062306a36Sopenharmony_ci#define JH7100_RESET_STATUS0	0x10
2162306a36Sopenharmony_ci#define JH7100_RESET_STATUS1	0x14
2262306a36Sopenharmony_ci#define JH7100_RESET_STATUS2	0x18
2362306a36Sopenharmony_ci#define JH7100_RESET_STATUS3	0x1c
2462306a36Sopenharmony_ci
2562306a36Sopenharmony_ci/*
2662306a36Sopenharmony_ci * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
2762306a36Sopenharmony_ci * line 32m + n, and writing a 0 deasserts the same line.
2862306a36Sopenharmony_ci * Most reset lines have their status inverted so a 0 bit in the STATUS
2962306a36Sopenharmony_ci * register means the line is asserted and a 1 means it's deasserted. A few
3062306a36Sopenharmony_ci * lines don't though, so store the expected value of the status registers when
3162306a36Sopenharmony_ci * all lines are asserted.
3262306a36Sopenharmony_ci */
3362306a36Sopenharmony_cistatic const u32 jh7100_reset_asserted[4] = {
3462306a36Sopenharmony_ci	/* STATUS0 */
3562306a36Sopenharmony_ci	BIT(JH7100_RST_U74 % 32) |
3662306a36Sopenharmony_ci	BIT(JH7100_RST_VP6_DRESET % 32) |
3762306a36Sopenharmony_ci	BIT(JH7100_RST_VP6_BRESET % 32),
3862306a36Sopenharmony_ci	/* STATUS1 */
3962306a36Sopenharmony_ci	BIT(JH7100_RST_HIFI4_DRESET % 32) |
4062306a36Sopenharmony_ci	BIT(JH7100_RST_HIFI4_BRESET % 32),
4162306a36Sopenharmony_ci	/* STATUS2 */
4262306a36Sopenharmony_ci	BIT(JH7100_RST_E24 % 32),
4362306a36Sopenharmony_ci	/* STATUS3 */
4462306a36Sopenharmony_ci	0,
4562306a36Sopenharmony_ci};
4662306a36Sopenharmony_ci
4762306a36Sopenharmony_cistatic int __init jh7100_reset_probe(struct platform_device *pdev)
4862306a36Sopenharmony_ci{
4962306a36Sopenharmony_ci	void __iomem *base = devm_platform_ioremap_resource(pdev, 0);
5062306a36Sopenharmony_ci
5162306a36Sopenharmony_ci	if (IS_ERR(base))
5262306a36Sopenharmony_ci		return PTR_ERR(base);
5362306a36Sopenharmony_ci
5462306a36Sopenharmony_ci	return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node,
5562306a36Sopenharmony_ci					      base + JH7100_RESET_ASSERT0,
5662306a36Sopenharmony_ci					      base + JH7100_RESET_STATUS0,
5762306a36Sopenharmony_ci					      jh7100_reset_asserted,
5862306a36Sopenharmony_ci					      JH7100_RSTN_END,
5962306a36Sopenharmony_ci					      THIS_MODULE);
6062306a36Sopenharmony_ci}
6162306a36Sopenharmony_ci
6262306a36Sopenharmony_cistatic const struct of_device_id jh7100_reset_dt_ids[] = {
6362306a36Sopenharmony_ci	{ .compatible = "starfive,jh7100-reset" },
6462306a36Sopenharmony_ci	{ /* sentinel */ }
6562306a36Sopenharmony_ci};
6662306a36Sopenharmony_ci
6762306a36Sopenharmony_cistatic struct platform_driver jh7100_reset_driver = {
6862306a36Sopenharmony_ci	.driver = {
6962306a36Sopenharmony_ci		.name = "jh7100-reset",
7062306a36Sopenharmony_ci		.of_match_table = jh7100_reset_dt_ids,
7162306a36Sopenharmony_ci		.suppress_bind_attrs = true,
7262306a36Sopenharmony_ci	},
7362306a36Sopenharmony_ci};
7462306a36Sopenharmony_cibuiltin_platform_driver_probe(jh7100_reset_driver, jh7100_reset_probe);
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