162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> 462306a36Sopenharmony_ci * Copyright 2021 NXP 562306a36Sopenharmony_ci */ 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci#ifndef _IMX_RPROC_H 862306a36Sopenharmony_ci#define _IMX_RPROC_H 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci/* address translation table */ 1162306a36Sopenharmony_cistruct imx_rproc_att { 1262306a36Sopenharmony_ci u32 da; /* device address (From Cortex M4 view)*/ 1362306a36Sopenharmony_ci u32 sa; /* system bus address */ 1462306a36Sopenharmony_ci u32 size; /* size of reg range */ 1562306a36Sopenharmony_ci int flags; 1662306a36Sopenharmony_ci}; 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci/* Remote core start/stop method */ 1962306a36Sopenharmony_cienum imx_rproc_method { 2062306a36Sopenharmony_ci IMX_RPROC_NONE, 2162306a36Sopenharmony_ci /* Through syscon regmap */ 2262306a36Sopenharmony_ci IMX_RPROC_MMIO, 2362306a36Sopenharmony_ci /* Through ARM SMCCC */ 2462306a36Sopenharmony_ci IMX_RPROC_SMC, 2562306a36Sopenharmony_ci /* Through System Control Unit API */ 2662306a36Sopenharmony_ci IMX_RPROC_SCU_API, 2762306a36Sopenharmony_ci}; 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_cistruct imx_rproc_dcfg { 3062306a36Sopenharmony_ci u32 src_reg; 3162306a36Sopenharmony_ci u32 src_mask; 3262306a36Sopenharmony_ci u32 src_start; 3362306a36Sopenharmony_ci u32 src_stop; 3462306a36Sopenharmony_ci u32 gpr_reg; 3562306a36Sopenharmony_ci u32 gpr_wait; 3662306a36Sopenharmony_ci const struct imx_rproc_att *att; 3762306a36Sopenharmony_ci size_t att_size; 3862306a36Sopenharmony_ci enum imx_rproc_method method; 3962306a36Sopenharmony_ci}; 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ci#endif /* _IMX_RPROC_H */ 42