1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright 2021 NXP */ 3 4#include <dt-bindings/firmware/imx/rsrc.h> 5#include <linux/arm-smccc.h> 6#include <linux/clk.h> 7#include <linux/err.h> 8#include <linux/firmware.h> 9#include <linux/firmware/imx/sci.h> 10#include <linux/interrupt.h> 11#include <linux/kernel.h> 12#include <linux/mailbox_client.h> 13#include <linux/mfd/syscon.h> 14#include <linux/module.h> 15#include <linux/of.h> 16#include <linux/of_reserved_mem.h> 17#include <linux/platform_device.h> 18#include <linux/pm_domain.h> 19#include <linux/pm_runtime.h> 20#include <linux/regmap.h> 21#include <linux/remoteproc.h> 22#include <linux/slab.h> 23 24#include "imx_rproc.h" 25#include "remoteproc_elf_helpers.h" 26#include "remoteproc_internal.h" 27 28#define DSP_RPROC_CLK_MAX 5 29 30/* 31 * Module parameters 32 */ 33static unsigned int no_mailboxes; 34module_param_named(no_mailboxes, no_mailboxes, int, 0644); 35MODULE_PARM_DESC(no_mailboxes, 36 "There is no mailbox between cores, so ignore remote proc reply after start, default is 0 (off)."); 37 38#define REMOTE_IS_READY BIT(0) 39#define REMOTE_READY_WAIT_MAX_RETRIES 500 40 41/* att flags */ 42/* DSP own area */ 43#define ATT_OWN BIT(31) 44/* DSP instruction area */ 45#define ATT_IRAM BIT(30) 46 47/* Definitions for i.MX8MP */ 48/* DAP registers */ 49#define IMX8M_DAP_DEBUG 0x28800000 50#define IMX8M_DAP_DEBUG_SIZE (64 * 1024) 51#define IMX8M_DAP_PWRCTL (0x4000 + 0x3020) 52#define IMX8M_PWRCTL_CORERESET BIT(16) 53 54/* DSP audio mix registers */ 55#define IMX8M_AudioDSP_REG0 0x100 56#define IMX8M_AudioDSP_REG1 0x104 57#define IMX8M_AudioDSP_REG2 0x108 58#define IMX8M_AudioDSP_REG3 0x10c 59 60#define IMX8M_AudioDSP_REG2_RUNSTALL BIT(5) 61#define IMX8M_AudioDSP_REG2_PWAITMODE BIT(1) 62 63/* Definitions for i.MX8ULP */ 64#define IMX8ULP_SIM_LPAV_REG_SYSCTRL0 0x8 65#define IMX8ULP_SYSCTRL0_DSP_DBG_RST BIT(25) 66#define IMX8ULP_SYSCTRL0_DSP_PLAT_CLK_EN BIT(19) 67#define IMX8ULP_SYSCTRL0_DSP_PBCLK_EN BIT(18) 68#define IMX8ULP_SYSCTRL0_DSP_CLK_EN BIT(17) 69#define IMX8ULP_SYSCTRL0_DSP_RST BIT(16) 70#define IMX8ULP_SYSCTRL0_DSP_OCD_HALT BIT(14) 71#define IMX8ULP_SYSCTRL0_DSP_STALL BIT(13) 72 73#define IMX8ULP_SIP_HIFI_XRDC 0xc200000e 74 75/* 76 * enum - Predefined Mailbox Messages 77 * 78 * @RP_MBOX_SUSPEND_SYSTEM: system suspend request for the remote processor 79 * 80 * @RP_MBOX_SUSPEND_ACK: successful response from remote processor for a 81 * suspend request 82 * 83 * @RP_MBOX_RESUME_SYSTEM: system resume request for the remote processor 84 * 85 * @RP_MBOX_RESUME_ACK: successful response from remote processor for a 86 * resume request 87 */ 88enum imx_dsp_rp_mbox_messages { 89 RP_MBOX_SUSPEND_SYSTEM = 0xFF11, 90 RP_MBOX_SUSPEND_ACK = 0xFF12, 91 RP_MBOX_RESUME_SYSTEM = 0xFF13, 92 RP_MBOX_RESUME_ACK = 0xFF14, 93}; 94 95/** 96 * struct imx_dsp_rproc - DSP remote processor state 97 * @regmap: regmap handler 98 * @rproc: rproc handler 99 * @dsp_dcfg: device configuration pointer 100 * @clks: clocks needed by this device 101 * @cl: mailbox client to request the mailbox channel 102 * @cl_rxdb: mailbox client to request the mailbox channel for doorbell 103 * @tx_ch: mailbox tx channel handle 104 * @rx_ch: mailbox rx channel handle 105 * @rxdb_ch: mailbox rx doorbell channel handle 106 * @pd_dev: power domain device 107 * @pd_dev_link: power domain device link 108 * @ipc_handle: System Control Unit ipc handle 109 * @rproc_work: work for processing virtio interrupts 110 * @pm_comp: completion primitive to sync for suspend response 111 * @num_domains: power domain number 112 * @flags: control flags 113 */ 114struct imx_dsp_rproc { 115 struct regmap *regmap; 116 struct rproc *rproc; 117 const struct imx_dsp_rproc_dcfg *dsp_dcfg; 118 struct clk_bulk_data clks[DSP_RPROC_CLK_MAX]; 119 struct mbox_client cl; 120 struct mbox_client cl_rxdb; 121 struct mbox_chan *tx_ch; 122 struct mbox_chan *rx_ch; 123 struct mbox_chan *rxdb_ch; 124 struct device **pd_dev; 125 struct device_link **pd_dev_link; 126 struct imx_sc_ipc *ipc_handle; 127 struct work_struct rproc_work; 128 struct completion pm_comp; 129 int num_domains; 130 u32 flags; 131}; 132 133/** 134 * struct imx_dsp_rproc_dcfg - DSP remote processor configuration 135 * @dcfg: imx_rproc_dcfg handler 136 * @reset: reset callback function 137 */ 138struct imx_dsp_rproc_dcfg { 139 const struct imx_rproc_dcfg *dcfg; 140 int (*reset)(struct imx_dsp_rproc *priv); 141}; 142 143static const struct imx_rproc_att imx_dsp_rproc_att_imx8qm[] = { 144 /* dev addr , sys addr , size , flags */ 145 { 0x596e8000, 0x556e8000, 0x00008000, ATT_OWN }, 146 { 0x596f0000, 0x556f0000, 0x00008000, ATT_OWN }, 147 { 0x596f8000, 0x556f8000, 0x00000800, ATT_OWN | ATT_IRAM}, 148 { 0x55700000, 0x55700000, 0x00070000, ATT_OWN }, 149 /* DDR (Data) */ 150 { 0x80000000, 0x80000000, 0x60000000, 0}, 151}; 152 153static const struct imx_rproc_att imx_dsp_rproc_att_imx8qxp[] = { 154 /* dev addr , sys addr , size , flags */ 155 { 0x596e8000, 0x596e8000, 0x00008000, ATT_OWN }, 156 { 0x596f0000, 0x596f0000, 0x00008000, ATT_OWN }, 157 { 0x596f8000, 0x596f8000, 0x00000800, ATT_OWN | ATT_IRAM}, 158 { 0x59700000, 0x59700000, 0x00070000, ATT_OWN }, 159 /* DDR (Data) */ 160 { 0x80000000, 0x80000000, 0x60000000, 0}, 161}; 162 163static const struct imx_rproc_att imx_dsp_rproc_att_imx8mp[] = { 164 /* dev addr , sys addr , size , flags */ 165 { 0x3b6e8000, 0x3b6e8000, 0x00008000, ATT_OWN }, 166 { 0x3b6f0000, 0x3b6f0000, 0x00008000, ATT_OWN }, 167 { 0x3b6f8000, 0x3b6f8000, 0x00000800, ATT_OWN | ATT_IRAM}, 168 { 0x3b700000, 0x3b700000, 0x00040000, ATT_OWN }, 169 /* DDR (Data) */ 170 { 0x40000000, 0x40000000, 0x80000000, 0}, 171}; 172 173static const struct imx_rproc_att imx_dsp_rproc_att_imx8ulp[] = { 174 /* dev addr , sys addr , size , flags */ 175 { 0x21170000, 0x21170000, 0x00010000, ATT_OWN | ATT_IRAM}, 176 { 0x21180000, 0x21180000, 0x00010000, ATT_OWN }, 177 /* DDR (Data) */ 178 { 0x0c000000, 0x80000000, 0x10000000, 0}, 179 { 0x30000000, 0x90000000, 0x10000000, 0}, 180}; 181 182/* Initialize the mailboxes between cores, if exists */ 183static int (*imx_dsp_rproc_mbox_init)(struct imx_dsp_rproc *priv); 184 185/* Reset function for DSP on i.MX8MP */ 186static int imx8mp_dsp_reset(struct imx_dsp_rproc *priv) 187{ 188 void __iomem *dap = ioremap_wc(IMX8M_DAP_DEBUG, IMX8M_DAP_DEBUG_SIZE); 189 int pwrctl; 190 191 /* Put DSP into reset and stall */ 192 pwrctl = readl(dap + IMX8M_DAP_PWRCTL); 193 pwrctl |= IMX8M_PWRCTL_CORERESET; 194 writel(pwrctl, dap + IMX8M_DAP_PWRCTL); 195 196 /* Keep reset asserted for 10 cycles */ 197 usleep_range(1, 2); 198 199 regmap_update_bits(priv->regmap, IMX8M_AudioDSP_REG2, 200 IMX8M_AudioDSP_REG2_RUNSTALL, 201 IMX8M_AudioDSP_REG2_RUNSTALL); 202 203 /* Take the DSP out of reset and keep stalled for FW loading */ 204 pwrctl = readl(dap + IMX8M_DAP_PWRCTL); 205 pwrctl &= ~IMX8M_PWRCTL_CORERESET; 206 writel(pwrctl, dap + IMX8M_DAP_PWRCTL); 207 208 iounmap(dap); 209 return 0; 210} 211 212/* Reset function for DSP on i.MX8ULP */ 213static int imx8ulp_dsp_reset(struct imx_dsp_rproc *priv) 214{ 215 struct arm_smccc_res res; 216 217 /* Put DSP into reset and stall */ 218 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 219 IMX8ULP_SYSCTRL0_DSP_RST, IMX8ULP_SYSCTRL0_DSP_RST); 220 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 221 IMX8ULP_SYSCTRL0_DSP_STALL, 222 IMX8ULP_SYSCTRL0_DSP_STALL); 223 224 /* Configure resources of DSP through TFA */ 225 arm_smccc_smc(IMX8ULP_SIP_HIFI_XRDC, 0, 0, 0, 0, 0, 0, 0, &res); 226 227 /* Take the DSP out of reset and keep stalled for FW loading */ 228 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 229 IMX8ULP_SYSCTRL0_DSP_RST, 0); 230 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 231 IMX8ULP_SYSCTRL0_DSP_DBG_RST, 0); 232 233 return 0; 234} 235 236/* Specific configuration for i.MX8MP */ 237static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8mp = { 238 .src_reg = IMX8M_AudioDSP_REG2, 239 .src_mask = IMX8M_AudioDSP_REG2_RUNSTALL, 240 .src_start = 0, 241 .src_stop = IMX8M_AudioDSP_REG2_RUNSTALL, 242 .att = imx_dsp_rproc_att_imx8mp, 243 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8mp), 244 .method = IMX_RPROC_MMIO, 245}; 246 247static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8mp = { 248 .dcfg = &dsp_rproc_cfg_imx8mp, 249 .reset = imx8mp_dsp_reset, 250}; 251 252/* Specific configuration for i.MX8ULP */ 253static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8ulp = { 254 .src_reg = IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 255 .src_mask = IMX8ULP_SYSCTRL0_DSP_STALL, 256 .src_start = 0, 257 .src_stop = IMX8ULP_SYSCTRL0_DSP_STALL, 258 .att = imx_dsp_rproc_att_imx8ulp, 259 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8ulp), 260 .method = IMX_RPROC_MMIO, 261}; 262 263static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8ulp = { 264 .dcfg = &dsp_rproc_cfg_imx8ulp, 265 .reset = imx8ulp_dsp_reset, 266}; 267 268/* Specific configuration for i.MX8QXP */ 269static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qxp = { 270 .att = imx_dsp_rproc_att_imx8qxp, 271 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qxp), 272 .method = IMX_RPROC_SCU_API, 273}; 274 275static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qxp = { 276 .dcfg = &dsp_rproc_cfg_imx8qxp, 277}; 278 279/* Specific configuration for i.MX8QM */ 280static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qm = { 281 .att = imx_dsp_rproc_att_imx8qm, 282 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qm), 283 .method = IMX_RPROC_SCU_API, 284}; 285 286static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qm = { 287 .dcfg = &dsp_rproc_cfg_imx8qm, 288}; 289 290static int imx_dsp_rproc_ready(struct rproc *rproc) 291{ 292 struct imx_dsp_rproc *priv = rproc->priv; 293 int i; 294 295 if (!priv->rxdb_ch) 296 return 0; 297 298 for (i = 0; i < REMOTE_READY_WAIT_MAX_RETRIES; i++) { 299 if (priv->flags & REMOTE_IS_READY) 300 return 0; 301 usleep_range(100, 200); 302 } 303 304 return -ETIMEDOUT; 305} 306 307/* 308 * Start function for rproc_ops 309 * 310 * There is a handshake for start procedure: when DSP starts, it 311 * will send a doorbell message to this driver, then the 312 * REMOTE_IS_READY flags is set, then driver will kick 313 * a message to DSP. 314 */ 315static int imx_dsp_rproc_start(struct rproc *rproc) 316{ 317 struct imx_dsp_rproc *priv = rproc->priv; 318 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 319 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 320 struct device *dev = rproc->dev.parent; 321 int ret; 322 323 switch (dcfg->method) { 324 case IMX_RPROC_MMIO: 325 ret = regmap_update_bits(priv->regmap, 326 dcfg->src_reg, 327 dcfg->src_mask, 328 dcfg->src_start); 329 break; 330 case IMX_RPROC_SCU_API: 331 ret = imx_sc_pm_cpu_start(priv->ipc_handle, 332 IMX_SC_R_DSP, 333 true, 334 rproc->bootaddr); 335 break; 336 default: 337 return -EOPNOTSUPP; 338 } 339 340 if (ret) 341 dev_err(dev, "Failed to enable remote core!\n"); 342 else 343 ret = imx_dsp_rproc_ready(rproc); 344 345 return ret; 346} 347 348/* 349 * Stop function for rproc_ops 350 * It clears the REMOTE_IS_READY flags 351 */ 352static int imx_dsp_rproc_stop(struct rproc *rproc) 353{ 354 struct imx_dsp_rproc *priv = rproc->priv; 355 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 356 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 357 struct device *dev = rproc->dev.parent; 358 int ret = 0; 359 360 if (rproc->state == RPROC_CRASHED) { 361 priv->flags &= ~REMOTE_IS_READY; 362 return 0; 363 } 364 365 switch (dcfg->method) { 366 case IMX_RPROC_MMIO: 367 ret = regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, 368 dcfg->src_stop); 369 break; 370 case IMX_RPROC_SCU_API: 371 ret = imx_sc_pm_cpu_start(priv->ipc_handle, 372 IMX_SC_R_DSP, 373 false, 374 rproc->bootaddr); 375 break; 376 default: 377 return -EOPNOTSUPP; 378 } 379 380 if (ret) 381 dev_err(dev, "Failed to stop remote core\n"); 382 else 383 priv->flags &= ~REMOTE_IS_READY; 384 385 return ret; 386} 387 388/** 389 * imx_dsp_rproc_sys_to_da() - internal memory translation helper 390 * @priv: private data pointer 391 * @sys: system address (DDR address) 392 * @len: length of the memory buffer 393 * @da: device address to translate 394 * 395 * Convert system address (DDR address) to device address (DSP) 396 * for there may be memory remap for device. 397 */ 398static int imx_dsp_rproc_sys_to_da(struct imx_dsp_rproc *priv, u64 sys, 399 size_t len, u64 *da) 400{ 401 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 402 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 403 int i; 404 405 /* Parse address translation table */ 406 for (i = 0; i < dcfg->att_size; i++) { 407 const struct imx_rproc_att *att = &dcfg->att[i]; 408 409 if (sys >= att->sa && sys + len <= att->sa + att->size) { 410 unsigned int offset = sys - att->sa; 411 412 *da = att->da + offset; 413 return 0; 414 } 415 } 416 417 return -ENOENT; 418} 419 420/* Main virtqueue message work function 421 * 422 * This function is executed upon scheduling of the i.MX DSP remoteproc 423 * driver's workqueue. The workqueue is scheduled by the mailbox rx 424 * handler. 425 * 426 * This work function processes both the Tx and Rx virtqueue indices on 427 * every invocation. The rproc_vq_interrupt function can detect if there 428 * are new unprocessed messages or not (returns IRQ_NONE vs IRQ_HANDLED), 429 * but there is no need to check for these return values. The index 0 430 * triggering will process all pending Rx buffers, and the index 1 triggering 431 * will process all newly available Tx buffers and will wakeup any potentially 432 * blocked senders. 433 * 434 * NOTE: 435 * The current logic is based on an inherent design assumption of supporting 436 * only 2 vrings, but this can be changed if needed. 437 */ 438static void imx_dsp_rproc_vq_work(struct work_struct *work) 439{ 440 struct imx_dsp_rproc *priv = container_of(work, struct imx_dsp_rproc, 441 rproc_work); 442 struct rproc *rproc = priv->rproc; 443 444 mutex_lock(&rproc->lock); 445 446 if (rproc->state != RPROC_RUNNING) 447 goto unlock_mutex; 448 449 rproc_vq_interrupt(priv->rproc, 0); 450 rproc_vq_interrupt(priv->rproc, 1); 451 452unlock_mutex: 453 mutex_unlock(&rproc->lock); 454} 455 456/** 457 * imx_dsp_rproc_rx_tx_callback() - inbound mailbox message handler 458 * @cl: mailbox client pointer used for requesting the mailbox channel 459 * @data: mailbox payload 460 * 461 * This handler is invoked by mailbox driver whenever a mailbox 462 * message is received. Usually, the SUSPEND and RESUME related messages 463 * are handled in this function, other messages are handled by remoteproc core 464 */ 465static void imx_dsp_rproc_rx_tx_callback(struct mbox_client *cl, void *data) 466{ 467 struct rproc *rproc = dev_get_drvdata(cl->dev); 468 struct imx_dsp_rproc *priv = rproc->priv; 469 struct device *dev = rproc->dev.parent; 470 u32 message = (u32)(*(u32 *)data); 471 472 dev_dbg(dev, "mbox msg: 0x%x\n", message); 473 474 switch (message) { 475 case RP_MBOX_SUSPEND_ACK: 476 complete(&priv->pm_comp); 477 break; 478 case RP_MBOX_RESUME_ACK: 479 complete(&priv->pm_comp); 480 break; 481 default: 482 schedule_work(&priv->rproc_work); 483 break; 484 } 485} 486 487/** 488 * imx_dsp_rproc_rxdb_callback() - inbound mailbox message handler 489 * @cl: mailbox client pointer used for requesting the mailbox channel 490 * @data: mailbox payload 491 * 492 * For doorbell, there is no message specified, just set REMOTE_IS_READY 493 * flag. 494 */ 495static void imx_dsp_rproc_rxdb_callback(struct mbox_client *cl, void *data) 496{ 497 struct rproc *rproc = dev_get_drvdata(cl->dev); 498 struct imx_dsp_rproc *priv = rproc->priv; 499 500 /* Remote is ready after firmware is loaded and running */ 501 priv->flags |= REMOTE_IS_READY; 502} 503 504/** 505 * imx_dsp_rproc_mbox_alloc() - request mailbox channels 506 * @priv: private data pointer 507 * 508 * Request three mailbox channels (tx, rx, rxdb). 509 */ 510static int imx_dsp_rproc_mbox_alloc(struct imx_dsp_rproc *priv) 511{ 512 struct device *dev = priv->rproc->dev.parent; 513 struct mbox_client *cl; 514 int ret; 515 516 if (!of_get_property(dev->of_node, "mbox-names", NULL)) 517 return 0; 518 519 cl = &priv->cl; 520 cl->dev = dev; 521 cl->tx_block = true; 522 cl->tx_tout = 100; 523 cl->knows_txdone = false; 524 cl->rx_callback = imx_dsp_rproc_rx_tx_callback; 525 526 /* Channel for sending message */ 527 priv->tx_ch = mbox_request_channel_byname(cl, "tx"); 528 if (IS_ERR(priv->tx_ch)) { 529 ret = PTR_ERR(priv->tx_ch); 530 dev_dbg(cl->dev, "failed to request tx mailbox channel: %d\n", 531 ret); 532 return ret; 533 } 534 535 /* Channel for receiving message */ 536 priv->rx_ch = mbox_request_channel_byname(cl, "rx"); 537 if (IS_ERR(priv->rx_ch)) { 538 ret = PTR_ERR(priv->rx_ch); 539 dev_dbg(cl->dev, "failed to request rx mailbox channel: %d\n", 540 ret); 541 goto free_channel_tx; 542 } 543 544 cl = &priv->cl_rxdb; 545 cl->dev = dev; 546 cl->rx_callback = imx_dsp_rproc_rxdb_callback; 547 548 /* 549 * RX door bell is used to receive the ready signal from remote 550 * after firmware loaded. 551 */ 552 priv->rxdb_ch = mbox_request_channel_byname(cl, "rxdb"); 553 if (IS_ERR(priv->rxdb_ch)) { 554 ret = PTR_ERR(priv->rxdb_ch); 555 dev_dbg(cl->dev, "failed to request mbox chan rxdb, ret %d\n", 556 ret); 557 goto free_channel_rx; 558 } 559 560 return 0; 561 562free_channel_rx: 563 mbox_free_channel(priv->rx_ch); 564free_channel_tx: 565 mbox_free_channel(priv->tx_ch); 566 return ret; 567} 568 569/* 570 * imx_dsp_rproc_mbox_no_alloc() 571 * 572 * Empty function for no mailbox between cores 573 * 574 * Always return 0 575 */ 576static int imx_dsp_rproc_mbox_no_alloc(struct imx_dsp_rproc *priv) 577{ 578 return 0; 579} 580 581static void imx_dsp_rproc_free_mbox(struct imx_dsp_rproc *priv) 582{ 583 mbox_free_channel(priv->tx_ch); 584 mbox_free_channel(priv->rx_ch); 585 mbox_free_channel(priv->rxdb_ch); 586} 587 588/** 589 * imx_dsp_rproc_add_carveout() - request mailbox channels 590 * @priv: private data pointer 591 * 592 * This function registers specified memory entry in @rproc carveouts list 593 * The carveouts can help to mapping the memory address for DSP. 594 */ 595static int imx_dsp_rproc_add_carveout(struct imx_dsp_rproc *priv) 596{ 597 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 598 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 599 struct rproc *rproc = priv->rproc; 600 struct device *dev = rproc->dev.parent; 601 struct device_node *np = dev->of_node; 602 struct of_phandle_iterator it; 603 struct rproc_mem_entry *mem; 604 struct reserved_mem *rmem; 605 void __iomem *cpu_addr; 606 int a; 607 u64 da; 608 609 /* Remap required addresses */ 610 for (a = 0; a < dcfg->att_size; a++) { 611 const struct imx_rproc_att *att = &dcfg->att[a]; 612 613 if (!(att->flags & ATT_OWN)) 614 continue; 615 616 if (imx_dsp_rproc_sys_to_da(priv, att->sa, att->size, &da)) 617 return -EINVAL; 618 619 cpu_addr = devm_ioremap_wc(dev, att->sa, att->size); 620 if (!cpu_addr) { 621 dev_err(dev, "failed to map memory %p\n", &att->sa); 622 return -ENOMEM; 623 } 624 625 /* Register memory region */ 626 mem = rproc_mem_entry_init(dev, (void __force *)cpu_addr, (dma_addr_t)att->sa, 627 att->size, da, NULL, NULL, "dsp_mem"); 628 629 if (mem) 630 rproc_coredump_add_segment(rproc, da, att->size); 631 else 632 return -ENOMEM; 633 634 rproc_add_carveout(rproc, mem); 635 } 636 637 of_phandle_iterator_init(&it, np, "memory-region", NULL, 0); 638 while (of_phandle_iterator_next(&it) == 0) { 639 /* 640 * Ignore the first memory region which will be used vdev buffer. 641 * No need to do extra handlings, rproc_add_virtio_dev will handle it. 642 */ 643 if (!strcmp(it.node->name, "vdev0buffer")) 644 continue; 645 646 rmem = of_reserved_mem_lookup(it.node); 647 if (!rmem) { 648 of_node_put(it.node); 649 dev_err(dev, "unable to acquire memory-region\n"); 650 return -EINVAL; 651 } 652 653 if (imx_dsp_rproc_sys_to_da(priv, rmem->base, rmem->size, &da)) { 654 of_node_put(it.node); 655 return -EINVAL; 656 } 657 658 cpu_addr = devm_ioremap_wc(dev, rmem->base, rmem->size); 659 if (!cpu_addr) { 660 of_node_put(it.node); 661 dev_err(dev, "failed to map memory %p\n", &rmem->base); 662 return -ENOMEM; 663 } 664 665 /* Register memory region */ 666 mem = rproc_mem_entry_init(dev, (void __force *)cpu_addr, (dma_addr_t)rmem->base, 667 rmem->size, da, NULL, NULL, it.node->name); 668 669 if (mem) { 670 rproc_coredump_add_segment(rproc, da, rmem->size); 671 } else { 672 of_node_put(it.node); 673 return -ENOMEM; 674 } 675 676 rproc_add_carveout(rproc, mem); 677 } 678 679 return 0; 680} 681 682/* Prepare function for rproc_ops */ 683static int imx_dsp_rproc_prepare(struct rproc *rproc) 684{ 685 struct imx_dsp_rproc *priv = rproc->priv; 686 struct device *dev = rproc->dev.parent; 687 struct rproc_mem_entry *carveout; 688 int ret; 689 690 ret = imx_dsp_rproc_add_carveout(priv); 691 if (ret) { 692 dev_err(dev, "failed on imx_dsp_rproc_add_carveout\n"); 693 return ret; 694 } 695 696 pm_runtime_get_sync(dev); 697 698 /* 699 * Clear buffers after pm rumtime for internal ocram is not 700 * accessible if power and clock are not enabled. 701 */ 702 list_for_each_entry(carveout, &rproc->carveouts, node) { 703 if (carveout->va) 704 memset(carveout->va, 0, carveout->len); 705 } 706 707 return 0; 708} 709 710/* Unprepare function for rproc_ops */ 711static int imx_dsp_rproc_unprepare(struct rproc *rproc) 712{ 713 pm_runtime_put_sync(rproc->dev.parent); 714 715 return 0; 716} 717 718/* Kick function for rproc_ops */ 719static void imx_dsp_rproc_kick(struct rproc *rproc, int vqid) 720{ 721 struct imx_dsp_rproc *priv = rproc->priv; 722 struct device *dev = rproc->dev.parent; 723 int err; 724 __u32 mmsg; 725 726 if (!priv->tx_ch) { 727 dev_err(dev, "No initialized mbox tx channel\n"); 728 return; 729 } 730 731 /* 732 * Send the index of the triggered virtqueue as the mu payload. 733 * Let remote processor know which virtqueue is used. 734 */ 735 mmsg = vqid; 736 737 err = mbox_send_message(priv->tx_ch, (void *)&mmsg); 738 if (err < 0) 739 dev_err(dev, "%s: failed (%d, err:%d)\n", __func__, vqid, err); 740} 741 742/* 743 * Custom memory copy implementation for i.MX DSP Cores 744 * 745 * The IRAM is part of the HiFi DSP. 746 * According to hw specs only 32-bits writes are allowed. 747 */ 748static int imx_dsp_rproc_memcpy(void *dst, const void *src, size_t size) 749{ 750 void __iomem *dest = (void __iomem *)dst; 751 const u8 *src_byte = src; 752 const u32 *source = src; 753 u32 affected_mask; 754 int i, q, r; 755 u32 tmp; 756 757 /* destination must be 32bit aligned */ 758 if (!IS_ALIGNED((uintptr_t)dest, 4)) 759 return -EINVAL; 760 761 q = size / 4; 762 r = size % 4; 763 764 /* copy data in units of 32 bits at a time */ 765 for (i = 0; i < q; i++) 766 writel(source[i], dest + i * 4); 767 768 if (r) { 769 affected_mask = GENMASK(8 * r, 0); 770 771 /* 772 * first read the 32bit data of dest, then change affected 773 * bytes, and write back to dest. 774 * For unaffected bytes, it should not be changed 775 */ 776 tmp = readl(dest + q * 4); 777 tmp &= ~affected_mask; 778 779 /* avoid reading after end of source */ 780 for (i = 0; i < r; i++) 781 tmp |= (src_byte[q * 4 + i] << (8 * i)); 782 783 writel(tmp, dest + q * 4); 784 } 785 786 return 0; 787} 788 789/* 790 * Custom memset implementation for i.MX DSP Cores 791 * 792 * The IRAM is part of the HiFi DSP. 793 * According to hw specs only 32-bits writes are allowed. 794 */ 795static int imx_dsp_rproc_memset(void *addr, u8 value, size_t size) 796{ 797 void __iomem *tmp_dst = (void __iomem *)addr; 798 u32 tmp_val = value; 799 u32 affected_mask; 800 int q, r; 801 u32 tmp; 802 803 /* destination must be 32bit aligned */ 804 if (!IS_ALIGNED((uintptr_t)addr, 4)) 805 return -EINVAL; 806 807 tmp_val |= tmp_val << 8; 808 tmp_val |= tmp_val << 16; 809 810 q = size / 4; 811 r = size % 4; 812 813 while (q--) 814 writel(tmp_val, tmp_dst++); 815 816 if (r) { 817 affected_mask = GENMASK(8 * r, 0); 818 819 /* 820 * first read the 32bit data of addr, then change affected 821 * bytes, and write back to addr. 822 * For unaffected bytes, it should not be changed 823 */ 824 tmp = readl(tmp_dst); 825 tmp &= ~affected_mask; 826 827 tmp |= (tmp_val & affected_mask); 828 writel(tmp, tmp_dst); 829 } 830 831 return 0; 832} 833 834/* 835 * imx_dsp_rproc_elf_load_segments() - load firmware segments to memory 836 * @rproc: remote processor which will be booted using these fw segments 837 * @fw: the ELF firmware image 838 * 839 * This function loads the firmware segments to memory, where the remote 840 * processor expects them. 841 * 842 * Return: 0 on success and an appropriate error code otherwise 843 */ 844static int imx_dsp_rproc_elf_load_segments(struct rproc *rproc, const struct firmware *fw) 845{ 846 struct device *dev = &rproc->dev; 847 const void *ehdr, *phdr; 848 int i, ret = 0; 849 u16 phnum; 850 const u8 *elf_data = fw->data; 851 u8 class = fw_elf_get_class(fw); 852 u32 elf_phdr_get_size = elf_size_of_phdr(class); 853 854 ehdr = elf_data; 855 phnum = elf_hdr_get_e_phnum(class, ehdr); 856 phdr = elf_data + elf_hdr_get_e_phoff(class, ehdr); 857 858 /* go through the available ELF segments */ 859 for (i = 0; i < phnum; i++, phdr += elf_phdr_get_size) { 860 u64 da = elf_phdr_get_p_paddr(class, phdr); 861 u64 memsz = elf_phdr_get_p_memsz(class, phdr); 862 u64 filesz = elf_phdr_get_p_filesz(class, phdr); 863 u64 offset = elf_phdr_get_p_offset(class, phdr); 864 u32 type = elf_phdr_get_p_type(class, phdr); 865 void *ptr; 866 867 if (type != PT_LOAD || !memsz) 868 continue; 869 870 dev_dbg(dev, "phdr: type %d da 0x%llx memsz 0x%llx filesz 0x%llx\n", 871 type, da, memsz, filesz); 872 873 if (filesz > memsz) { 874 dev_err(dev, "bad phdr filesz 0x%llx memsz 0x%llx\n", 875 filesz, memsz); 876 ret = -EINVAL; 877 break; 878 } 879 880 if (offset + filesz > fw->size) { 881 dev_err(dev, "truncated fw: need 0x%llx avail 0x%zx\n", 882 offset + filesz, fw->size); 883 ret = -EINVAL; 884 break; 885 } 886 887 if (!rproc_u64_fit_in_size_t(memsz)) { 888 dev_err(dev, "size (%llx) does not fit in size_t type\n", 889 memsz); 890 ret = -EOVERFLOW; 891 break; 892 } 893 894 /* grab the kernel address for this device address */ 895 ptr = rproc_da_to_va(rproc, da, memsz, NULL); 896 if (!ptr) { 897 dev_err(dev, "bad phdr da 0x%llx mem 0x%llx\n", da, 898 memsz); 899 ret = -EINVAL; 900 break; 901 } 902 903 /* put the segment where the remote processor expects it */ 904 if (filesz) { 905 ret = imx_dsp_rproc_memcpy(ptr, elf_data + offset, filesz); 906 if (ret) { 907 dev_err(dev, "memory copy failed for da 0x%llx memsz 0x%llx\n", 908 da, memsz); 909 break; 910 } 911 } 912 913 /* zero out remaining memory for this segment */ 914 if (memsz > filesz) { 915 ret = imx_dsp_rproc_memset(ptr + filesz, 0, memsz - filesz); 916 if (ret) { 917 dev_err(dev, "memset failed for da 0x%llx memsz 0x%llx\n", 918 da, memsz); 919 break; 920 } 921 } 922 } 923 924 return ret; 925} 926 927static int imx_dsp_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) 928{ 929 if (rproc_elf_load_rsc_table(rproc, fw)) 930 dev_warn(&rproc->dev, "no resource table found for this firmware\n"); 931 932 return 0; 933} 934 935static const struct rproc_ops imx_dsp_rproc_ops = { 936 .prepare = imx_dsp_rproc_prepare, 937 .unprepare = imx_dsp_rproc_unprepare, 938 .start = imx_dsp_rproc_start, 939 .stop = imx_dsp_rproc_stop, 940 .kick = imx_dsp_rproc_kick, 941 .load = imx_dsp_rproc_elf_load_segments, 942 .parse_fw = imx_dsp_rproc_parse_fw, 943 .sanity_check = rproc_elf_sanity_check, 944 .get_boot_addr = rproc_elf_get_boot_addr, 945}; 946 947/** 948 * imx_dsp_attach_pm_domains() - attach the power domains 949 * @priv: private data pointer 950 * 951 * On i.MX8QM and i.MX8QXP there is multiple power domains 952 * required, so need to link them. 953 */ 954static int imx_dsp_attach_pm_domains(struct imx_dsp_rproc *priv) 955{ 956 struct device *dev = priv->rproc->dev.parent; 957 int ret, i; 958 959 priv->num_domains = of_count_phandle_with_args(dev->of_node, 960 "power-domains", 961 "#power-domain-cells"); 962 963 /* If only one domain, then no need to link the device */ 964 if (priv->num_domains <= 1) 965 return 0; 966 967 priv->pd_dev = devm_kmalloc_array(dev, priv->num_domains, 968 sizeof(*priv->pd_dev), 969 GFP_KERNEL); 970 if (!priv->pd_dev) 971 return -ENOMEM; 972 973 priv->pd_dev_link = devm_kmalloc_array(dev, priv->num_domains, 974 sizeof(*priv->pd_dev_link), 975 GFP_KERNEL); 976 if (!priv->pd_dev_link) 977 return -ENOMEM; 978 979 for (i = 0; i < priv->num_domains; i++) { 980 priv->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i); 981 if (IS_ERR(priv->pd_dev[i])) { 982 ret = PTR_ERR(priv->pd_dev[i]); 983 goto detach_pm; 984 } 985 986 /* 987 * device_link_add will check priv->pd_dev[i], if it is 988 * NULL, then will break. 989 */ 990 priv->pd_dev_link[i] = device_link_add(dev, 991 priv->pd_dev[i], 992 DL_FLAG_STATELESS | 993 DL_FLAG_PM_RUNTIME); 994 if (!priv->pd_dev_link[i]) { 995 dev_pm_domain_detach(priv->pd_dev[i], false); 996 ret = -EINVAL; 997 goto detach_pm; 998 } 999 } 1000 1001 return 0; 1002 1003detach_pm: 1004 while (--i >= 0) { 1005 device_link_del(priv->pd_dev_link[i]); 1006 dev_pm_domain_detach(priv->pd_dev[i], false); 1007 } 1008 1009 return ret; 1010} 1011 1012static int imx_dsp_detach_pm_domains(struct imx_dsp_rproc *priv) 1013{ 1014 int i; 1015 1016 if (priv->num_domains <= 1) 1017 return 0; 1018 1019 for (i = 0; i < priv->num_domains; i++) { 1020 device_link_del(priv->pd_dev_link[i]); 1021 dev_pm_domain_detach(priv->pd_dev[i], false); 1022 } 1023 1024 return 0; 1025} 1026 1027/** 1028 * imx_dsp_rproc_detect_mode() - detect DSP control mode 1029 * @priv: private data pointer 1030 * 1031 * Different platform has different control method for DSP, which depends 1032 * on how the DSP is integrated in platform. 1033 * 1034 * For i.MX8QXP and i.MX8QM, DSP should be started and stopped by System 1035 * Control Unit. 1036 * For i.MX8MP and i.MX8ULP, DSP should be started and stopped by system 1037 * integration module. 1038 */ 1039static int imx_dsp_rproc_detect_mode(struct imx_dsp_rproc *priv) 1040{ 1041 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 1042 struct device *dev = priv->rproc->dev.parent; 1043 struct regmap *regmap; 1044 int ret = 0; 1045 1046 switch (dsp_dcfg->dcfg->method) { 1047 case IMX_RPROC_SCU_API: 1048 ret = imx_scu_get_handle(&priv->ipc_handle); 1049 if (ret) 1050 return ret; 1051 break; 1052 case IMX_RPROC_MMIO: 1053 regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,dsp-ctrl"); 1054 if (IS_ERR(regmap)) { 1055 dev_err(dev, "failed to find syscon\n"); 1056 return PTR_ERR(regmap); 1057 } 1058 1059 priv->regmap = regmap; 1060 break; 1061 default: 1062 ret = -EOPNOTSUPP; 1063 break; 1064 } 1065 1066 return ret; 1067} 1068 1069static const char *imx_dsp_clks_names[DSP_RPROC_CLK_MAX] = { 1070 /* DSP clocks */ 1071 "core", "ocram", "debug", "ipg", "mu", 1072}; 1073 1074static int imx_dsp_rproc_clk_get(struct imx_dsp_rproc *priv) 1075{ 1076 struct device *dev = priv->rproc->dev.parent; 1077 struct clk_bulk_data *clks = priv->clks; 1078 int i; 1079 1080 for (i = 0; i < DSP_RPROC_CLK_MAX; i++) 1081 clks[i].id = imx_dsp_clks_names[i]; 1082 1083 return devm_clk_bulk_get_optional(dev, DSP_RPROC_CLK_MAX, clks); 1084} 1085 1086static int imx_dsp_rproc_probe(struct platform_device *pdev) 1087{ 1088 const struct imx_dsp_rproc_dcfg *dsp_dcfg; 1089 struct device *dev = &pdev->dev; 1090 struct imx_dsp_rproc *priv; 1091 struct rproc *rproc; 1092 const char *fw_name; 1093 int ret; 1094 1095 dsp_dcfg = of_device_get_match_data(dev); 1096 if (!dsp_dcfg) 1097 return -ENODEV; 1098 1099 ret = rproc_of_parse_firmware(dev, 0, &fw_name); 1100 if (ret) { 1101 dev_err(dev, "failed to parse firmware-name property, ret = %d\n", 1102 ret); 1103 return ret; 1104 } 1105 1106 rproc = rproc_alloc(dev, "imx-dsp-rproc", &imx_dsp_rproc_ops, fw_name, 1107 sizeof(*priv)); 1108 if (!rproc) 1109 return -ENOMEM; 1110 1111 priv = rproc->priv; 1112 priv->rproc = rproc; 1113 priv->dsp_dcfg = dsp_dcfg; 1114 1115 if (no_mailboxes) 1116 imx_dsp_rproc_mbox_init = imx_dsp_rproc_mbox_no_alloc; 1117 else 1118 imx_dsp_rproc_mbox_init = imx_dsp_rproc_mbox_alloc; 1119 1120 dev_set_drvdata(dev, rproc); 1121 1122 INIT_WORK(&priv->rproc_work, imx_dsp_rproc_vq_work); 1123 1124 ret = imx_dsp_rproc_detect_mode(priv); 1125 if (ret) { 1126 dev_err(dev, "failed on imx_dsp_rproc_detect_mode\n"); 1127 goto err_put_rproc; 1128 } 1129 1130 /* There are multiple power domains required by DSP on some platform */ 1131 ret = imx_dsp_attach_pm_domains(priv); 1132 if (ret) { 1133 dev_err(dev, "failed on imx_dsp_attach_pm_domains\n"); 1134 goto err_put_rproc; 1135 } 1136 /* Get clocks */ 1137 ret = imx_dsp_rproc_clk_get(priv); 1138 if (ret) { 1139 dev_err(dev, "failed on imx_dsp_rproc_clk_get\n"); 1140 goto err_detach_domains; 1141 } 1142 1143 init_completion(&priv->pm_comp); 1144 rproc->auto_boot = false; 1145 ret = rproc_add(rproc); 1146 if (ret) { 1147 dev_err(dev, "rproc_add failed\n"); 1148 goto err_detach_domains; 1149 } 1150 1151 pm_runtime_enable(dev); 1152 1153 return 0; 1154 1155err_detach_domains: 1156 imx_dsp_detach_pm_domains(priv); 1157err_put_rproc: 1158 rproc_free(rproc); 1159 1160 return ret; 1161} 1162 1163static void imx_dsp_rproc_remove(struct platform_device *pdev) 1164{ 1165 struct rproc *rproc = platform_get_drvdata(pdev); 1166 struct imx_dsp_rproc *priv = rproc->priv; 1167 1168 pm_runtime_disable(&pdev->dev); 1169 rproc_del(rproc); 1170 imx_dsp_detach_pm_domains(priv); 1171 rproc_free(rproc); 1172} 1173 1174/* pm runtime functions */ 1175static int imx_dsp_runtime_resume(struct device *dev) 1176{ 1177 struct rproc *rproc = dev_get_drvdata(dev); 1178 struct imx_dsp_rproc *priv = rproc->priv; 1179 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 1180 int ret; 1181 1182 /* 1183 * There is power domain attached with mailbox, if setup mailbox 1184 * in probe(), then the power of mailbox is always enabled, 1185 * the power can't be saved. 1186 * So move setup of mailbox to runtime resume. 1187 */ 1188 ret = imx_dsp_rproc_mbox_init(priv); 1189 if (ret) { 1190 dev_err(dev, "failed on imx_dsp_rproc_mbox_init\n"); 1191 return ret; 1192 } 1193 1194 ret = clk_bulk_prepare_enable(DSP_RPROC_CLK_MAX, priv->clks); 1195 if (ret) { 1196 dev_err(dev, "failed on clk_bulk_prepare_enable\n"); 1197 return ret; 1198 } 1199 1200 /* Reset DSP if needed */ 1201 if (dsp_dcfg->reset) 1202 dsp_dcfg->reset(priv); 1203 1204 return 0; 1205} 1206 1207static int imx_dsp_runtime_suspend(struct device *dev) 1208{ 1209 struct rproc *rproc = dev_get_drvdata(dev); 1210 struct imx_dsp_rproc *priv = rproc->priv; 1211 1212 clk_bulk_disable_unprepare(DSP_RPROC_CLK_MAX, priv->clks); 1213 1214 imx_dsp_rproc_free_mbox(priv); 1215 1216 return 0; 1217} 1218 1219static void imx_dsp_load_firmware(const struct firmware *fw, void *context) 1220{ 1221 struct rproc *rproc = context; 1222 int ret; 1223 1224 /* 1225 * Same flow as start procedure. 1226 * Load the ELF segments to memory firstly. 1227 */ 1228 ret = rproc_load_segments(rproc, fw); 1229 if (ret) 1230 goto out; 1231 1232 /* Start the remote processor */ 1233 ret = rproc->ops->start(rproc); 1234 if (ret) 1235 goto out; 1236 1237 rproc->ops->kick(rproc, 0); 1238 1239out: 1240 release_firmware(fw); 1241} 1242 1243static int imx_dsp_suspend(struct device *dev) 1244{ 1245 struct rproc *rproc = dev_get_drvdata(dev); 1246 struct imx_dsp_rproc *priv = rproc->priv; 1247 __u32 mmsg = RP_MBOX_SUSPEND_SYSTEM; 1248 int ret; 1249 1250 if (rproc->state != RPROC_RUNNING) 1251 goto out; 1252 1253 reinit_completion(&priv->pm_comp); 1254 1255 /* Tell DSP that suspend is happening */ 1256 ret = mbox_send_message(priv->tx_ch, (void *)&mmsg); 1257 if (ret < 0) { 1258 dev_err(dev, "PM mbox_send_message failed: %d\n", ret); 1259 return ret; 1260 } 1261 1262 /* 1263 * DSP need to save the context at suspend. 1264 * Here waiting the response for DSP, then power can be disabled. 1265 */ 1266 if (!wait_for_completion_timeout(&priv->pm_comp, msecs_to_jiffies(100))) 1267 return -EBUSY; 1268 1269out: 1270 /* 1271 * The power of DSP is disabled in suspend, so force pm runtime 1272 * to be suspend, then we can reenable the power and clocks at 1273 * resume stage. 1274 */ 1275 return pm_runtime_force_suspend(dev); 1276} 1277 1278static int imx_dsp_resume(struct device *dev) 1279{ 1280 struct rproc *rproc = dev_get_drvdata(dev); 1281 int ret = 0; 1282 1283 ret = pm_runtime_force_resume(dev); 1284 if (ret) 1285 return ret; 1286 1287 if (rproc->state != RPROC_RUNNING) 1288 return 0; 1289 1290 /* 1291 * The power of DSP is disabled at suspend, the memory of dsp 1292 * is reset, the image segments are lost. So need to reload 1293 * firmware and restart the DSP if it is in running state. 1294 */ 1295 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT, 1296 rproc->firmware, dev, GFP_KERNEL, 1297 rproc, imx_dsp_load_firmware); 1298 if (ret < 0) { 1299 dev_err(dev, "load firmware failed: %d\n", ret); 1300 goto err; 1301 } 1302 1303 return 0; 1304 1305err: 1306 pm_runtime_force_suspend(dev); 1307 1308 return ret; 1309} 1310 1311static const struct dev_pm_ops imx_dsp_rproc_pm_ops = { 1312 SYSTEM_SLEEP_PM_OPS(imx_dsp_suspend, imx_dsp_resume) 1313 RUNTIME_PM_OPS(imx_dsp_runtime_suspend, imx_dsp_runtime_resume, NULL) 1314}; 1315 1316static const struct of_device_id imx_dsp_rproc_of_match[] = { 1317 { .compatible = "fsl,imx8qxp-hifi4", .data = &imx_dsp_rproc_cfg_imx8qxp }, 1318 { .compatible = "fsl,imx8qm-hifi4", .data = &imx_dsp_rproc_cfg_imx8qm }, 1319 { .compatible = "fsl,imx8mp-hifi4", .data = &imx_dsp_rproc_cfg_imx8mp }, 1320 { .compatible = "fsl,imx8ulp-hifi4", .data = &imx_dsp_rproc_cfg_imx8ulp }, 1321 {}, 1322}; 1323MODULE_DEVICE_TABLE(of, imx_dsp_rproc_of_match); 1324 1325static struct platform_driver imx_dsp_rproc_driver = { 1326 .probe = imx_dsp_rproc_probe, 1327 .remove_new = imx_dsp_rproc_remove, 1328 .driver = { 1329 .name = "imx-dsp-rproc", 1330 .of_match_table = imx_dsp_rproc_of_match, 1331 .pm = pm_ptr(&imx_dsp_rproc_pm_ops), 1332 }, 1333}; 1334module_platform_driver(imx_dsp_rproc_driver); 1335 1336MODULE_LICENSE("GPL v2"); 1337MODULE_DESCRIPTION("i.MX HiFi Core Remote Processor Control Driver"); 1338MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>"); 1339