1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * MediaTek display pulse-width-modulation controller driver.
4 * Copyright (c) 2015 MediaTek Inc.
5 * Author: YH Huang <yh.huang@mediatek.com>
6 */
7
8#include <linux/bitfield.h>
9#include <linux/clk.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/pwm.h>
16#include <linux/slab.h>
17
18#define DISP_PWM_EN		0x00
19
20#define PWM_CLKDIV_SHIFT	16
21#define PWM_CLKDIV_MAX		0x3ff
22#define PWM_CLKDIV_MASK		(PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
23
24#define PWM_PERIOD_BIT_WIDTH	12
25#define PWM_PERIOD_MASK		((1 << PWM_PERIOD_BIT_WIDTH) - 1)
26
27#define PWM_HIGH_WIDTH_SHIFT	16
28#define PWM_HIGH_WIDTH_MASK	(0x1fff << PWM_HIGH_WIDTH_SHIFT)
29
30struct mtk_pwm_data {
31	u32 enable_mask;
32	unsigned int con0;
33	u32 con0_sel;
34	unsigned int con1;
35
36	bool has_commit;
37	unsigned int commit;
38	unsigned int commit_mask;
39
40	unsigned int bls_debug;
41	u32 bls_debug_mask;
42};
43
44struct mtk_disp_pwm {
45	struct pwm_chip chip;
46	const struct mtk_pwm_data *data;
47	struct clk *clk_main;
48	struct clk *clk_mm;
49	void __iomem *base;
50	bool enabled;
51};
52
53static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
54{
55	return container_of(chip, struct mtk_disp_pwm, chip);
56}
57
58static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
59				     u32 mask, u32 data)
60{
61	void __iomem *address = mdp->base + offset;
62	u32 value;
63
64	value = readl(address);
65	value &= ~mask;
66	value |= data;
67	writel(value, address);
68}
69
70static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
71			      const struct pwm_state *state)
72{
73	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
74	u32 clk_div, period, high_width, value;
75	u64 div, rate;
76	int err;
77
78	if (state->polarity != PWM_POLARITY_NORMAL)
79		return -EINVAL;
80
81	if (!state->enabled && mdp->enabled) {
82		mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN,
83					 mdp->data->enable_mask, 0x0);
84		clk_disable_unprepare(mdp->clk_mm);
85		clk_disable_unprepare(mdp->clk_main);
86
87		mdp->enabled = false;
88		return 0;
89	}
90
91	if (!mdp->enabled) {
92		err = clk_prepare_enable(mdp->clk_main);
93		if (err < 0) {
94			dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n",
95				ERR_PTR(err));
96			return err;
97		}
98
99		err = clk_prepare_enable(mdp->clk_mm);
100		if (err < 0) {
101			dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n",
102				ERR_PTR(err));
103			clk_disable_unprepare(mdp->clk_main);
104			return err;
105		}
106	}
107
108	/*
109	 * Find period, high_width and clk_div to suit duty_ns and period_ns.
110	 * Calculate proper div value to keep period value in the bound.
111	 *
112	 * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
113	 * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
114	 *
115	 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
116	 * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
117	 */
118	rate = clk_get_rate(mdp->clk_main);
119	clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >>
120			  PWM_PERIOD_BIT_WIDTH;
121	if (clk_div > PWM_CLKDIV_MAX) {
122		if (!mdp->enabled) {
123			clk_disable_unprepare(mdp->clk_mm);
124			clk_disable_unprepare(mdp->clk_main);
125		}
126		return -EINVAL;
127	}
128
129	div = NSEC_PER_SEC * (clk_div + 1);
130	period = mul_u64_u64_div_u64(state->period, rate, div);
131	if (period > 0)
132		period--;
133
134	high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div);
135	value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
136
137	if (mdp->data->bls_debug && !mdp->data->has_commit) {
138		/*
139		 * For MT2701, disable double buffer before writing register
140		 * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
141		 */
142		mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
143					 mdp->data->bls_debug_mask,
144					 mdp->data->bls_debug_mask);
145		mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
146					 mdp->data->con0_sel,
147					 mdp->data->con0_sel);
148	}
149
150	mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
151				 PWM_CLKDIV_MASK,
152				 clk_div << PWM_CLKDIV_SHIFT);
153	mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
154				 PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
155				 value);
156
157	if (mdp->data->has_commit) {
158		mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
159					 mdp->data->commit_mask,
160					 mdp->data->commit_mask);
161		mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
162					 mdp->data->commit_mask,
163					 0x0);
164	}
165
166	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
167				 mdp->data->enable_mask);
168	mdp->enabled = true;
169
170	return 0;
171}
172
173static int mtk_disp_pwm_get_state(struct pwm_chip *chip,
174				  struct pwm_device *pwm,
175				  struct pwm_state *state)
176{
177	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
178	u64 rate, period, high_width;
179	u32 clk_div, pwm_en, con0, con1;
180	int err;
181
182	err = clk_prepare_enable(mdp->clk_main);
183	if (err < 0) {
184		dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
185		return err;
186	}
187
188	err = clk_prepare_enable(mdp->clk_mm);
189	if (err < 0) {
190		dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
191		clk_disable_unprepare(mdp->clk_main);
192		return err;
193	}
194
195	/*
196	 * Apply DISP_PWM_DEBUG settings to choose whether to enable or disable
197	 * registers double buffer and manual commit to working register before
198	 * performing any read/write operation
199	 */
200	if (mdp->data->bls_debug)
201		mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
202					 mdp->data->bls_debug_mask,
203					 mdp->data->bls_debug_mask);
204
205	rate = clk_get_rate(mdp->clk_main);
206	con0 = readl(mdp->base + mdp->data->con0);
207	con1 = readl(mdp->base + mdp->data->con1);
208	pwm_en = readl(mdp->base + DISP_PWM_EN);
209	state->enabled = !!(pwm_en & mdp->data->enable_mask);
210	clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0);
211	period = FIELD_GET(PWM_PERIOD_MASK, con1);
212	/*
213	 * period has 12 bits, clk_div 11 and NSEC_PER_SEC has 30,
214	 * so period * (clk_div + 1) * NSEC_PER_SEC doesn't overflow.
215	 */
216	state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate);
217	high_width = FIELD_GET(PWM_HIGH_WIDTH_MASK, con1);
218	state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC,
219					       rate);
220	state->polarity = PWM_POLARITY_NORMAL;
221	clk_disable_unprepare(mdp->clk_mm);
222	clk_disable_unprepare(mdp->clk_main);
223
224	return 0;
225}
226
227static const struct pwm_ops mtk_disp_pwm_ops = {
228	.apply = mtk_disp_pwm_apply,
229	.get_state = mtk_disp_pwm_get_state,
230	.owner = THIS_MODULE,
231};
232
233static int mtk_disp_pwm_probe(struct platform_device *pdev)
234{
235	struct mtk_disp_pwm *mdp;
236	int ret;
237
238	mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
239	if (!mdp)
240		return -ENOMEM;
241
242	mdp->data = of_device_get_match_data(&pdev->dev);
243
244	mdp->base = devm_platform_ioremap_resource(pdev, 0);
245	if (IS_ERR(mdp->base))
246		return PTR_ERR(mdp->base);
247
248	mdp->clk_main = devm_clk_get(&pdev->dev, "main");
249	if (IS_ERR(mdp->clk_main))
250		return PTR_ERR(mdp->clk_main);
251
252	mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
253	if (IS_ERR(mdp->clk_mm))
254		return PTR_ERR(mdp->clk_mm);
255
256	mdp->chip.dev = &pdev->dev;
257	mdp->chip.ops = &mtk_disp_pwm_ops;
258	mdp->chip.npwm = 1;
259
260	ret = pwmchip_add(&mdp->chip);
261	if (ret < 0) {
262		dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret));
263		return ret;
264	}
265
266	platform_set_drvdata(pdev, mdp);
267
268	return 0;
269}
270
271static void mtk_disp_pwm_remove(struct platform_device *pdev)
272{
273	struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
274
275	pwmchip_remove(&mdp->chip);
276}
277
278static const struct mtk_pwm_data mt2701_pwm_data = {
279	.enable_mask = BIT(16),
280	.con0 = 0xa8,
281	.con0_sel = 0x2,
282	.con1 = 0xac,
283	.has_commit = false,
284	.bls_debug = 0xb0,
285	.bls_debug_mask = 0x3,
286};
287
288static const struct mtk_pwm_data mt8173_pwm_data = {
289	.enable_mask = BIT(0),
290	.con0 = 0x10,
291	.con0_sel = 0x0,
292	.con1 = 0x14,
293	.has_commit = true,
294	.commit = 0x8,
295	.commit_mask = 0x1,
296};
297
298static const struct mtk_pwm_data mt8183_pwm_data = {
299	.enable_mask = BIT(0),
300	.con0 = 0x18,
301	.con0_sel = 0x0,
302	.con1 = 0x1c,
303	.has_commit = false,
304	.bls_debug = 0x80,
305	.bls_debug_mask = 0x3,
306};
307
308static const struct of_device_id mtk_disp_pwm_of_match[] = {
309	{ .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
310	{ .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
311	{ .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
312	{ .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
313	{ }
314};
315MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
316
317static struct platform_driver mtk_disp_pwm_driver = {
318	.driver = {
319		.name = "mediatek-disp-pwm",
320		.of_match_table = mtk_disp_pwm_of_match,
321	},
322	.probe = mtk_disp_pwm_probe,
323	.remove_new = mtk_disp_pwm_remove,
324};
325module_platform_driver(mtk_disp_pwm_driver);
326
327MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
328MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
329MODULE_LICENSE("GPL v2");
330