162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 OR MIT
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Driver for the Apple SoC PWM controller
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright The Asahi Linux Contributors
662306a36Sopenharmony_ci *
762306a36Sopenharmony_ci * Limitations:
862306a36Sopenharmony_ci * - The writes to cycle registers are shadowed until a write to
962306a36Sopenharmony_ci *   the control register.
1062306a36Sopenharmony_ci * - If both OFF_CYCLES and ON_CYCLES are set to 0, the output
1162306a36Sopenharmony_ci *   is a constant off signal.
1262306a36Sopenharmony_ci * - When APPLE_PWM_CTRL is set to 0, the output is constant low
1362306a36Sopenharmony_ci */
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_ci#include <linux/mod_devicetable.h>
1662306a36Sopenharmony_ci#include <linux/module.h>
1762306a36Sopenharmony_ci#include <linux/platform_device.h>
1862306a36Sopenharmony_ci#include <linux/pwm.h>
1962306a36Sopenharmony_ci#include <linux/io.h>
2062306a36Sopenharmony_ci#include <linux/clk.h>
2162306a36Sopenharmony_ci#include <linux/math64.h>
2262306a36Sopenharmony_ci
2362306a36Sopenharmony_ci#define APPLE_PWM_CTRL        0x00
2462306a36Sopenharmony_ci#define APPLE_PWM_ON_CYCLES   0x1c
2562306a36Sopenharmony_ci#define APPLE_PWM_OFF_CYCLES  0x18
2662306a36Sopenharmony_ci
2762306a36Sopenharmony_ci#define APPLE_PWM_CTRL_ENABLE        BIT(0)
2862306a36Sopenharmony_ci#define APPLE_PWM_CTRL_MODE          BIT(2)
2962306a36Sopenharmony_ci#define APPLE_PWM_CTRL_UPDATE        BIT(5)
3062306a36Sopenharmony_ci#define APPLE_PWM_CTRL_TRIGGER       BIT(9)
3162306a36Sopenharmony_ci#define APPLE_PWM_CTRL_INVERT        BIT(10)
3262306a36Sopenharmony_ci#define APPLE_PWM_CTRL_OUTPUT_ENABLE BIT(14)
3362306a36Sopenharmony_ci
3462306a36Sopenharmony_cistruct apple_pwm {
3562306a36Sopenharmony_ci	struct pwm_chip chip;
3662306a36Sopenharmony_ci	void __iomem *base;
3762306a36Sopenharmony_ci	u64 clkrate;
3862306a36Sopenharmony_ci};
3962306a36Sopenharmony_ci
4062306a36Sopenharmony_cistatic inline struct apple_pwm *to_apple_pwm(struct pwm_chip *chip)
4162306a36Sopenharmony_ci{
4262306a36Sopenharmony_ci	return container_of(chip, struct apple_pwm, chip);
4362306a36Sopenharmony_ci}
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_cistatic int apple_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
4662306a36Sopenharmony_ci			   const struct pwm_state *state)
4762306a36Sopenharmony_ci{
4862306a36Sopenharmony_ci	struct apple_pwm *fpwm;
4962306a36Sopenharmony_ci
5062306a36Sopenharmony_ci	if (state->polarity == PWM_POLARITY_INVERSED)
5162306a36Sopenharmony_ci		return -EINVAL;
5262306a36Sopenharmony_ci
5362306a36Sopenharmony_ci	fpwm = to_apple_pwm(chip);
5462306a36Sopenharmony_ci	if (state->enabled) {
5562306a36Sopenharmony_ci		u64 on_cycles, off_cycles;
5662306a36Sopenharmony_ci
5762306a36Sopenharmony_ci		on_cycles = mul_u64_u64_div_u64(fpwm->clkrate,
5862306a36Sopenharmony_ci						state->duty_cycle, NSEC_PER_SEC);
5962306a36Sopenharmony_ci		if (on_cycles > 0xFFFFFFFF)
6062306a36Sopenharmony_ci			on_cycles = 0xFFFFFFFF;
6162306a36Sopenharmony_ci
6262306a36Sopenharmony_ci		off_cycles = mul_u64_u64_div_u64(fpwm->clkrate,
6362306a36Sopenharmony_ci						 state->period, NSEC_PER_SEC) - on_cycles;
6462306a36Sopenharmony_ci		if (off_cycles > 0xFFFFFFFF)
6562306a36Sopenharmony_ci			off_cycles = 0xFFFFFFFF;
6662306a36Sopenharmony_ci
6762306a36Sopenharmony_ci		writel(on_cycles, fpwm->base + APPLE_PWM_ON_CYCLES);
6862306a36Sopenharmony_ci		writel(off_cycles, fpwm->base + APPLE_PWM_OFF_CYCLES);
6962306a36Sopenharmony_ci		writel(APPLE_PWM_CTRL_ENABLE | APPLE_PWM_CTRL_OUTPUT_ENABLE | APPLE_PWM_CTRL_UPDATE,
7062306a36Sopenharmony_ci		       fpwm->base + APPLE_PWM_CTRL);
7162306a36Sopenharmony_ci	} else {
7262306a36Sopenharmony_ci		writel(0, fpwm->base + APPLE_PWM_CTRL);
7362306a36Sopenharmony_ci	}
7462306a36Sopenharmony_ci	return 0;
7562306a36Sopenharmony_ci}
7662306a36Sopenharmony_ci
7762306a36Sopenharmony_cistatic int apple_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
7862306a36Sopenharmony_ci			   struct pwm_state *state)
7962306a36Sopenharmony_ci{
8062306a36Sopenharmony_ci	struct apple_pwm *fpwm;
8162306a36Sopenharmony_ci	u32 on_cycles, off_cycles, ctrl;
8262306a36Sopenharmony_ci
8362306a36Sopenharmony_ci	fpwm = to_apple_pwm(chip);
8462306a36Sopenharmony_ci
8562306a36Sopenharmony_ci	ctrl = readl(fpwm->base + APPLE_PWM_CTRL);
8662306a36Sopenharmony_ci	on_cycles = readl(fpwm->base + APPLE_PWM_ON_CYCLES);
8762306a36Sopenharmony_ci	off_cycles = readl(fpwm->base + APPLE_PWM_OFF_CYCLES);
8862306a36Sopenharmony_ci
8962306a36Sopenharmony_ci	state->enabled = (ctrl & APPLE_PWM_CTRL_ENABLE) && (ctrl & APPLE_PWM_CTRL_OUTPUT_ENABLE);
9062306a36Sopenharmony_ci	state->polarity = PWM_POLARITY_NORMAL;
9162306a36Sopenharmony_ci	// on_cycles + off_cycles is 33 bits, NSEC_PER_SEC is 30, there is no overflow
9262306a36Sopenharmony_ci	state->duty_cycle = DIV64_U64_ROUND_UP((u64)on_cycles * NSEC_PER_SEC, fpwm->clkrate);
9362306a36Sopenharmony_ci	state->period = DIV64_U64_ROUND_UP(((u64)off_cycles + (u64)on_cycles) *
9462306a36Sopenharmony_ci					    NSEC_PER_SEC, fpwm->clkrate);
9562306a36Sopenharmony_ci
9662306a36Sopenharmony_ci	return 0;
9762306a36Sopenharmony_ci}
9862306a36Sopenharmony_ci
9962306a36Sopenharmony_cistatic const struct pwm_ops apple_pwm_ops = {
10062306a36Sopenharmony_ci	.apply = apple_pwm_apply,
10162306a36Sopenharmony_ci	.get_state = apple_pwm_get_state,
10262306a36Sopenharmony_ci	.owner = THIS_MODULE,
10362306a36Sopenharmony_ci};
10462306a36Sopenharmony_ci
10562306a36Sopenharmony_cistatic int apple_pwm_probe(struct platform_device *pdev)
10662306a36Sopenharmony_ci{
10762306a36Sopenharmony_ci	struct apple_pwm *fpwm;
10862306a36Sopenharmony_ci	struct clk *clk;
10962306a36Sopenharmony_ci	int ret;
11062306a36Sopenharmony_ci
11162306a36Sopenharmony_ci	fpwm = devm_kzalloc(&pdev->dev, sizeof(*fpwm), GFP_KERNEL);
11262306a36Sopenharmony_ci	if (!fpwm)
11362306a36Sopenharmony_ci		return -ENOMEM;
11462306a36Sopenharmony_ci
11562306a36Sopenharmony_ci	fpwm->base = devm_platform_ioremap_resource(pdev, 0);
11662306a36Sopenharmony_ci	if (IS_ERR(fpwm->base))
11762306a36Sopenharmony_ci		return PTR_ERR(fpwm->base);
11862306a36Sopenharmony_ci
11962306a36Sopenharmony_ci	clk = devm_clk_get_enabled(&pdev->dev, NULL);
12062306a36Sopenharmony_ci	if (IS_ERR(clk))
12162306a36Sopenharmony_ci		return dev_err_probe(&pdev->dev, PTR_ERR(clk), "unable to get the clock");
12262306a36Sopenharmony_ci
12362306a36Sopenharmony_ci	/*
12462306a36Sopenharmony_ci	 * Uses the 24MHz system clock on all existing devices, can only
12562306a36Sopenharmony_ci	 * happen if the device tree is broken
12662306a36Sopenharmony_ci	 *
12762306a36Sopenharmony_ci	 * This check is done to prevent an overflow in .apply
12862306a36Sopenharmony_ci	 */
12962306a36Sopenharmony_ci	fpwm->clkrate = clk_get_rate(clk);
13062306a36Sopenharmony_ci	if (fpwm->clkrate > NSEC_PER_SEC)
13162306a36Sopenharmony_ci		return dev_err_probe(&pdev->dev, -EINVAL, "pwm clock out of range");
13262306a36Sopenharmony_ci
13362306a36Sopenharmony_ci	fpwm->chip.dev = &pdev->dev;
13462306a36Sopenharmony_ci	fpwm->chip.npwm = 1;
13562306a36Sopenharmony_ci	fpwm->chip.ops = &apple_pwm_ops;
13662306a36Sopenharmony_ci
13762306a36Sopenharmony_ci	ret = devm_pwmchip_add(&pdev->dev, &fpwm->chip);
13862306a36Sopenharmony_ci	if (ret < 0)
13962306a36Sopenharmony_ci		return dev_err_probe(&pdev->dev, ret, "unable to add pwm chip");
14062306a36Sopenharmony_ci
14162306a36Sopenharmony_ci	return 0;
14262306a36Sopenharmony_ci}
14362306a36Sopenharmony_ci
14462306a36Sopenharmony_cistatic const struct of_device_id apple_pwm_of_match[] = {
14562306a36Sopenharmony_ci	{ .compatible = "apple,s5l-fpwm" },
14662306a36Sopenharmony_ci	{}
14762306a36Sopenharmony_ci};
14862306a36Sopenharmony_ciMODULE_DEVICE_TABLE(of, apple_pwm_of_match);
14962306a36Sopenharmony_ci
15062306a36Sopenharmony_cistatic struct platform_driver apple_pwm_driver = {
15162306a36Sopenharmony_ci	.probe = apple_pwm_probe,
15262306a36Sopenharmony_ci	.driver = {
15362306a36Sopenharmony_ci		.name = "apple-pwm",
15462306a36Sopenharmony_ci		.of_match_table = apple_pwm_of_match,
15562306a36Sopenharmony_ci	},
15662306a36Sopenharmony_ci};
15762306a36Sopenharmony_cimodule_platform_driver(apple_pwm_driver);
15862306a36Sopenharmony_ci
15962306a36Sopenharmony_ciMODULE_DESCRIPTION("Apple SoC PWM driver");
16062306a36Sopenharmony_ciMODULE_LICENSE("Dual MIT/GPL");
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