1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#ifndef __SOC_MEDIATEK_MTK_PM_DOMAINS_H
4#define __SOC_MEDIATEK_MTK_PM_DOMAINS_H
5
6#define MTK_SCPD_ACTIVE_WAKEUP		BIT(0)
7#define MTK_SCPD_FWAIT_SRAM		BIT(1)
8#define MTK_SCPD_SRAM_ISO		BIT(2)
9#define MTK_SCPD_KEEP_DEFAULT_OFF	BIT(3)
10#define MTK_SCPD_DOMAIN_SUPPLY		BIT(4)
11/* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */
12#define MTK_SCPD_ALWAYS_ON		BIT(5)
13#define MTK_SCPD_EXT_BUCK_ISO		BIT(6)
14#define MTK_SCPD_CAPS(_scpd, _x)	((_scpd)->data->caps & (_x))
15
16#define SPM_VDE_PWR_CON			0x0210
17#define SPM_MFG_PWR_CON			0x0214
18#define SPM_VEN_PWR_CON			0x0230
19#define SPM_ISP_PWR_CON			0x0238
20#define SPM_DIS_PWR_CON			0x023c
21#define SPM_CONN_PWR_CON		0x0280
22#define SPM_VEN2_PWR_CON		0x0298
23#define SPM_AUDIO_PWR_CON		0x029c
24#define SPM_MFG_2D_PWR_CON		0x02c0
25#define SPM_MFG_ASYNC_PWR_CON		0x02c4
26#define SPM_USB_PWR_CON			0x02cc
27
28#define SPM_PWR_STATUS			0x060c
29#define SPM_PWR_STATUS_2ND		0x0610
30
31#define PWR_STATUS_CONN			BIT(1)
32#define PWR_STATUS_DISP			BIT(3)
33#define PWR_STATUS_MFG			BIT(4)
34#define PWR_STATUS_ISP			BIT(5)
35#define PWR_STATUS_VDEC			BIT(7)
36#define PWR_STATUS_VENC_LT		BIT(20)
37#define PWR_STATUS_VENC			BIT(21)
38#define PWR_STATUS_MFG_2D		BIT(22)
39#define PWR_STATUS_MFG_ASYNC		BIT(23)
40#define PWR_STATUS_AUDIO		BIT(24)
41#define PWR_STATUS_USB			BIT(25)
42
43#define SPM_MAX_BUS_PROT_DATA		6
44
45#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) {	\
46		.bus_prot_mask = (_mask),			\
47		.bus_prot_set = _set,				\
48		.bus_prot_clr = _clr,				\
49		.bus_prot_sta = _sta,				\
50		.bus_prot_reg_update = _update,			\
51		.ignore_clr_ack = _ignore,			\
52	}
53
54#define BUS_PROT_WR(_mask, _set, _clr, _sta)			\
55		_BUS_PROT(_mask, _set, _clr, _sta, false, false)
56
57#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta)		\
58		_BUS_PROT(_mask, _set, _clr, _sta, false, true)
59
60#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta)		\
61		_BUS_PROT(_mask, _set, _clr, _sta, true, false)
62
63#define BUS_PROT_UPDATE_TOPAXI(_mask)				\
64		BUS_PROT_UPDATE(_mask,				\
65				INFRA_TOPAXI_PROTECTEN,		\
66				INFRA_TOPAXI_PROTECTEN,		\
67				INFRA_TOPAXI_PROTECTSTA1)
68
69struct scpsys_bus_prot_data {
70	u32 bus_prot_mask;
71	u32 bus_prot_set;
72	u32 bus_prot_clr;
73	u32 bus_prot_sta;
74	bool bus_prot_reg_update;
75	bool ignore_clr_ack;
76};
77
78/**
79 * struct scpsys_domain_data - scp domain data for power on/off flow
80 * @name: The name of the power domain.
81 * @sta_mask: The mask for power on/off status bit.
82 * @ctl_offs: The offset for main power control register.
83 * @sram_pdn_bits: The mask for sram power control bits.
84 * @sram_pdn_ack_bits: The mask for sram power control acked bits.
85 * @ext_buck_iso_offs: The offset for external buck isolation
86 * @ext_buck_iso_mask: The mask for external buck isolation
87 * @caps: The flag for active wake-up action.
88 * @bp_infracfg: bus protection for infracfg subsystem
89 * @bp_smi: bus protection for smi subsystem
90 */
91struct scpsys_domain_data {
92	const char *name;
93	u32 sta_mask;
94	int ctl_offs;
95	u32 sram_pdn_bits;
96	u32 sram_pdn_ack_bits;
97	int ext_buck_iso_offs;
98	u32 ext_buck_iso_mask;
99	u8 caps;
100	const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA];
101	const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA];
102	int pwr_sta_offs;
103	int pwr_sta2nd_offs;
104};
105
106struct scpsys_soc_data {
107	const struct scpsys_domain_data *domains_data;
108	int num_domains;
109};
110
111#endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */
112