1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 */ 6 7#ifndef __SOC_MEDIATEK_MT8195_PM_DOMAINS_H 8#define __SOC_MEDIATEK_MT8195_PM_DOMAINS_H 9 10#include "mtk-pm-domains.h" 11#include <dt-bindings/power/mt8195-power.h> 12 13/* 14 * MT8195 power domain support 15 */ 16 17static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { 18 [MT8195_POWER_DOMAIN_PCIE_MAC_P0] = { 19 .name = "pcie_mac_p0", 20 .sta_mask = BIT(11), 21 .ctl_offs = 0x328, 22 .pwr_sta_offs = 0x174, 23 .pwr_sta2nd_offs = 0x178, 24 .sram_pdn_bits = GENMASK(8, 8), 25 .sram_pdn_ack_bits = GENMASK(12, 12), 26 .bp_infracfg = { 27 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0, 28 MT8195_TOP_AXI_PROT_EN_VDNR_SET, 29 MT8195_TOP_AXI_PROT_EN_VDNR_CLR, 30 MT8195_TOP_AXI_PROT_EN_VDNR_STA1), 31 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0, 32 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 33 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 34 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 35 }, 36 }, 37 [MT8195_POWER_DOMAIN_PCIE_MAC_P1] = { 38 .name = "pcie_mac_p1", 39 .sta_mask = BIT(12), 40 .ctl_offs = 0x32C, 41 .pwr_sta_offs = 0x174, 42 .pwr_sta2nd_offs = 0x178, 43 .sram_pdn_bits = GENMASK(8, 8), 44 .sram_pdn_ack_bits = GENMASK(12, 12), 45 .bp_infracfg = { 46 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1, 47 MT8195_TOP_AXI_PROT_EN_VDNR_SET, 48 MT8195_TOP_AXI_PROT_EN_VDNR_CLR, 49 MT8195_TOP_AXI_PROT_EN_VDNR_STA1), 50 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1, 51 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 52 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 53 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 54 }, 55 }, 56 [MT8195_POWER_DOMAIN_PCIE_PHY] = { 57 .name = "pcie_phy", 58 .sta_mask = BIT(13), 59 .ctl_offs = 0x330, 60 .pwr_sta_offs = 0x174, 61 .pwr_sta2nd_offs = 0x178, 62 .caps = MTK_SCPD_ACTIVE_WAKEUP, 63 }, 64 [MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY] = { 65 .name = "ssusb_pcie_phy", 66 .sta_mask = BIT(14), 67 .ctl_offs = 0x334, 68 .pwr_sta_offs = 0x174, 69 .pwr_sta2nd_offs = 0x178, 70 .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_ALWAYS_ON, 71 }, 72 [MT8195_POWER_DOMAIN_CSI_RX_TOP] = { 73 .name = "csi_rx_top", 74 .sta_mask = BIT(18), 75 .ctl_offs = 0x3C4, 76 .pwr_sta_offs = 0x174, 77 .pwr_sta2nd_offs = 0x178, 78 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 79 }, 80 [MT8195_POWER_DOMAIN_ETHER] = { 81 .name = "ether", 82 .sta_mask = BIT(3), 83 .ctl_offs = 0x344, 84 .pwr_sta_offs = 0x16c, 85 .pwr_sta2nd_offs = 0x170, 86 .sram_pdn_bits = GENMASK(8, 8), 87 .sram_pdn_ack_bits = GENMASK(12, 12), 88 .caps = MTK_SCPD_ACTIVE_WAKEUP, 89 }, 90 [MT8195_POWER_DOMAIN_ADSP] = { 91 .name = "adsp", 92 .sta_mask = BIT(10), 93 .ctl_offs = 0x360, 94 .pwr_sta_offs = 0x16c, 95 .pwr_sta2nd_offs = 0x170, 96 .sram_pdn_bits = GENMASK(8, 8), 97 .sram_pdn_ack_bits = GENMASK(12, 12), 98 .bp_infracfg = { 99 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP, 100 MT8195_TOP_AXI_PROT_EN_2_SET, 101 MT8195_TOP_AXI_PROT_EN_2_CLR, 102 MT8195_TOP_AXI_PROT_EN_2_STA1), 103 }, 104 .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, 105 }, 106 [MT8195_POWER_DOMAIN_AUDIO] = { 107 .name = "audio", 108 .sta_mask = BIT(8), 109 .ctl_offs = 0x358, 110 .pwr_sta_offs = 0x16c, 111 .pwr_sta2nd_offs = 0x170, 112 .sram_pdn_bits = GENMASK(8, 8), 113 .sram_pdn_ack_bits = GENMASK(12, 12), 114 .bp_infracfg = { 115 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO, 116 MT8195_TOP_AXI_PROT_EN_2_SET, 117 MT8195_TOP_AXI_PROT_EN_2_CLR, 118 MT8195_TOP_AXI_PROT_EN_2_STA1), 119 }, 120 }, 121 [MT8195_POWER_DOMAIN_MFG0] = { 122 .name = "mfg0", 123 .sta_mask = BIT(1), 124 .ctl_offs = 0x300, 125 .pwr_sta_offs = 0x174, 126 .pwr_sta2nd_offs = 0x178, 127 .sram_pdn_bits = GENMASK(8, 8), 128 .sram_pdn_ack_bits = GENMASK(12, 12), 129 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 130 }, 131 [MT8195_POWER_DOMAIN_MFG1] = { 132 .name = "mfg1", 133 .sta_mask = BIT(2), 134 .ctl_offs = 0x304, 135 .pwr_sta_offs = 0x174, 136 .pwr_sta2nd_offs = 0x178, 137 .sram_pdn_bits = GENMASK(8, 8), 138 .sram_pdn_ack_bits = GENMASK(12, 12), 139 .bp_infracfg = { 140 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1, 141 MT8195_TOP_AXI_PROT_EN_SET, 142 MT8195_TOP_AXI_PROT_EN_CLR, 143 MT8195_TOP_AXI_PROT_EN_STA1), 144 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1, 145 MT8195_TOP_AXI_PROT_EN_2_SET, 146 MT8195_TOP_AXI_PROT_EN_2_CLR, 147 MT8195_TOP_AXI_PROT_EN_2_STA1), 148 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1, 149 MT8195_TOP_AXI_PROT_EN_1_SET, 150 MT8195_TOP_AXI_PROT_EN_1_CLR, 151 MT8195_TOP_AXI_PROT_EN_1_STA1), 152 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, 153 MT8195_TOP_AXI_PROT_EN_2_SET, 154 MT8195_TOP_AXI_PROT_EN_2_CLR, 155 MT8195_TOP_AXI_PROT_EN_2_STA1), 156 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND, 157 MT8195_TOP_AXI_PROT_EN_SET, 158 MT8195_TOP_AXI_PROT_EN_CLR, 159 MT8195_TOP_AXI_PROT_EN_STA1), 160 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1, 161 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 162 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 163 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), 164 }, 165 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 166 }, 167 [MT8195_POWER_DOMAIN_MFG2] = { 168 .name = "mfg2", 169 .sta_mask = BIT(3), 170 .ctl_offs = 0x308, 171 .pwr_sta_offs = 0x174, 172 .pwr_sta2nd_offs = 0x178, 173 .sram_pdn_bits = GENMASK(8, 8), 174 .sram_pdn_ack_bits = GENMASK(12, 12), 175 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 176 }, 177 [MT8195_POWER_DOMAIN_MFG3] = { 178 .name = "mfg3", 179 .sta_mask = BIT(4), 180 .ctl_offs = 0x30C, 181 .pwr_sta_offs = 0x174, 182 .pwr_sta2nd_offs = 0x178, 183 .sram_pdn_bits = GENMASK(8, 8), 184 .sram_pdn_ack_bits = GENMASK(12, 12), 185 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 186 }, 187 [MT8195_POWER_DOMAIN_MFG4] = { 188 .name = "mfg4", 189 .sta_mask = BIT(5), 190 .ctl_offs = 0x310, 191 .pwr_sta_offs = 0x174, 192 .pwr_sta2nd_offs = 0x178, 193 .sram_pdn_bits = GENMASK(8, 8), 194 .sram_pdn_ack_bits = GENMASK(12, 12), 195 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 196 }, 197 [MT8195_POWER_DOMAIN_MFG5] = { 198 .name = "mfg5", 199 .sta_mask = BIT(6), 200 .ctl_offs = 0x314, 201 .pwr_sta_offs = 0x174, 202 .pwr_sta2nd_offs = 0x178, 203 .sram_pdn_bits = GENMASK(8, 8), 204 .sram_pdn_ack_bits = GENMASK(12, 12), 205 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 206 }, 207 [MT8195_POWER_DOMAIN_MFG6] = { 208 .name = "mfg6", 209 .sta_mask = BIT(7), 210 .ctl_offs = 0x318, 211 .pwr_sta_offs = 0x174, 212 .pwr_sta2nd_offs = 0x178, 213 .sram_pdn_bits = GENMASK(8, 8), 214 .sram_pdn_ack_bits = GENMASK(12, 12), 215 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 216 }, 217 [MT8195_POWER_DOMAIN_VPPSYS0] = { 218 .name = "vppsys0", 219 .sta_mask = BIT(11), 220 .ctl_offs = 0x364, 221 .pwr_sta_offs = 0x16c, 222 .pwr_sta2nd_offs = 0x170, 223 .sram_pdn_bits = GENMASK(8, 8), 224 .sram_pdn_ack_bits = GENMASK(12, 12), 225 .bp_infracfg = { 226 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0, 227 MT8195_TOP_AXI_PROT_EN_SET, 228 MT8195_TOP_AXI_PROT_EN_CLR, 229 MT8195_TOP_AXI_PROT_EN_STA1), 230 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0, 231 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 232 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 233 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 234 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, 235 MT8195_TOP_AXI_PROT_EN_SET, 236 MT8195_TOP_AXI_PROT_EN_CLR, 237 MT8195_TOP_AXI_PROT_EN_STA1), 238 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND, 239 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 240 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 241 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 242 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0, 243 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 244 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 245 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), 246 }, 247 }, 248 [MT8195_POWER_DOMAIN_VDOSYS0] = { 249 .name = "vdosys0", 250 .sta_mask = BIT(13), 251 .ctl_offs = 0x36C, 252 .pwr_sta_offs = 0x16c, 253 .pwr_sta2nd_offs = 0x170, 254 .sram_pdn_bits = GENMASK(8, 8), 255 .sram_pdn_ack_bits = GENMASK(12, 12), 256 .bp_infracfg = { 257 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0, 258 MT8195_TOP_AXI_PROT_EN_MM_SET, 259 MT8195_TOP_AXI_PROT_EN_MM_CLR, 260 MT8195_TOP_AXI_PROT_EN_MM_STA1), 261 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0, 262 MT8195_TOP_AXI_PROT_EN_SET, 263 MT8195_TOP_AXI_PROT_EN_CLR, 264 MT8195_TOP_AXI_PROT_EN_STA1), 265 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0, 266 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 267 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 268 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), 269 }, 270 }, 271 [MT8195_POWER_DOMAIN_VPPSYS1] = { 272 .name = "vppsys1", 273 .sta_mask = BIT(12), 274 .ctl_offs = 0x368, 275 .pwr_sta_offs = 0x16c, 276 .pwr_sta2nd_offs = 0x170, 277 .sram_pdn_bits = GENMASK(8, 8), 278 .sram_pdn_ack_bits = GENMASK(12, 12), 279 .bp_infracfg = { 280 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, 281 MT8195_TOP_AXI_PROT_EN_MM_SET, 282 MT8195_TOP_AXI_PROT_EN_MM_CLR, 283 MT8195_TOP_AXI_PROT_EN_MM_STA1), 284 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND, 285 MT8195_TOP_AXI_PROT_EN_MM_SET, 286 MT8195_TOP_AXI_PROT_EN_MM_CLR, 287 MT8195_TOP_AXI_PROT_EN_MM_STA1), 288 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1, 289 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 290 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 291 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 292 }, 293 }, 294 [MT8195_POWER_DOMAIN_VDOSYS1] = { 295 .name = "vdosys1", 296 .sta_mask = BIT(14), 297 .ctl_offs = 0x370, 298 .pwr_sta_offs = 0x16c, 299 .pwr_sta2nd_offs = 0x170, 300 .sram_pdn_bits = GENMASK(8, 8), 301 .sram_pdn_ack_bits = GENMASK(12, 12), 302 .bp_infracfg = { 303 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, 304 MT8195_TOP_AXI_PROT_EN_MM_SET, 305 MT8195_TOP_AXI_PROT_EN_MM_CLR, 306 MT8195_TOP_AXI_PROT_EN_MM_STA1), 307 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND, 308 MT8195_TOP_AXI_PROT_EN_MM_SET, 309 MT8195_TOP_AXI_PROT_EN_MM_CLR, 310 MT8195_TOP_AXI_PROT_EN_MM_STA1), 311 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1, 312 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 313 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 314 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 315 }, 316 }, 317 [MT8195_POWER_DOMAIN_DP_TX] = { 318 .name = "dp_tx", 319 .sta_mask = BIT(16), 320 .ctl_offs = 0x378, 321 .pwr_sta_offs = 0x16c, 322 .pwr_sta2nd_offs = 0x170, 323 .sram_pdn_bits = GENMASK(8, 8), 324 .sram_pdn_ack_bits = GENMASK(12, 12), 325 .bp_infracfg = { 326 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX, 327 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 328 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 329 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 330 }, 331 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 332 }, 333 [MT8195_POWER_DOMAIN_EPD_TX] = { 334 .name = "epd_tx", 335 .sta_mask = BIT(17), 336 .ctl_offs = 0x37C, 337 .pwr_sta_offs = 0x16c, 338 .pwr_sta2nd_offs = 0x170, 339 .sram_pdn_bits = GENMASK(8, 8), 340 .sram_pdn_ack_bits = GENMASK(12, 12), 341 .bp_infracfg = { 342 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX, 343 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 344 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 345 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 346 }, 347 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 348 }, 349 [MT8195_POWER_DOMAIN_HDMI_TX] = { 350 .name = "hdmi_tx", 351 .sta_mask = BIT(18), 352 .ctl_offs = 0x380, 353 .pwr_sta_offs = 0x16c, 354 .pwr_sta2nd_offs = 0x170, 355 .sram_pdn_bits = GENMASK(8, 8), 356 .sram_pdn_ack_bits = GENMASK(12, 12), 357 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 358 }, 359 [MT8195_POWER_DOMAIN_WPESYS] = { 360 .name = "wpesys", 361 .sta_mask = BIT(15), 362 .ctl_offs = 0x374, 363 .pwr_sta_offs = 0x16c, 364 .pwr_sta2nd_offs = 0x170, 365 .sram_pdn_bits = GENMASK(8, 8), 366 .sram_pdn_ack_bits = GENMASK(12, 12), 367 .bp_infracfg = { 368 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, 369 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 370 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 371 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 372 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS, 373 MT8195_TOP_AXI_PROT_EN_MM_SET, 374 MT8195_TOP_AXI_PROT_EN_MM_CLR, 375 MT8195_TOP_AXI_PROT_EN_MM_STA1), 376 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND, 377 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 378 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 379 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 380 }, 381 }, 382 [MT8195_POWER_DOMAIN_VDEC0] = { 383 .name = "vdec0", 384 .sta_mask = BIT(20), 385 .ctl_offs = 0x388, 386 .pwr_sta_offs = 0x16c, 387 .pwr_sta2nd_offs = 0x170, 388 .sram_pdn_bits = GENMASK(8, 8), 389 .sram_pdn_ack_bits = GENMASK(12, 12), 390 .bp_infracfg = { 391 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0, 392 MT8195_TOP_AXI_PROT_EN_MM_SET, 393 MT8195_TOP_AXI_PROT_EN_MM_CLR, 394 MT8195_TOP_AXI_PROT_EN_MM_STA1), 395 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, 396 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 397 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 398 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 399 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND, 400 MT8195_TOP_AXI_PROT_EN_MM_SET, 401 MT8195_TOP_AXI_PROT_EN_MM_CLR, 402 MT8195_TOP_AXI_PROT_EN_MM_STA1), 403 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND, 404 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 405 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 406 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 407 }, 408 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 409 }, 410 [MT8195_POWER_DOMAIN_VDEC1] = { 411 .name = "vdec1", 412 .sta_mask = BIT(21), 413 .ctl_offs = 0x38C, 414 .pwr_sta_offs = 0x16c, 415 .pwr_sta2nd_offs = 0x170, 416 .sram_pdn_bits = GENMASK(8, 8), 417 .sram_pdn_ack_bits = GENMASK(12, 12), 418 .bp_infracfg = { 419 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1, 420 MT8195_TOP_AXI_PROT_EN_MM_SET, 421 MT8195_TOP_AXI_PROT_EN_MM_CLR, 422 MT8195_TOP_AXI_PROT_EN_MM_STA1), 423 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND, 424 MT8195_TOP_AXI_PROT_EN_MM_SET, 425 MT8195_TOP_AXI_PROT_EN_MM_CLR, 426 MT8195_TOP_AXI_PROT_EN_MM_STA1), 427 }, 428 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 429 }, 430 [MT8195_POWER_DOMAIN_VDEC2] = { 431 .name = "vdec2", 432 .sta_mask = BIT(22), 433 .ctl_offs = 0x390, 434 .pwr_sta_offs = 0x16c, 435 .pwr_sta2nd_offs = 0x170, 436 .sram_pdn_bits = GENMASK(8, 8), 437 .sram_pdn_ack_bits = GENMASK(12, 12), 438 .bp_infracfg = { 439 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, 440 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 441 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 442 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 443 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND, 444 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 445 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 446 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 447 }, 448 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 449 }, 450 [MT8195_POWER_DOMAIN_VENC] = { 451 .name = "venc", 452 .sta_mask = BIT(23), 453 .ctl_offs = 0x394, 454 .pwr_sta_offs = 0x16c, 455 .pwr_sta2nd_offs = 0x170, 456 .sram_pdn_bits = GENMASK(8, 8), 457 .sram_pdn_ack_bits = GENMASK(12, 12), 458 .bp_infracfg = { 459 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC, 460 MT8195_TOP_AXI_PROT_EN_MM_SET, 461 MT8195_TOP_AXI_PROT_EN_MM_CLR, 462 MT8195_TOP_AXI_PROT_EN_MM_STA1), 463 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, 464 MT8195_TOP_AXI_PROT_EN_MM_SET, 465 MT8195_TOP_AXI_PROT_EN_MM_CLR, 466 MT8195_TOP_AXI_PROT_EN_MM_STA1), 467 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC, 468 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 469 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 470 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 471 }, 472 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 473 }, 474 [MT8195_POWER_DOMAIN_VENC_CORE1] = { 475 .name = "venc_core1", 476 .sta_mask = BIT(24), 477 .ctl_offs = 0x398, 478 .pwr_sta_offs = 0x16c, 479 .pwr_sta2nd_offs = 0x170, 480 .sram_pdn_bits = GENMASK(8, 8), 481 .sram_pdn_ack_bits = GENMASK(12, 12), 482 .bp_infracfg = { 483 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1, 484 MT8195_TOP_AXI_PROT_EN_MM_SET, 485 MT8195_TOP_AXI_PROT_EN_MM_CLR, 486 MT8195_TOP_AXI_PROT_EN_MM_STA1), 487 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1, 488 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 489 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 490 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 491 }, 492 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 493 }, 494 [MT8195_POWER_DOMAIN_IMG] = { 495 .name = "img", 496 .sta_mask = BIT(29), 497 .ctl_offs = 0x3AC, 498 .pwr_sta_offs = 0x16c, 499 .pwr_sta2nd_offs = 0x170, 500 .sram_pdn_bits = GENMASK(8, 8), 501 .sram_pdn_ack_bits = GENMASK(12, 12), 502 .bp_infracfg = { 503 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG, 504 MT8195_TOP_AXI_PROT_EN_MM_SET, 505 MT8195_TOP_AXI_PROT_EN_MM_CLR, 506 MT8195_TOP_AXI_PROT_EN_MM_STA1), 507 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, 508 MT8195_TOP_AXI_PROT_EN_MM_SET, 509 MT8195_TOP_AXI_PROT_EN_MM_CLR, 510 MT8195_TOP_AXI_PROT_EN_MM_STA1), 511 }, 512 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 513 }, 514 [MT8195_POWER_DOMAIN_DIP] = { 515 .name = "dip", 516 .sta_mask = BIT(30), 517 .ctl_offs = 0x3B0, 518 .pwr_sta_offs = 0x16c, 519 .pwr_sta2nd_offs = 0x170, 520 .sram_pdn_bits = GENMASK(8, 8), 521 .sram_pdn_ack_bits = GENMASK(12, 12), 522 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 523 }, 524 [MT8195_POWER_DOMAIN_IPE] = { 525 .name = "ipe", 526 .sta_mask = BIT(31), 527 .ctl_offs = 0x3B4, 528 .pwr_sta_offs = 0x16c, 529 .pwr_sta2nd_offs = 0x170, 530 .sram_pdn_bits = GENMASK(8, 8), 531 .sram_pdn_ack_bits = GENMASK(12, 12), 532 .bp_infracfg = { 533 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE, 534 MT8195_TOP_AXI_PROT_EN_MM_SET, 535 MT8195_TOP_AXI_PROT_EN_MM_CLR, 536 MT8195_TOP_AXI_PROT_EN_MM_STA1), 537 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE, 538 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 539 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 540 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 541 }, 542 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 543 }, 544 [MT8195_POWER_DOMAIN_CAM] = { 545 .name = "cam", 546 .sta_mask = BIT(25), 547 .ctl_offs = 0x39C, 548 .pwr_sta_offs = 0x16c, 549 .pwr_sta2nd_offs = 0x170, 550 .sram_pdn_bits = GENMASK(8, 8), 551 .sram_pdn_ack_bits = GENMASK(12, 12), 552 .bp_infracfg = { 553 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_CAM, 554 MT8195_TOP_AXI_PROT_EN_2_SET, 555 MT8195_TOP_AXI_PROT_EN_2_CLR, 556 MT8195_TOP_AXI_PROT_EN_2_STA1), 557 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM, 558 MT8195_TOP_AXI_PROT_EN_MM_SET, 559 MT8195_TOP_AXI_PROT_EN_MM_CLR, 560 MT8195_TOP_AXI_PROT_EN_MM_STA1), 561 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_CAM, 562 MT8195_TOP_AXI_PROT_EN_1_SET, 563 MT8195_TOP_AXI_PROT_EN_1_CLR, 564 MT8195_TOP_AXI_PROT_EN_1_STA1), 565 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, 566 MT8195_TOP_AXI_PROT_EN_MM_SET, 567 MT8195_TOP_AXI_PROT_EN_MM_CLR, 568 MT8195_TOP_AXI_PROT_EN_MM_STA1), 569 BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM, 570 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 571 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 572 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 573 }, 574 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 575 }, 576 [MT8195_POWER_DOMAIN_CAM_RAWA] = { 577 .name = "cam_rawa", 578 .sta_mask = BIT(26), 579 .ctl_offs = 0x3A0, 580 .pwr_sta_offs = 0x16c, 581 .pwr_sta2nd_offs = 0x170, 582 .sram_pdn_bits = GENMASK(8, 8), 583 .sram_pdn_ack_bits = GENMASK(12, 12), 584 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 585 }, 586 [MT8195_POWER_DOMAIN_CAM_RAWB] = { 587 .name = "cam_rawb", 588 .sta_mask = BIT(27), 589 .ctl_offs = 0x3A4, 590 .pwr_sta_offs = 0x16c, 591 .pwr_sta2nd_offs = 0x170, 592 .sram_pdn_bits = GENMASK(8, 8), 593 .sram_pdn_ack_bits = GENMASK(12, 12), 594 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 595 }, 596 [MT8195_POWER_DOMAIN_CAM_MRAW] = { 597 .name = "cam_mraw", 598 .sta_mask = BIT(28), 599 .ctl_offs = 0x3A8, 600 .pwr_sta_offs = 0x16c, 601 .pwr_sta2nd_offs = 0x170, 602 .sram_pdn_bits = GENMASK(8, 8), 603 .sram_pdn_ack_bits = GENMASK(12, 12), 604 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 605 }, 606}; 607 608static const struct scpsys_soc_data mt8195_scpsys_data = { 609 .domains_data = scpsys_domain_data_mt8195, 610 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8195), 611}; 612 613#endif /* __SOC_MEDIATEK_MT8195_PM_DOMAINS_H */ 614