1/* SPDX-License-Identifier: GPL-2.0-only */ 2 3#ifndef __SOC_MEDIATEK_MT8183_PM_DOMAINS_H 4#define __SOC_MEDIATEK_MT8183_PM_DOMAINS_H 5 6#include "mtk-pm-domains.h" 7#include <dt-bindings/power/mt8183-power.h> 8 9/* 10 * MT8183 power domain support 11 */ 12 13static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 14 [MT8183_POWER_DOMAIN_AUDIO] = { 15 .name = "audio", 16 .sta_mask = PWR_STATUS_AUDIO, 17 .ctl_offs = 0x0314, 18 .pwr_sta_offs = 0x0180, 19 .pwr_sta2nd_offs = 0x0184, 20 .sram_pdn_bits = GENMASK(11, 8), 21 .sram_pdn_ack_bits = GENMASK(15, 12), 22 }, 23 [MT8183_POWER_DOMAIN_CONN] = { 24 .name = "conn", 25 .sta_mask = PWR_STATUS_CONN, 26 .ctl_offs = 0x032c, 27 .pwr_sta_offs = 0x0180, 28 .pwr_sta2nd_offs = 0x0184, 29 .sram_pdn_bits = 0, 30 .sram_pdn_ack_bits = 0, 31 .bp_infracfg = { 32 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET, 33 MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), 34 }, 35 }, 36 [MT8183_POWER_DOMAIN_MFG_ASYNC] = { 37 .name = "mfg_async", 38 .sta_mask = PWR_STATUS_MFG_ASYNC, 39 .ctl_offs = 0x0334, 40 .pwr_sta_offs = 0x0180, 41 .pwr_sta2nd_offs = 0x0184, 42 .sram_pdn_bits = 0, 43 .sram_pdn_ack_bits = 0, 44 .caps = MTK_SCPD_DOMAIN_SUPPLY, 45 }, 46 [MT8183_POWER_DOMAIN_MFG] = { 47 .name = "mfg", 48 .sta_mask = PWR_STATUS_MFG, 49 .ctl_offs = 0x0338, 50 .pwr_sta_offs = 0x0180, 51 .pwr_sta2nd_offs = 0x0184, 52 .sram_pdn_bits = GENMASK(8, 8), 53 .sram_pdn_ack_bits = GENMASK(12, 12), 54 .caps = MTK_SCPD_DOMAIN_SUPPLY, 55 }, 56 [MT8183_POWER_DOMAIN_MFG_CORE0] = { 57 .name = "mfg_core0", 58 .sta_mask = BIT(7), 59 .ctl_offs = 0x034c, 60 .pwr_sta_offs = 0x0180, 61 .pwr_sta2nd_offs = 0x0184, 62 .sram_pdn_bits = GENMASK(8, 8), 63 .sram_pdn_ack_bits = GENMASK(12, 12), 64 }, 65 [MT8183_POWER_DOMAIN_MFG_CORE1] = { 66 .name = "mfg_core1", 67 .sta_mask = BIT(20), 68 .ctl_offs = 0x0310, 69 .pwr_sta_offs = 0x0180, 70 .pwr_sta2nd_offs = 0x0184, 71 .sram_pdn_bits = GENMASK(8, 8), 72 .sram_pdn_ack_bits = GENMASK(12, 12), 73 }, 74 [MT8183_POWER_DOMAIN_MFG_2D] = { 75 .name = "mfg_2d", 76 .sta_mask = PWR_STATUS_MFG_2D, 77 .ctl_offs = 0x0348, 78 .pwr_sta_offs = 0x0180, 79 .pwr_sta2nd_offs = 0x0184, 80 .sram_pdn_bits = GENMASK(8, 8), 81 .sram_pdn_ack_bits = GENMASK(12, 12), 82 .bp_infracfg = { 83 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET, 84 MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), 85 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET, 86 MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), 87 }, 88 }, 89 [MT8183_POWER_DOMAIN_DISP] = { 90 .name = "disp", 91 .sta_mask = PWR_STATUS_DISP, 92 .ctl_offs = 0x030c, 93 .pwr_sta_offs = 0x0180, 94 .pwr_sta2nd_offs = 0x0184, 95 .sram_pdn_bits = GENMASK(8, 8), 96 .sram_pdn_ack_bits = GENMASK(12, 12), 97 .bp_infracfg = { 98 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET, 99 MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), 100 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET, 101 MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), 102 }, 103 .bp_smi = { 104 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP, 105 MT8183_SMI_COMMON_CLAMP_EN_SET, 106 MT8183_SMI_COMMON_CLAMP_EN_CLR, 107 MT8183_SMI_COMMON_CLAMP_EN), 108 }, 109 }, 110 [MT8183_POWER_DOMAIN_CAM] = { 111 .name = "cam", 112 .sta_mask = BIT(25), 113 .ctl_offs = 0x0344, 114 .pwr_sta_offs = 0x0180, 115 .pwr_sta2nd_offs = 0x0184, 116 .sram_pdn_bits = GENMASK(9, 8), 117 .sram_pdn_ack_bits = GENMASK(13, 12), 118 .bp_infracfg = { 119 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SET, 120 MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), 121 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET, 122 MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), 123 BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND, 124 MT8183_TOP_AXI_PROT_EN_MM_SET, 125 MT8183_TOP_AXI_PROT_EN_MM_CLR, 126 MT8183_TOP_AXI_PROT_EN_MM_STA1), 127 }, 128 .bp_smi = { 129 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM, 130 MT8183_SMI_COMMON_CLAMP_EN_SET, 131 MT8183_SMI_COMMON_CLAMP_EN_CLR, 132 MT8183_SMI_COMMON_CLAMP_EN), 133 }, 134 }, 135 [MT8183_POWER_DOMAIN_ISP] = { 136 .name = "isp", 137 .sta_mask = PWR_STATUS_ISP, 138 .ctl_offs = 0x0308, 139 .pwr_sta_offs = 0x0180, 140 .pwr_sta2nd_offs = 0x0184, 141 .sram_pdn_bits = GENMASK(9, 8), 142 .sram_pdn_ack_bits = GENMASK(13, 12), 143 .bp_infracfg = { 144 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP, 145 MT8183_TOP_AXI_PROT_EN_MM_SET, 146 MT8183_TOP_AXI_PROT_EN_MM_CLR, 147 MT8183_TOP_AXI_PROT_EN_MM_STA1), 148 BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND, 149 MT8183_TOP_AXI_PROT_EN_MM_SET, 150 MT8183_TOP_AXI_PROT_EN_MM_CLR, 151 MT8183_TOP_AXI_PROT_EN_MM_STA1), 152 }, 153 .bp_smi = { 154 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP, 155 MT8183_SMI_COMMON_CLAMP_EN_SET, 156 MT8183_SMI_COMMON_CLAMP_EN_CLR, 157 MT8183_SMI_COMMON_CLAMP_EN), 158 }, 159 }, 160 [MT8183_POWER_DOMAIN_VDEC] = { 161 .name = "vdec", 162 .sta_mask = BIT(31), 163 .ctl_offs = 0x0300, 164 .pwr_sta_offs = 0x0180, 165 .pwr_sta2nd_offs = 0x0184, 166 .sram_pdn_bits = GENMASK(8, 8), 167 .sram_pdn_ack_bits = GENMASK(12, 12), 168 .bp_smi = { 169 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC, 170 MT8183_SMI_COMMON_CLAMP_EN_SET, 171 MT8183_SMI_COMMON_CLAMP_EN_CLR, 172 MT8183_SMI_COMMON_CLAMP_EN), 173 }, 174 }, 175 [MT8183_POWER_DOMAIN_VENC] = { 176 .name = "venc", 177 .sta_mask = PWR_STATUS_VENC, 178 .ctl_offs = 0x0304, 179 .pwr_sta_offs = 0x0180, 180 .pwr_sta2nd_offs = 0x0184, 181 .sram_pdn_bits = GENMASK(11, 8), 182 .sram_pdn_ack_bits = GENMASK(15, 12), 183 .bp_smi = { 184 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC, 185 MT8183_SMI_COMMON_CLAMP_EN_SET, 186 MT8183_SMI_COMMON_CLAMP_EN_CLR, 187 MT8183_SMI_COMMON_CLAMP_EN), 188 }, 189 }, 190 [MT8183_POWER_DOMAIN_VPU_TOP] = { 191 .name = "vpu_top", 192 .sta_mask = BIT(26), 193 .ctl_offs = 0x0324, 194 .pwr_sta_offs = 0x0180, 195 .pwr_sta2nd_offs = 0x0184, 196 .sram_pdn_bits = GENMASK(8, 8), 197 .sram_pdn_ack_bits = GENMASK(12, 12), 198 .bp_infracfg = { 199 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP, 200 MT8183_TOP_AXI_PROT_EN_MM_SET, 201 MT8183_TOP_AXI_PROT_EN_MM_CLR, 202 MT8183_TOP_AXI_PROT_EN_MM_STA1), 203 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP, 204 MT8183_TOP_AXI_PROT_EN_SET, 205 MT8183_TOP_AXI_PROT_EN_CLR, 206 MT8183_TOP_AXI_PROT_EN_STA1), 207 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND, 208 MT8183_TOP_AXI_PROT_EN_MM_SET, 209 MT8183_TOP_AXI_PROT_EN_MM_CLR, 210 MT8183_TOP_AXI_PROT_EN_MM_STA1), 211 }, 212 .bp_smi = { 213 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP, 214 MT8183_SMI_COMMON_CLAMP_EN_SET, 215 MT8183_SMI_COMMON_CLAMP_EN_CLR, 216 MT8183_SMI_COMMON_CLAMP_EN), 217 }, 218 }, 219 [MT8183_POWER_DOMAIN_VPU_CORE0] = { 220 .name = "vpu_core0", 221 .sta_mask = BIT(27), 222 .ctl_offs = 0x33c, 223 .pwr_sta_offs = 0x0180, 224 .pwr_sta2nd_offs = 0x0184, 225 .sram_pdn_bits = GENMASK(11, 8), 226 .sram_pdn_ack_bits = GENMASK(13, 12), 227 .bp_infracfg = { 228 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0, 229 MT8183_TOP_AXI_PROT_EN_MCU_SET, 230 MT8183_TOP_AXI_PROT_EN_MCU_CLR, 231 MT8183_TOP_AXI_PROT_EN_MCU_STA1), 232 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND, 233 MT8183_TOP_AXI_PROT_EN_MCU_SET, 234 MT8183_TOP_AXI_PROT_EN_MCU_CLR, 235 MT8183_TOP_AXI_PROT_EN_MCU_STA1), 236 }, 237 .caps = MTK_SCPD_SRAM_ISO, 238 }, 239 [MT8183_POWER_DOMAIN_VPU_CORE1] = { 240 .name = "vpu_core1", 241 .sta_mask = BIT(28), 242 .ctl_offs = 0x0340, 243 .pwr_sta_offs = 0x0180, 244 .pwr_sta2nd_offs = 0x0184, 245 .sram_pdn_bits = GENMASK(11, 8), 246 .sram_pdn_ack_bits = GENMASK(13, 12), 247 .bp_infracfg = { 248 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1, 249 MT8183_TOP_AXI_PROT_EN_MCU_SET, 250 MT8183_TOP_AXI_PROT_EN_MCU_CLR, 251 MT8183_TOP_AXI_PROT_EN_MCU_STA1), 252 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND, 253 MT8183_TOP_AXI_PROT_EN_MCU_SET, 254 MT8183_TOP_AXI_PROT_EN_MCU_CLR, 255 MT8183_TOP_AXI_PROT_EN_MCU_STA1), 256 }, 257 .caps = MTK_SCPD_SRAM_ISO, 258 }, 259}; 260 261static const struct scpsys_soc_data mt8183_scpsys_data = { 262 .domains_data = scpsys_domain_data_mt8183, 263 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183), 264}; 265 266#endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */ 267