1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2019 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 */ 6 7#include <linux/platform_device.h> 8#include <linux/pm_domain.h> 9#include <linux/bitfield.h> 10#include <linux/regmap.h> 11#include <linux/mfd/syscon.h> 12#include <linux/of.h> 13#include <linux/reset-controller.h> 14#include <linux/reset.h> 15#include <linux/clk.h> 16#include <linux/module.h> 17#include <dt-bindings/power/meson8-power.h> 18#include <dt-bindings/power/meson-axg-power.h> 19#include <dt-bindings/power/meson-g12a-power.h> 20#include <dt-bindings/power/meson-gxbb-power.h> 21#include <dt-bindings/power/meson-sm1-power.h> 22 23/* AO Offsets */ 24 25#define GX_AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2) 26#define GX_AO_RTI_GEN_PWR_ISO0 (0x3b << 2) 27 28/* 29 * Meson8/Meson8b/Meson8m2 only expose the power management registers of the 30 * AO-bus as syscon. 0x3a from GX translates to 0x02, 0x3b translates to 0x03 31 * and so on. 32 */ 33#define MESON8_AO_RTI_GEN_PWR_SLEEP0 (0x02 << 2) 34#define MESON8_AO_RTI_GEN_PWR_ISO0 (0x03 << 2) 35 36/* HHI Offsets */ 37 38#define HHI_MEM_PD_REG0 (0x40 << 2) 39#define HHI_VPU_MEM_PD_REG0 (0x41 << 2) 40#define HHI_VPU_MEM_PD_REG1 (0x42 << 2) 41#define HHI_VPU_MEM_PD_REG3 (0x43 << 2) 42#define HHI_VPU_MEM_PD_REG4 (0x44 << 2) 43#define HHI_AUDIO_MEM_PD_REG0 (0x45 << 2) 44#define HHI_NANOQ_MEM_PD_REG0 (0x46 << 2) 45#define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2) 46#define HHI_VPU_MEM_PD_REG2 (0x4d << 2) 47 48#define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2) 49#define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2) 50 51struct meson_ee_pwrc; 52struct meson_ee_pwrc_domain; 53 54struct meson_ee_pwrc_mem_domain { 55 unsigned int reg; 56 unsigned int mask; 57}; 58 59struct meson_ee_pwrc_top_domain { 60 unsigned int sleep_reg; 61 unsigned int sleep_mask; 62 unsigned int iso_reg; 63 unsigned int iso_mask; 64}; 65 66struct meson_ee_pwrc_domain_desc { 67 char *name; 68 unsigned int reset_names_count; 69 unsigned int clk_names_count; 70 struct meson_ee_pwrc_top_domain *top_pd; 71 unsigned int mem_pd_count; 72 struct meson_ee_pwrc_mem_domain *mem_pd; 73 bool (*is_powered_off)(struct meson_ee_pwrc_domain *pwrc_domain); 74}; 75 76struct meson_ee_pwrc_domain_data { 77 unsigned int count; 78 struct meson_ee_pwrc_domain_desc *domains; 79}; 80 81/* TOP Power Domains */ 82 83static struct meson_ee_pwrc_top_domain gx_pwrc_vpu = { 84 .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, 85 .sleep_mask = BIT(8), 86 .iso_reg = GX_AO_RTI_GEN_PWR_SLEEP0, 87 .iso_mask = BIT(9), 88}; 89 90static struct meson_ee_pwrc_top_domain meson8_pwrc_vpu = { 91 .sleep_reg = MESON8_AO_RTI_GEN_PWR_SLEEP0, 92 .sleep_mask = BIT(8), 93 .iso_reg = MESON8_AO_RTI_GEN_PWR_SLEEP0, 94 .iso_mask = BIT(9), 95}; 96 97#define SM1_EE_PD(__bit) \ 98 { \ 99 .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, \ 100 .sleep_mask = BIT(__bit), \ 101 .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, \ 102 .iso_mask = BIT(__bit), \ 103 } 104 105static struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8); 106static struct meson_ee_pwrc_top_domain sm1_pwrc_nna = SM1_EE_PD(16); 107static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17); 108static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18); 109static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19); 110 111static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = { 112 .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, 113 .sleep_mask = BIT(16) | BIT(17), 114 .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, 115 .iso_mask = BIT(16) | BIT(17), 116}; 117 118/* Memory PD Domains */ 119 120#define VPU_MEMPD(__reg) \ 121 { __reg, GENMASK(1, 0) }, \ 122 { __reg, GENMASK(3, 2) }, \ 123 { __reg, GENMASK(5, 4) }, \ 124 { __reg, GENMASK(7, 6) }, \ 125 { __reg, GENMASK(9, 8) }, \ 126 { __reg, GENMASK(11, 10) }, \ 127 { __reg, GENMASK(13, 12) }, \ 128 { __reg, GENMASK(15, 14) }, \ 129 { __reg, GENMASK(17, 16) }, \ 130 { __reg, GENMASK(19, 18) }, \ 131 { __reg, GENMASK(21, 20) }, \ 132 { __reg, GENMASK(23, 22) }, \ 133 { __reg, GENMASK(25, 24) }, \ 134 { __reg, GENMASK(27, 26) }, \ 135 { __reg, GENMASK(29, 28) }, \ 136 { __reg, GENMASK(31, 30) } 137 138#define VPU_HHI_MEMPD(__reg) \ 139 { __reg, BIT(8) }, \ 140 { __reg, BIT(9) }, \ 141 { __reg, BIT(10) }, \ 142 { __reg, BIT(11) }, \ 143 { __reg, BIT(12) }, \ 144 { __reg, BIT(13) }, \ 145 { __reg, BIT(14) }, \ 146 { __reg, BIT(15) } 147 148static struct meson_ee_pwrc_mem_domain axg_pwrc_mem_vpu[] = { 149 VPU_MEMPD(HHI_VPU_MEM_PD_REG0), 150 VPU_HHI_MEMPD(HHI_MEM_PD_REG0), 151}; 152 153static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = { 154 VPU_MEMPD(HHI_VPU_MEM_PD_REG0), 155 VPU_MEMPD(HHI_VPU_MEM_PD_REG1), 156 VPU_MEMPD(HHI_VPU_MEM_PD_REG2), 157 VPU_HHI_MEMPD(HHI_MEM_PD_REG0), 158}; 159 160static struct meson_ee_pwrc_mem_domain gxbb_pwrc_mem_vpu[] = { 161 VPU_MEMPD(HHI_VPU_MEM_PD_REG0), 162 VPU_MEMPD(HHI_VPU_MEM_PD_REG1), 163 VPU_HHI_MEMPD(HHI_MEM_PD_REG0), 164}; 165 166static struct meson_ee_pwrc_mem_domain meson_pwrc_mem_eth[] = { 167 { HHI_MEM_PD_REG0, GENMASK(3, 2) }, 168}; 169 170static struct meson_ee_pwrc_mem_domain meson8_pwrc_audio_dsp_mem[] = { 171 { HHI_MEM_PD_REG0, GENMASK(1, 0) }, 172}; 173 174static struct meson_ee_pwrc_mem_domain meson8_pwrc_mem_vpu[] = { 175 VPU_MEMPD(HHI_VPU_MEM_PD_REG0), 176 VPU_MEMPD(HHI_VPU_MEM_PD_REG1), 177 VPU_HHI_MEMPD(HHI_MEM_PD_REG0), 178}; 179 180static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = { 181 VPU_MEMPD(HHI_VPU_MEM_PD_REG0), 182 VPU_MEMPD(HHI_VPU_MEM_PD_REG1), 183 VPU_MEMPD(HHI_VPU_MEM_PD_REG2), 184 VPU_MEMPD(HHI_VPU_MEM_PD_REG3), 185 { HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) }, 186 { HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) }, 187 { HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) }, 188 { HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) }, 189 VPU_HHI_MEMPD(HHI_MEM_PD_REG0), 190}; 191 192static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_nna[] = { 193 { HHI_NANOQ_MEM_PD_REG0, 0xff }, 194 { HHI_NANOQ_MEM_PD_REG1, 0xff }, 195}; 196 197static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_usb[] = { 198 { HHI_MEM_PD_REG0, GENMASK(31, 30) }, 199}; 200 201static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_pcie[] = { 202 { HHI_MEM_PD_REG0, GENMASK(29, 26) }, 203}; 204 205static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = { 206 { HHI_MEM_PD_REG0, GENMASK(25, 18) }, 207}; 208 209static struct meson_ee_pwrc_mem_domain axg_pwrc_mem_audio[] = { 210 { HHI_MEM_PD_REG0, GENMASK(5, 4) }, 211}; 212 213static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = { 214 { HHI_MEM_PD_REG0, GENMASK(5, 4) }, 215 { HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) }, 216 { HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) }, 217 { HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) }, 218 { HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) }, 219 { HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) }, 220 { HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) }, 221 { HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) }, 222 { HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) }, 223 { HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) }, 224 { HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) }, 225 { HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) }, 226 { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) }, 227}; 228 229static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = { 230 { G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) }, 231 { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(31, 0) }, 232}; 233 234#define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \ 235 { \ 236 .name = __name, \ 237 .reset_names_count = __resets, \ 238 .clk_names_count = __clks, \ 239 .top_pd = __top_pd, \ 240 .mem_pd_count = ARRAY_SIZE(__mem), \ 241 .mem_pd = __mem, \ 242 .is_powered_off = __is_pwr_off, \ 243 } 244 245#define TOP_PD(__name, __top_pd, __mem, __is_pwr_off) \ 246 { \ 247 .name = __name, \ 248 .top_pd = __top_pd, \ 249 .mem_pd_count = ARRAY_SIZE(__mem), \ 250 .mem_pd = __mem, \ 251 .is_powered_off = __is_pwr_off, \ 252 } 253 254#define MEM_PD(__name, __mem) \ 255 TOP_PD(__name, NULL, __mem, NULL) 256 257static bool pwrc_ee_is_powered_off(struct meson_ee_pwrc_domain *pwrc_domain); 258 259static struct meson_ee_pwrc_domain_desc axg_pwrc_domains[] = { 260 [PWRC_AXG_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, axg_pwrc_mem_vpu, 261 pwrc_ee_is_powered_off, 5, 2), 262 [PWRC_AXG_ETHERNET_MEM_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), 263 [PWRC_AXG_AUDIO_ID] = MEM_PD("AUDIO", axg_pwrc_mem_audio), 264}; 265 266static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = { 267 [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu, 268 pwrc_ee_is_powered_off, 11, 2), 269 [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), 270 [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna, 271 pwrc_ee_is_powered_off), 272}; 273 274static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = { 275 [PWRC_GXBB_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, gxbb_pwrc_mem_vpu, 276 pwrc_ee_is_powered_off, 12, 2), 277 [PWRC_GXBB_ETHERNET_MEM_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), 278}; 279 280static struct meson_ee_pwrc_domain_desc meson8_pwrc_domains[] = { 281 [PWRC_MESON8_VPU_ID] = VPU_PD("VPU", &meson8_pwrc_vpu, 282 meson8_pwrc_mem_vpu, 283 pwrc_ee_is_powered_off, 0, 1), 284 [PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM", 285 meson_pwrc_mem_eth), 286 [PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM", 287 meson8_pwrc_audio_dsp_mem), 288}; 289 290static struct meson_ee_pwrc_domain_desc meson8b_pwrc_domains[] = { 291 [PWRC_MESON8_VPU_ID] = VPU_PD("VPU", &meson8_pwrc_vpu, 292 meson8_pwrc_mem_vpu, 293 pwrc_ee_is_powered_off, 11, 1), 294 [PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM", 295 meson_pwrc_mem_eth), 296 [PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM", 297 meson8_pwrc_audio_dsp_mem), 298}; 299 300static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = { 301 [PWRC_SM1_VPU_ID] = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu, 302 pwrc_ee_is_powered_off, 11, 2), 303 [PWRC_SM1_NNA_ID] = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna, 304 pwrc_ee_is_powered_off), 305 [PWRC_SM1_USB_ID] = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb, 306 pwrc_ee_is_powered_off), 307 [PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie, 308 pwrc_ee_is_powered_off), 309 [PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d, 310 pwrc_ee_is_powered_off), 311 [PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio), 312 [PWRC_SM1_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), 313}; 314 315struct meson_ee_pwrc_domain { 316 struct generic_pm_domain base; 317 bool enabled; 318 struct meson_ee_pwrc *pwrc; 319 struct meson_ee_pwrc_domain_desc desc; 320 struct clk_bulk_data *clks; 321 int num_clks; 322 struct reset_control *rstc; 323 int num_rstc; 324}; 325 326struct meson_ee_pwrc { 327 struct regmap *regmap_ao; 328 struct regmap *regmap_hhi; 329 struct meson_ee_pwrc_domain *domains; 330 struct genpd_onecell_data xlate; 331}; 332 333static bool pwrc_ee_is_powered_off(struct meson_ee_pwrc_domain *pwrc_domain) 334{ 335 u32 reg; 336 337 regmap_read(pwrc_domain->pwrc->regmap_ao, 338 pwrc_domain->desc.top_pd->sleep_reg, ®); 339 340 return (reg & pwrc_domain->desc.top_pd->sleep_mask); 341} 342 343static int meson_ee_pwrc_off(struct generic_pm_domain *domain) 344{ 345 struct meson_ee_pwrc_domain *pwrc_domain = 346 container_of(domain, struct meson_ee_pwrc_domain, base); 347 int i; 348 349 if (pwrc_domain->desc.top_pd) 350 regmap_update_bits(pwrc_domain->pwrc->regmap_ao, 351 pwrc_domain->desc.top_pd->sleep_reg, 352 pwrc_domain->desc.top_pd->sleep_mask, 353 pwrc_domain->desc.top_pd->sleep_mask); 354 udelay(20); 355 356 for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i) 357 regmap_update_bits(pwrc_domain->pwrc->regmap_hhi, 358 pwrc_domain->desc.mem_pd[i].reg, 359 pwrc_domain->desc.mem_pd[i].mask, 360 pwrc_domain->desc.mem_pd[i].mask); 361 362 udelay(20); 363 364 if (pwrc_domain->desc.top_pd) 365 regmap_update_bits(pwrc_domain->pwrc->regmap_ao, 366 pwrc_domain->desc.top_pd->iso_reg, 367 pwrc_domain->desc.top_pd->iso_mask, 368 pwrc_domain->desc.top_pd->iso_mask); 369 370 if (pwrc_domain->num_clks) { 371 msleep(20); 372 clk_bulk_disable_unprepare(pwrc_domain->num_clks, 373 pwrc_domain->clks); 374 } 375 376 return 0; 377} 378 379static int meson_ee_pwrc_on(struct generic_pm_domain *domain) 380{ 381 struct meson_ee_pwrc_domain *pwrc_domain = 382 container_of(domain, struct meson_ee_pwrc_domain, base); 383 int i, ret; 384 385 if (pwrc_domain->desc.top_pd) 386 regmap_update_bits(pwrc_domain->pwrc->regmap_ao, 387 pwrc_domain->desc.top_pd->sleep_reg, 388 pwrc_domain->desc.top_pd->sleep_mask, 0); 389 udelay(20); 390 391 for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i) 392 regmap_update_bits(pwrc_domain->pwrc->regmap_hhi, 393 pwrc_domain->desc.mem_pd[i].reg, 394 pwrc_domain->desc.mem_pd[i].mask, 0); 395 396 udelay(20); 397 398 ret = reset_control_assert(pwrc_domain->rstc); 399 if (ret) 400 return ret; 401 402 if (pwrc_domain->desc.top_pd) 403 regmap_update_bits(pwrc_domain->pwrc->regmap_ao, 404 pwrc_domain->desc.top_pd->iso_reg, 405 pwrc_domain->desc.top_pd->iso_mask, 0); 406 407 ret = reset_control_deassert(pwrc_domain->rstc); 408 if (ret) 409 return ret; 410 411 return clk_bulk_prepare_enable(pwrc_domain->num_clks, 412 pwrc_domain->clks); 413} 414 415static int meson_ee_pwrc_init_domain(struct platform_device *pdev, 416 struct meson_ee_pwrc *pwrc, 417 struct meson_ee_pwrc_domain *dom) 418{ 419 int ret; 420 421 dom->pwrc = pwrc; 422 dom->num_rstc = dom->desc.reset_names_count; 423 dom->num_clks = dom->desc.clk_names_count; 424 425 if (dom->num_rstc) { 426 int count = reset_control_get_count(&pdev->dev); 427 428 if (count != dom->num_rstc) 429 dev_warn(&pdev->dev, "Invalid resets count %d for domain %s\n", 430 count, dom->desc.name); 431 432 dom->rstc = devm_reset_control_array_get_exclusive(&pdev->dev); 433 if (IS_ERR(dom->rstc)) 434 return PTR_ERR(dom->rstc); 435 } 436 437 if (dom->num_clks) { 438 int ret = devm_clk_bulk_get_all(&pdev->dev, &dom->clks); 439 if (ret < 0) 440 return ret; 441 442 if (dom->num_clks != ret) { 443 dev_warn(&pdev->dev, "Invalid clocks count %d for domain %s\n", 444 ret, dom->desc.name); 445 dom->num_clks = ret; 446 } 447 } 448 449 dom->base.name = dom->desc.name; 450 dom->base.power_on = meson_ee_pwrc_on; 451 dom->base.power_off = meson_ee_pwrc_off; 452 453 /* 454 * TOFIX: This is a special case for the VPU power domain, which can 455 * be enabled previously by the bootloader. In this case the VPU 456 * pipeline may be functional but no driver maybe never attach 457 * to this power domain, and if the domain is disabled it could 458 * cause system errors. This is why the pm_domain_always_on_gov 459 * is used here. 460 * For the same reason, the clocks should be enabled in case 461 * we need to power the domain off, otherwise the internal clocks 462 * prepare/enable counters won't be in sync. 463 */ 464 if (dom->num_clks && dom->desc.is_powered_off && !dom->desc.is_powered_off(dom)) { 465 ret = clk_bulk_prepare_enable(dom->num_clks, dom->clks); 466 if (ret) 467 return ret; 468 469 dom->base.flags = GENPD_FLAG_ALWAYS_ON; 470 ret = pm_genpd_init(&dom->base, NULL, false); 471 if (ret) 472 return ret; 473 } else { 474 ret = pm_genpd_init(&dom->base, NULL, 475 (dom->desc.is_powered_off ? 476 dom->desc.is_powered_off(dom) : true)); 477 if (ret) 478 return ret; 479 } 480 481 return 0; 482} 483 484static int meson_ee_pwrc_probe(struct platform_device *pdev) 485{ 486 const struct meson_ee_pwrc_domain_data *match; 487 struct regmap *regmap_ao, *regmap_hhi; 488 struct device_node *parent_np; 489 struct meson_ee_pwrc *pwrc; 490 int i, ret; 491 492 match = of_device_get_match_data(&pdev->dev); 493 if (!match) { 494 dev_err(&pdev->dev, "failed to get match data\n"); 495 return -ENODEV; 496 } 497 498 pwrc = devm_kzalloc(&pdev->dev, sizeof(*pwrc), GFP_KERNEL); 499 if (!pwrc) 500 return -ENOMEM; 501 502 pwrc->xlate.domains = devm_kcalloc(&pdev->dev, match->count, 503 sizeof(*pwrc->xlate.domains), 504 GFP_KERNEL); 505 if (!pwrc->xlate.domains) 506 return -ENOMEM; 507 508 pwrc->domains = devm_kcalloc(&pdev->dev, match->count, 509 sizeof(*pwrc->domains), GFP_KERNEL); 510 if (!pwrc->domains) 511 return -ENOMEM; 512 513 pwrc->xlate.num_domains = match->count; 514 515 parent_np = of_get_parent(pdev->dev.of_node); 516 regmap_hhi = syscon_node_to_regmap(parent_np); 517 of_node_put(parent_np); 518 if (IS_ERR(regmap_hhi)) { 519 dev_err(&pdev->dev, "failed to get HHI regmap\n"); 520 return PTR_ERR(regmap_hhi); 521 } 522 523 regmap_ao = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 524 "amlogic,ao-sysctrl"); 525 if (IS_ERR(regmap_ao)) { 526 dev_err(&pdev->dev, "failed to get AO regmap\n"); 527 return PTR_ERR(regmap_ao); 528 } 529 530 pwrc->regmap_ao = regmap_ao; 531 pwrc->regmap_hhi = regmap_hhi; 532 533 platform_set_drvdata(pdev, pwrc); 534 535 for (i = 0 ; i < match->count ; ++i) { 536 struct meson_ee_pwrc_domain *dom = &pwrc->domains[i]; 537 538 memcpy(&dom->desc, &match->domains[i], sizeof(dom->desc)); 539 540 ret = meson_ee_pwrc_init_domain(pdev, pwrc, dom); 541 if (ret) 542 return ret; 543 544 pwrc->xlate.domains[i] = &dom->base; 545 } 546 547 return of_genpd_add_provider_onecell(pdev->dev.of_node, &pwrc->xlate); 548} 549 550static void meson_ee_pwrc_shutdown(struct platform_device *pdev) 551{ 552 struct meson_ee_pwrc *pwrc = platform_get_drvdata(pdev); 553 int i; 554 555 for (i = 0 ; i < pwrc->xlate.num_domains ; ++i) { 556 struct meson_ee_pwrc_domain *dom = &pwrc->domains[i]; 557 558 if (dom->desc.is_powered_off && !dom->desc.is_powered_off(dom)) 559 meson_ee_pwrc_off(&dom->base); 560 } 561} 562 563static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = { 564 .count = ARRAY_SIZE(g12a_pwrc_domains), 565 .domains = g12a_pwrc_domains, 566}; 567 568static struct meson_ee_pwrc_domain_data meson_ee_axg_pwrc_data = { 569 .count = ARRAY_SIZE(axg_pwrc_domains), 570 .domains = axg_pwrc_domains, 571}; 572 573static struct meson_ee_pwrc_domain_data meson_ee_gxbb_pwrc_data = { 574 .count = ARRAY_SIZE(gxbb_pwrc_domains), 575 .domains = gxbb_pwrc_domains, 576}; 577 578static struct meson_ee_pwrc_domain_data meson_ee_m8_pwrc_data = { 579 .count = ARRAY_SIZE(meson8_pwrc_domains), 580 .domains = meson8_pwrc_domains, 581}; 582 583static struct meson_ee_pwrc_domain_data meson_ee_m8b_pwrc_data = { 584 .count = ARRAY_SIZE(meson8b_pwrc_domains), 585 .domains = meson8b_pwrc_domains, 586}; 587 588static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = { 589 .count = ARRAY_SIZE(sm1_pwrc_domains), 590 .domains = sm1_pwrc_domains, 591}; 592 593static const struct of_device_id meson_ee_pwrc_match_table[] = { 594 { 595 .compatible = "amlogic,meson8-pwrc", 596 .data = &meson_ee_m8_pwrc_data, 597 }, 598 { 599 .compatible = "amlogic,meson8b-pwrc", 600 .data = &meson_ee_m8b_pwrc_data, 601 }, 602 { 603 .compatible = "amlogic,meson8m2-pwrc", 604 .data = &meson_ee_m8b_pwrc_data, 605 }, 606 { 607 .compatible = "amlogic,meson-axg-pwrc", 608 .data = &meson_ee_axg_pwrc_data, 609 }, 610 { 611 .compatible = "amlogic,meson-gxbb-pwrc", 612 .data = &meson_ee_gxbb_pwrc_data, 613 }, 614 { 615 .compatible = "amlogic,meson-g12a-pwrc", 616 .data = &meson_ee_g12a_pwrc_data, 617 }, 618 { 619 .compatible = "amlogic,meson-sm1-pwrc", 620 .data = &meson_ee_sm1_pwrc_data, 621 }, 622 { /* sentinel */ } 623}; 624MODULE_DEVICE_TABLE(of, meson_ee_pwrc_match_table); 625 626static struct platform_driver meson_ee_pwrc_driver = { 627 .probe = meson_ee_pwrc_probe, 628 .shutdown = meson_ee_pwrc_shutdown, 629 .driver = { 630 .name = "meson_ee_pwrc", 631 .of_match_table = meson_ee_pwrc_match_table, 632 }, 633}; 634module_platform_driver(meson_ee_pwrc_driver); 635MODULE_LICENSE("GPL v2"); 636