1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Driver for the NVIDIA Tegra pinmux 4 * 5 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 6 */ 7 8#ifndef __PINMUX_TEGRA_H__ 9#define __PINMUX_TEGRA_H__ 10 11struct tegra_pmx { 12 struct device *dev; 13 struct pinctrl_dev *pctl; 14 15 const struct tegra_pinctrl_soc_data *soc; 16 struct tegra_function *functions; 17 const char **group_pins; 18 19 struct pinctrl_gpio_range gpio_range; 20 struct pinctrl_desc desc; 21 int nbanks; 22 void __iomem **regs; 23 u32 *backup_regs; 24}; 25 26enum tegra_pinconf_param { 27 /* argument: tegra_pinconf_pull */ 28 TEGRA_PINCONF_PARAM_PULL, 29 /* argument: tegra_pinconf_tristate */ 30 TEGRA_PINCONF_PARAM_TRISTATE, 31 /* argument: Boolean */ 32 TEGRA_PINCONF_PARAM_ENABLE_INPUT, 33 /* argument: Boolean */ 34 TEGRA_PINCONF_PARAM_OPEN_DRAIN, 35 /* argument: Boolean */ 36 TEGRA_PINCONF_PARAM_LOCK, 37 /* argument: Boolean */ 38 TEGRA_PINCONF_PARAM_IORESET, 39 /* argument: Boolean */ 40 TEGRA_PINCONF_PARAM_RCV_SEL, 41 /* argument: Boolean */ 42 TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 43 /* argument: Boolean */ 44 TEGRA_PINCONF_PARAM_SCHMITT, 45 /* argument: Boolean */ 46 TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 47 /* argument: Integer, range is HW-dependant */ 48 TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 49 /* argument: Integer, range is HW-dependant */ 50 TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 51 /* argument: Integer, range is HW-dependant */ 52 TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 53 /* argument: Integer, range is HW-dependant */ 54 TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 55 /* argument: Integer, range is HW-dependant */ 56 TEGRA_PINCONF_PARAM_DRIVE_TYPE, 57}; 58 59enum tegra_pinconf_pull { 60 TEGRA_PINCONFIG_PULL_NONE, 61 TEGRA_PINCONFIG_PULL_DOWN, 62 TEGRA_PINCONFIG_PULL_UP, 63}; 64 65enum tegra_pinconf_tristate { 66 TEGRA_PINCONFIG_DRIVEN, 67 TEGRA_PINCONFIG_TRISTATE, 68}; 69 70#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_)) 71#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16) 72#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff) 73 74/** 75 * struct tegra_function - Tegra pinctrl mux function 76 * @name: The name of the function, exported to pinctrl core. 77 * @groups: An array of pin groups that may select this function. 78 * @ngroups: The number of entries in @groups. 79 */ 80struct tegra_function { 81 const char *name; 82 const char **groups; 83 unsigned ngroups; 84}; 85 86/** 87 * struct tegra_pingroup - Tegra pin group 88 * @name The name of the pin group. 89 * @pins An array of pin IDs included in this pin group. 90 * @npins The number of entries in @pins. 91 * @funcs The mux functions which can be muxed onto this group. 92 * @mux_reg: Mux register offset. 93 * This register contains the mux, einput, odrain, lock, 94 * ioreset, rcv_sel parameters. 95 * @mux_bank: Mux register bank. 96 * @mux_bit: Mux register bit. 97 * @pupd_reg: Pull-up/down register offset. 98 * @pupd_bank: Pull-up/down register bank. 99 * @pupd_bit: Pull-up/down register bit. 100 * @tri_reg: Tri-state register offset. 101 * @tri_bank: Tri-state register bank. 102 * @tri_bit: Tri-state register bit. 103 * @einput_bit: Enable-input register bit. 104 * @odrain_bit: Open-drain register bit. 105 * @lock_bit: Lock register bit. 106 * @ioreset_bit: IO reset register bit. 107 * @rcv_sel_bit: Receiver select bit. 108 * @drv_reg: Drive fields register offset. 109 * This register contains hsm, schmitt, lpmd, drvdn, 110 * drvup, slwr, slwf, and drvtype parameters. 111 * @drv_bank: Drive fields register bank. 112 * @hsm_bit: High Speed Mode register bit. 113 * @sfsel_bit: GPIO/SFIO selection register bit. 114 * @schmitt_bit: Schmitt register bit. 115 * @lpmd_bit: Low Power Mode register bit. 116 * @drvdn_bit: Drive Down register bit. 117 * @drvdn_width: Drive Down field width. 118 * @drvup_bit: Drive Up register bit. 119 * @drvup_width: Drive Up field width. 120 * @slwr_bit: Slew Rising register bit. 121 * @slwr_width: Slew Rising field width. 122 * @slwf_bit: Slew Falling register bit. 123 * @slwf_width: Slew Falling field width. 124 * @lpdr_bit: Base driver enabling bit. 125 * @drvtype_bit: Drive type register bit. 126 * @parked_bitmask: Parked register mask. 0 if unsupported. 127 * 128 * -1 in a *_reg field means that feature is unsupported for this group. 129 * *_bank and *_reg values are irrelevant when *_reg is -1. 130 * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature. 131 * 132 * A representation of a group of pins (possibly just one pin) in the Tegra 133 * pin controller. Each group allows some parameter or parameters to be 134 * configured. The most common is mux function selection. Many others exist 135 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex; 136 * certain groups may only support configuring certain parameters, hence 137 * each parameter is optional. 138 */ 139struct tegra_pingroup { 140 const char *name; 141 const unsigned *pins; 142 u8 npins; 143 u8 funcs[4]; 144 s32 mux_reg; 145 s32 pupd_reg; 146 s32 tri_reg; 147 s32 drv_reg; 148 u32 mux_bank:2; 149 u32 pupd_bank:2; 150 u32 tri_bank:2; 151 u32 drv_bank:2; 152 s32 mux_bit:6; 153 s32 pupd_bit:6; 154 s32 tri_bit:6; 155 s32 einput_bit:6; 156 s32 odrain_bit:6; 157 s32 lock_bit:6; 158 s32 ioreset_bit:6; 159 s32 rcv_sel_bit:6; 160 s32 hsm_bit:6; 161 s32 sfsel_bit:6; 162 s32 schmitt_bit:6; 163 s32 lpmd_bit:6; 164 s32 drvdn_bit:6; 165 s32 drvup_bit:6; 166 s32 slwr_bit:6; 167 s32 slwf_bit:6; 168 s32 lpdr_bit:6; 169 s32 drvtype_bit:6; 170 s32 drvdn_width:6; 171 s32 drvup_width:6; 172 s32 slwr_width:6; 173 s32 slwf_width:6; 174 u32 parked_bitmask; 175}; 176 177/** 178 * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration 179 * @ngpios: The number of GPIO pins the pin controller HW affects. 180 * @pins: An array describing all pins the pin controller affects. 181 * All pins which are also GPIOs must be listed first within the 182 * array, and be numbered identically to the GPIO controller's 183 * numbering. 184 * @npins: The numbmer of entries in @pins. 185 * @functions: An array describing all mux functions the SoC supports. 186 * @nfunctions: The numbmer of entries in @functions. 187 * @groups: An array describing all pin groups the pin SoC supports. 188 * @ngroups: The numbmer of entries in @groups. 189 */ 190struct tegra_pinctrl_soc_data { 191 unsigned ngpios; 192 const char *gpio_compatible; 193 const struct pinctrl_pin_desc *pins; 194 unsigned npins; 195 const char * const *functions; 196 unsigned nfunctions; 197 const struct tegra_pingroup *groups; 198 unsigned ngroups; 199 bool hsm_in_mux; 200 bool schmitt_in_mux; 201 bool drvtype_in_mux; 202 bool sfsel_in_mux; 203}; 204 205extern const struct dev_pm_ops tegra_pinctrl_pm; 206 207int tegra_pinctrl_probe(struct platform_device *pdev, 208 const struct tegra_pinctrl_soc_data *soc_data); 209#endif 210