1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Allwinner H616 SoC pinctrl driver. 4 * 5 * Copyright (C) 2020 Arm Ltd. 6 * based on the H6 pinctrl driver 7 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 8 */ 9 10#include <linux/module.h> 11#include <linux/platform_device.h> 12#include <linux/of.h> 13#include <linux/pinctrl/pinctrl.h> 14 15#include "pinctrl-sunxi.h" 16 17static const struct sunxi_desc_pin h616_pins[] = { 18 /* Internal connection to the AC200 part */ 19 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), 20 SUNXI_FUNCTION(0x2, "emac1")), /* ERXD1 */ 21 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), 22 SUNXI_FUNCTION(0x2, "emac1")), /* ERXD0 */ 23 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), 24 SUNXI_FUNCTION(0x2, "emac1")), /* ECRS_DV */ 25 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), 26 SUNXI_FUNCTION(0x2, "emac1")), /* ERXERR */ 27 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), 28 SUNXI_FUNCTION(0x2, "emac1")), /* ETXD1 */ 29 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), 30 SUNXI_FUNCTION(0x2, "emac1")), /* ETXD0 */ 31 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), 32 SUNXI_FUNCTION(0x2, "emac1")), /* ETXCK */ 33 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), 34 SUNXI_FUNCTION(0x2, "emac1")), /* ETXEN */ 35 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), 36 SUNXI_FUNCTION(0x2, "emac1")), /* EMDC */ 37 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), 38 SUNXI_FUNCTION(0x2, "emac1")), /* EMDIO */ 39 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), 40 SUNXI_FUNCTION(0x2, "i2c3")), /* SCK */ 41 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), 42 SUNXI_FUNCTION(0x2, "i2c3")), /* SDA */ 43 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), 44 SUNXI_FUNCTION(0x2, "pwm5")), 45 /* Hole */ 46 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), 47 SUNXI_FUNCTION(0x0, "gpio_in"), 48 SUNXI_FUNCTION(0x1, "gpio_out"), 49 SUNXI_FUNCTION(0x2, "nand0"), /* WE */ 50 SUNXI_FUNCTION(0x3, "mmc2"), /* DS */ 51 SUNXI_FUNCTION(0x4, "spi0"), /* CLK */ 52 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PC_EINT0 */ 53 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), 54 SUNXI_FUNCTION(0x0, "gpio_in"), 55 SUNXI_FUNCTION(0x1, "gpio_out"), 56 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ 57 SUNXI_FUNCTION(0x3, "mmc2"), /* RST */ 58 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PC_EINT1 */ 59 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), 60 SUNXI_FUNCTION(0x0, "gpio_in"), 61 SUNXI_FUNCTION(0x1, "gpio_out"), 62 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ 63 SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */ 64 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PC_EINT2 */ 65 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), 66 SUNXI_FUNCTION(0x0, "gpio_in"), 67 SUNXI_FUNCTION(0x1, "gpio_out"), 68 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ 69 SUNXI_FUNCTION(0x4, "spi0"), /* CS0 */ 70 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PC_EINT3 */ 71 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), 72 SUNXI_FUNCTION(0x0, "gpio_in"), 73 SUNXI_FUNCTION(0x1, "gpio_out"), 74 SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */ 75 SUNXI_FUNCTION(0x4, "spi0"), /* MISO */ 76 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PC_EINT4 */ 77 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), 78 SUNXI_FUNCTION(0x0, "gpio_in"), 79 SUNXI_FUNCTION(0x1, "gpio_out"), 80 SUNXI_FUNCTION(0x2, "nand0"), /* RE */ 81 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */ 82 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PC_EINT5 */ 83 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), 84 SUNXI_FUNCTION(0x0, "gpio_in"), 85 SUNXI_FUNCTION(0x1, "gpio_out"), 86 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ 87 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */ 88 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PC_EINT6 */ 89 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), 90 SUNXI_FUNCTION(0x0, "gpio_in"), 91 SUNXI_FUNCTION(0x1, "gpio_out"), 92 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */ 93 SUNXI_FUNCTION(0x4, "spi0"), /* CS1 */ 94 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PC_EINT7 */ 95 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), 96 SUNXI_FUNCTION(0x0, "gpio_in"), 97 SUNXI_FUNCTION(0x1, "gpio_out"), 98 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ 99 SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */ 100 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PC_EINT8 */ 101 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), 102 SUNXI_FUNCTION(0x0, "gpio_in"), 103 SUNXI_FUNCTION(0x1, "gpio_out"), 104 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ 105 SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */ 106 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PC_EINT9 */ 107 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), 108 SUNXI_FUNCTION(0x0, "gpio_in"), 109 SUNXI_FUNCTION(0x1, "gpio_out"), 110 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ 111 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */ 112 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PC_EINT10 */ 113 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), 114 SUNXI_FUNCTION(0x0, "gpio_in"), 115 SUNXI_FUNCTION(0x1, "gpio_out"), 116 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ 117 SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */ 118 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PC_EINT11 */ 119 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), 120 SUNXI_FUNCTION(0x0, "gpio_in"), 121 SUNXI_FUNCTION(0x1, "gpio_out"), 122 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ 123 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PC_EINT12 */ 124 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), 125 SUNXI_FUNCTION(0x0, "gpio_in"), 126 SUNXI_FUNCTION(0x1, "gpio_out"), 127 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ 128 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */ 129 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PC_EINT13 */ 130 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), 131 SUNXI_FUNCTION(0x0, "gpio_in"), 132 SUNXI_FUNCTION(0x1, "gpio_out"), 133 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ 134 SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */ 135 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), /* PC_EINT14 */ 136 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), 137 SUNXI_FUNCTION(0x0, "gpio_in"), 138 SUNXI_FUNCTION(0x1, "gpio_out"), 139 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ 140 SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */ 141 SUNXI_FUNCTION(0x4, "spi0"), /* WP */ 142 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PC_EINT15 */ 143 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), 144 SUNXI_FUNCTION(0x0, "gpio_in"), 145 SUNXI_FUNCTION(0x1, "gpio_out"), 146 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ 147 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */ 148 SUNXI_FUNCTION(0x4, "spi0"), /* HOLD */ 149 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PC_EINT16 */ 150 /* Hole */ 151 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), 152 SUNXI_FUNCTION(0x0, "gpio_in"), 153 SUNXI_FUNCTION(0x1, "gpio_out"), 154 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ 155 SUNXI_FUNCTION(0x3, "jtag"), /* MS */ 156 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)), /* PF_EINT0 */ 157 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), 158 SUNXI_FUNCTION(0x0, "gpio_in"), 159 SUNXI_FUNCTION(0x1, "gpio_out"), 160 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ 161 SUNXI_FUNCTION(0x3, "jtag"), /* DI */ 162 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)), /* PF_EINT1 */ 163 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), 164 SUNXI_FUNCTION(0x0, "gpio_in"), 165 SUNXI_FUNCTION(0x1, "gpio_out"), 166 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ 167 SUNXI_FUNCTION(0x3, "uart0"), /* TX */ 168 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)), /* PF_EINT2 */ 169 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), 170 SUNXI_FUNCTION(0x0, "gpio_in"), 171 SUNXI_FUNCTION(0x1, "gpio_out"), 172 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ 173 SUNXI_FUNCTION(0x3, "jtag"), /* DO */ 174 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)), /* PF_EINT3 */ 175 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), 176 SUNXI_FUNCTION(0x0, "gpio_in"), 177 SUNXI_FUNCTION(0x1, "gpio_out"), 178 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ 179 SUNXI_FUNCTION(0x3, "uart0"), /* RX */ 180 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)), /* PF_EINT4 */ 181 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), 182 SUNXI_FUNCTION(0x0, "gpio_in"), 183 SUNXI_FUNCTION(0x1, "gpio_out"), 184 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ 185 SUNXI_FUNCTION(0x3, "jtag"), /* CK */ 186 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)), /* PF_EINT5 */ 187 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), 188 SUNXI_FUNCTION(0x0, "gpio_in"), 189 SUNXI_FUNCTION(0x1, "gpio_out"), 190 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)), /* PF_EINT6 */ 191 /* Hole */ 192 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 193 SUNXI_FUNCTION(0x0, "gpio_in"), 194 SUNXI_FUNCTION(0x1, "gpio_out"), 195 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ 196 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0)), /* PG_EINT0 */ 197 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 198 SUNXI_FUNCTION(0x0, "gpio_in"), 199 SUNXI_FUNCTION(0x1, "gpio_out"), 200 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ 201 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1)), /* PG_EINT1 */ 202 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 203 SUNXI_FUNCTION(0x0, "gpio_in"), 204 SUNXI_FUNCTION(0x1, "gpio_out"), 205 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ 206 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2)), /* PG_EINT2 */ 207 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 208 SUNXI_FUNCTION(0x0, "gpio_in"), 209 SUNXI_FUNCTION(0x1, "gpio_out"), 210 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ 211 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3)), /* PG_EINT3 */ 212 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), 213 SUNXI_FUNCTION(0x0, "gpio_in"), 214 SUNXI_FUNCTION(0x1, "gpio_out"), 215 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ 216 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4)), /* PG_EINT4 */ 217 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), 218 SUNXI_FUNCTION(0x0, "gpio_in"), 219 SUNXI_FUNCTION(0x1, "gpio_out"), 220 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ 221 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5)), /* PG_EINT5 */ 222 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), 223 SUNXI_FUNCTION(0x0, "gpio_in"), 224 SUNXI_FUNCTION(0x1, "gpio_out"), 225 SUNXI_FUNCTION(0x2, "uart1"), /* TX */ 226 SUNXI_FUNCTION(0x4, "jtag"), /* MS */ 227 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6)), /* PG_EINT6 */ 228 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), 229 SUNXI_FUNCTION(0x0, "gpio_in"), 230 SUNXI_FUNCTION(0x1, "gpio_out"), 231 SUNXI_FUNCTION(0x2, "uart1"), /* RX */ 232 SUNXI_FUNCTION(0x4, "jtag"), /* CK */ 233 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7)), /* PG_EINT7 */ 234 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), 235 SUNXI_FUNCTION(0x0, "gpio_in"), 236 SUNXI_FUNCTION(0x1, "gpio_out"), 237 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ 238 SUNXI_FUNCTION(0x3, "clock"), /* PLL_LOCK_DEBUG */ 239 SUNXI_FUNCTION(0x4, "jtag"), /* DO */ 240 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8)), /* PG_EINT8 */ 241 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), 242 SUNXI_FUNCTION(0x0, "gpio_in"), 243 SUNXI_FUNCTION(0x1, "gpio_out"), 244 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ 245 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9)), /* PG_EINT9 */ 246 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), 247 SUNXI_FUNCTION(0x0, "gpio_in"), 248 SUNXI_FUNCTION(0x1, "gpio_out"), 249 SUNXI_FUNCTION(0x2, "i2s2"), /* MCLK */ 250 SUNXI_FUNCTION(0x3, "clock"), /* X32KFOUT */ 251 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10)), /* PG_EINT10 */ 252 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), 253 SUNXI_FUNCTION(0x0, "gpio_in"), 254 SUNXI_FUNCTION(0x1, "gpio_out"), 255 SUNXI_FUNCTION(0x2, "i2s2"), /* BCLK */ 256 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11)), /* PG_EINT11 */ 257 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), 258 SUNXI_FUNCTION(0x0, "gpio_in"), 259 SUNXI_FUNCTION(0x1, "gpio_out"), 260 SUNXI_FUNCTION(0x2, "i2s2"), /* SYNC */ 261 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12)), /* PG_EINT12 */ 262 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), 263 SUNXI_FUNCTION(0x0, "gpio_in"), 264 SUNXI_FUNCTION(0x1, "gpio_out"), 265 SUNXI_FUNCTION(0x2, "i2s2"), /* DOUT */ 266 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13)), /* PG_EINT13 */ 267 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), 268 SUNXI_FUNCTION(0x0, "gpio_in"), 269 SUNXI_FUNCTION(0x1, "gpio_out"), 270 SUNXI_FUNCTION(0x2, "i2s2"), /* DIN */ 271 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 14)), /* PG_EINT14 */ 272 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15), 273 SUNXI_FUNCTION(0x0, "gpio_in"), 274 SUNXI_FUNCTION(0x1, "gpio_out"), 275 SUNXI_FUNCTION(0x2, "uart2"), /* TX */ 276 SUNXI_FUNCTION(0x5, "i2c4"), /* SCK */ 277 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 15)), /* PG_EINT15 */ 278 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16), 279 SUNXI_FUNCTION(0x0, "gpio_in"), 280 SUNXI_FUNCTION(0x1, "gpio_out"), 281 SUNXI_FUNCTION(0x2, "uart2"), /* RX */ 282 SUNXI_FUNCTION(0x5, "i2c4"), /* SDA */ 283 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 16)), /* PG_EINT16 */ 284 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17), 285 SUNXI_FUNCTION(0x0, "gpio_in"), 286 SUNXI_FUNCTION(0x1, "gpio_out"), 287 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ 288 SUNXI_FUNCTION(0x5, "i2c3"), /* SCK */ 289 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 17)), /* PG_EINT17 */ 290 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18), 291 SUNXI_FUNCTION(0x0, "gpio_in"), 292 SUNXI_FUNCTION(0x1, "gpio_out"), 293 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ 294 SUNXI_FUNCTION(0x5, "i2c3"), /* SDA */ 295 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 18)), /* PG_EINT18 */ 296 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 19), 297 SUNXI_FUNCTION(0x0, "gpio_in"), 298 SUNXI_FUNCTION(0x1, "gpio_out"), 299 SUNXI_FUNCTION(0x4, "pwm1"), 300 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 19)), /* PG_EINT19 */ 301 /* Hole */ 302 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), 303 SUNXI_FUNCTION(0x0, "gpio_in"), 304 SUNXI_FUNCTION(0x1, "gpio_out"), 305 SUNXI_FUNCTION(0x2, "uart0"), /* TX */ 306 SUNXI_FUNCTION(0x4, "pwm3"), 307 SUNXI_FUNCTION(0x5, "i2c1"), /* SCK */ 308 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)), /* PH_EINT0 */ 309 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), 310 SUNXI_FUNCTION(0x0, "gpio_in"), 311 SUNXI_FUNCTION(0x1, "gpio_out"), 312 SUNXI_FUNCTION(0x2, "uart0"), /* RX */ 313 SUNXI_FUNCTION(0x4, "pwm4"), 314 SUNXI_FUNCTION(0x5, "i2c1"), /* SDA */ 315 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)), /* PH_EINT1 */ 316 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), 317 SUNXI_FUNCTION(0x0, "gpio_in"), 318 SUNXI_FUNCTION(0x1, "gpio_out"), 319 SUNXI_FUNCTION(0x2, "uart5"), /* TX */ 320 SUNXI_FUNCTION(0x3, "spdif"), /* MCLK */ 321 SUNXI_FUNCTION(0x4, "pwm2"), 322 SUNXI_FUNCTION(0x5, "i2c2"), /* SCK */ 323 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)), /* PH_EINT2 */ 324 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), 325 SUNXI_FUNCTION(0x0, "gpio_in"), 326 SUNXI_FUNCTION(0x1, "gpio_out"), 327 SUNXI_FUNCTION(0x2, "uart5"), /* RX */ 328 SUNXI_FUNCTION(0x4, "pwm1"), 329 SUNXI_FUNCTION(0x5, "i2c2"), /* SDA */ 330 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)), /* PH_EINT3 */ 331 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), 332 SUNXI_FUNCTION(0x0, "gpio_in"), 333 SUNXI_FUNCTION(0x1, "gpio_out"), 334 SUNXI_FUNCTION(0x3, "spdif"), /* OUT */ 335 SUNXI_FUNCTION(0x5, "i2c3"), /* SCK */ 336 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)), /* PH_EINT4 */ 337 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), 338 SUNXI_FUNCTION(0x0, "gpio_in"), 339 SUNXI_FUNCTION(0x1, "gpio_out"), 340 SUNXI_FUNCTION(0x2, "uart2"), /* TX */ 341 SUNXI_FUNCTION(0x3, "i2s3"), /* MCLK */ 342 SUNXI_FUNCTION(0x4, "spi1"), /* CS0 */ 343 SUNXI_FUNCTION(0x5, "i2c3"), /* SDA */ 344 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)), /* PH_EINT5 */ 345 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), 346 SUNXI_FUNCTION(0x0, "gpio_in"), 347 SUNXI_FUNCTION(0x1, "gpio_out"), 348 SUNXI_FUNCTION(0x2, "uart2"), /* RX */ 349 SUNXI_FUNCTION(0x3, "i2s3"), /* BCLK */ 350 SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ 351 SUNXI_FUNCTION(0x5, "i2c4"), /* SCK */ 352 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)), /* PH_EINT6 */ 353 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), 354 SUNXI_FUNCTION(0x0, "gpio_in"), 355 SUNXI_FUNCTION(0x1, "gpio_out"), 356 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ 357 SUNXI_FUNCTION(0x3, "i2s3"), /* SYNC */ 358 SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */ 359 SUNXI_FUNCTION(0x5, "i2c4"), /* SDA */ 360 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)), /* PH_EINT7 */ 361 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), 362 SUNXI_FUNCTION(0x0, "gpio_in"), 363 SUNXI_FUNCTION(0x1, "gpio_out"), 364 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ 365 SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DO0 */ 366 SUNXI_FUNCTION(0x4, "spi1"), /* MISO */ 367 SUNXI_FUNCTION(0x5, "i2s3_din1"), /* DI1 */ 368 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 8)), /* PH_EINT8 */ 369 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), 370 SUNXI_FUNCTION(0x0, "gpio_in"), 371 SUNXI_FUNCTION(0x1, "gpio_out"), 372 SUNXI_FUNCTION(0x3, "i2s3_din0"), /* DI0 */ 373 SUNXI_FUNCTION(0x4, "spi1"), /* CS1 */ 374 SUNXI_FUNCTION(0x5, "i2s3_dout1"), /* DO1 */ 375 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)), /* PH_EINT9 */ 376 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), 377 SUNXI_FUNCTION(0x0, "gpio_in"), 378 SUNXI_FUNCTION(0x1, "gpio_out"), 379 SUNXI_FUNCTION(0x3, "ir_rx"), 380 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)), /* PH_EINT10 */ 381 /* Hole */ 382 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0), 383 SUNXI_FUNCTION(0x0, "gpio_in"), 384 SUNXI_FUNCTION(0x1, "gpio_out"), 385 SUNXI_FUNCTION(0x2, "emac0"), /* ERXD3 */ 386 SUNXI_FUNCTION(0x3, "dmic"), /* CLK */ 387 SUNXI_FUNCTION(0x4, "i2s0"), /* MCLK */ 388 SUNXI_FUNCTION(0x5, "hdmi"), /* HSCL */ 389 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 0)), /* PI_EINT0 */ 390 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1), 391 SUNXI_FUNCTION(0x0, "gpio_in"), 392 SUNXI_FUNCTION(0x1, "gpio_out"), 393 SUNXI_FUNCTION(0x2, "emac0"), /* ERXD2 */ 394 SUNXI_FUNCTION(0x3, "dmic"), /* DATA0 */ 395 SUNXI_FUNCTION(0x4, "i2s0"), /* BCLK */ 396 SUNXI_FUNCTION(0x5, "hdmi"), /* HSDA */ 397 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 1)), /* PI_EINT1 */ 398 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2), 399 SUNXI_FUNCTION(0x0, "gpio_in"), 400 SUNXI_FUNCTION(0x1, "gpio_out"), 401 SUNXI_FUNCTION(0x2, "emac0"), /* ERXD1 */ 402 SUNXI_FUNCTION(0x3, "dmic"), /* DATA1 */ 403 SUNXI_FUNCTION(0x4, "i2s0"), /* SYNC */ 404 SUNXI_FUNCTION(0x5, "hdmi"), /* HCEC */ 405 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 2)), /* PI_EINT2 */ 406 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3), 407 SUNXI_FUNCTION(0x0, "gpio_in"), 408 SUNXI_FUNCTION(0x1, "gpio_out"), 409 SUNXI_FUNCTION(0x2, "emac0"), /* ERXD0 */ 410 SUNXI_FUNCTION(0x3, "dmic"), /* DATA2 */ 411 SUNXI_FUNCTION(0x4, "i2s0_dout0"), /* DO0 */ 412 SUNXI_FUNCTION(0x5, "i2s0_din1"), /* DI1 */ 413 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 3)), /* PI_EINT3 */ 414 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4), 415 SUNXI_FUNCTION(0x0, "gpio_in"), 416 SUNXI_FUNCTION(0x1, "gpio_out"), 417 SUNXI_FUNCTION(0x2, "emac0"), /* ERXCK */ 418 SUNXI_FUNCTION(0x3, "dmic"), /* DATA3 */ 419 SUNXI_FUNCTION(0x4, "i2s0_din0"), /* DI0 */ 420 SUNXI_FUNCTION(0x5, "i2s0_dout1"), /* DO1 */ 421 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 4)), /* PI_EINT4 */ 422 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5), 423 SUNXI_FUNCTION(0x0, "gpio_in"), 424 SUNXI_FUNCTION(0x1, "gpio_out"), 425 SUNXI_FUNCTION(0x2, "emac0"), /* ERXCTL */ 426 SUNXI_FUNCTION(0x3, "uart2"), /* TX */ 427 SUNXI_FUNCTION(0x4, "ts0"), /* CLK */ 428 SUNXI_FUNCTION(0x5, "i2c0"), /* SCK */ 429 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 5)), /* PI_EINT5 */ 430 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6), 431 SUNXI_FUNCTION(0x0, "gpio_in"), 432 SUNXI_FUNCTION(0x1, "gpio_out"), 433 SUNXI_FUNCTION(0x2, "emac0"), /* ENULL */ 434 SUNXI_FUNCTION(0x3, "uart2"), /* RX */ 435 SUNXI_FUNCTION(0x4, "ts0"), /* ERR */ 436 SUNXI_FUNCTION(0x5, "i2c0"), /* SDA */ 437 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 6)), /* PI_EINT6 */ 438 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7), 439 SUNXI_FUNCTION(0x0, "gpio_in"), 440 SUNXI_FUNCTION(0x1, "gpio_out"), 441 SUNXI_FUNCTION(0x2, "emac0"), /* ETXD3 */ 442 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ 443 SUNXI_FUNCTION(0x4, "ts0"), /* SYNC */ 444 SUNXI_FUNCTION(0x5, "i2c1"), /* SCK */ 445 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 7)), /* PI_EINT7 */ 446 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8), 447 SUNXI_FUNCTION(0x0, "gpio_in"), 448 SUNXI_FUNCTION(0x1, "gpio_out"), 449 SUNXI_FUNCTION(0x2, "emac0"), /* ETXD2 */ 450 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ 451 SUNXI_FUNCTION(0x4, "ts0"), /* DVLD */ 452 SUNXI_FUNCTION(0x5, "i2c1"), /* SDA */ 453 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 8)), /* PI_EINT8 */ 454 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9), 455 SUNXI_FUNCTION(0x0, "gpio_in"), 456 SUNXI_FUNCTION(0x1, "gpio_out"), 457 SUNXI_FUNCTION(0x2, "emac0"), /* ETXD1 */ 458 SUNXI_FUNCTION(0x3, "uart3"), /* TX */ 459 SUNXI_FUNCTION(0x4, "ts0"), /* D0 */ 460 SUNXI_FUNCTION(0x5, "i2c2"), /* SCK */ 461 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 9)), /* PI_EINT9 */ 462 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10), 463 SUNXI_FUNCTION(0x0, "gpio_in"), 464 SUNXI_FUNCTION(0x1, "gpio_out"), 465 SUNXI_FUNCTION(0x2, "emac0"), /* ETXD0 */ 466 SUNXI_FUNCTION(0x3, "uart3"), /* RX */ 467 SUNXI_FUNCTION(0x4, "ts0"), /* D1 */ 468 SUNXI_FUNCTION(0x5, "i2c2"), /* SDA */ 469 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 10)), /* PI_EINT10 */ 470 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11), 471 SUNXI_FUNCTION(0x0, "gpio_in"), 472 SUNXI_FUNCTION(0x1, "gpio_out"), 473 SUNXI_FUNCTION(0x2, "emac0"), /* ETXCK */ 474 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ 475 SUNXI_FUNCTION(0x4, "ts0"), /* D2 */ 476 SUNXI_FUNCTION(0x5, "pwm1"), 477 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 11)), /* PI_EINT11 */ 478 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12), 479 SUNXI_FUNCTION(0x0, "gpio_in"), 480 SUNXI_FUNCTION(0x1, "gpio_out"), 481 SUNXI_FUNCTION(0x2, "emac0"), /* ETXCTL */ 482 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ 483 SUNXI_FUNCTION(0x4, "ts0"), /* D3 */ 484 SUNXI_FUNCTION(0x5, "pwm2"), 485 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 12)), /* PI_EINT12 */ 486 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13), 487 SUNXI_FUNCTION(0x0, "gpio_in"), 488 SUNXI_FUNCTION(0x1, "gpio_out"), 489 SUNXI_FUNCTION(0x2, "emac0"), /* ECLKIN */ 490 SUNXI_FUNCTION(0x3, "uart4"), /* TX */ 491 SUNXI_FUNCTION(0x4, "ts0"), /* D4 */ 492 SUNXI_FUNCTION(0x5, "pwm3"), 493 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 13)), /* PI_EINT13 */ 494 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14), 495 SUNXI_FUNCTION(0x0, "gpio_in"), 496 SUNXI_FUNCTION(0x1, "gpio_out"), 497 SUNXI_FUNCTION(0x2, "emac0"), /* MDC */ 498 SUNXI_FUNCTION(0x3, "uart4"), /* RX */ 499 SUNXI_FUNCTION(0x4, "ts0"), /* D5 */ 500 SUNXI_FUNCTION(0x5, "pwm4"), 501 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 14)), /* PI_EINT14 */ 502 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15), 503 SUNXI_FUNCTION(0x0, "gpio_in"), 504 SUNXI_FUNCTION(0x1, "gpio_out"), 505 SUNXI_FUNCTION(0x2, "emac0"), /* MDIO */ 506 SUNXI_FUNCTION(0x3, "uart4"), /* RTS */ 507 SUNXI_FUNCTION(0x4, "ts0"), /* D6 */ 508 SUNXI_FUNCTION(0x5, "clock"), /* CLK_FANOUT0 */ 509 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 15)), /* PI_EINT15 */ 510 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16), 511 SUNXI_FUNCTION(0x0, "gpio_in"), 512 SUNXI_FUNCTION(0x1, "gpio_out"), 513 SUNXI_FUNCTION(0x2, "emac0"), /* EPHY_CLK */ 514 SUNXI_FUNCTION(0x3, "uart4"), /* CTS */ 515 SUNXI_FUNCTION(0x4, "ts0"), /* D7 */ 516 SUNXI_FUNCTION(0x5, "clock"), /* CLK_FANOUT1 */ 517 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 16)), /* PI_EINT16 */ 518}; 519static const unsigned int h616_irq_bank_map[] = { 0, 2, 3, 4, 5, 6, 7, 8 }; 520 521static const struct sunxi_pinctrl_desc h616_pinctrl_data = { 522 .pins = h616_pins, 523 .npins = ARRAY_SIZE(h616_pins), 524 .irq_banks = ARRAY_SIZE(h616_irq_bank_map), 525 .irq_bank_map = h616_irq_bank_map, 526 .irq_read_needs_mux = true, 527 .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL, 528}; 529 530static int h616_pinctrl_probe(struct platform_device *pdev) 531{ 532 return sunxi_pinctrl_init(pdev, &h616_pinctrl_data); 533} 534 535static const struct of_device_id h616_pinctrl_match[] = { 536 { .compatible = "allwinner,sun50i-h616-pinctrl", }, 537 {} 538}; 539 540static struct platform_driver h616_pinctrl_driver = { 541 .probe = h616_pinctrl_probe, 542 .driver = { 543 .name = "sun50i-h616-pinctrl", 544 .of_match_table = h616_pinctrl_match, 545 }, 546}; 547builtin_platform_driver(h616_pinctrl_driver); 548