162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Pinctrl / GPIO driver for StarFive JH7110 SoC 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 2022 StarFive Technology Co., Ltd. 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci#ifndef __PINCTRL_STARFIVE_JH7110_H__ 962306a36Sopenharmony_ci#define __PINCTRL_STARFIVE_JH7110_H__ 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci#include <linux/pinctrl/pinconf-generic.h> 1262306a36Sopenharmony_ci#include <linux/pinctrl/pinmux.h> 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_cistruct jh7110_pinctrl { 1562306a36Sopenharmony_ci struct device *dev; 1662306a36Sopenharmony_ci struct gpio_chip gc; 1762306a36Sopenharmony_ci struct pinctrl_gpio_range gpios; 1862306a36Sopenharmony_ci raw_spinlock_t lock; 1962306a36Sopenharmony_ci void __iomem *base; 2062306a36Sopenharmony_ci struct pinctrl_dev *pctl; 2162306a36Sopenharmony_ci /* register read/write mutex */ 2262306a36Sopenharmony_ci struct mutex mutex; 2362306a36Sopenharmony_ci const struct jh7110_pinctrl_soc_info *info; 2462306a36Sopenharmony_ci u32 *saved_regs; 2562306a36Sopenharmony_ci}; 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_cistruct jh7110_gpio_irq_reg { 2862306a36Sopenharmony_ci unsigned int is_reg_base; 2962306a36Sopenharmony_ci unsigned int ic_reg_base; 3062306a36Sopenharmony_ci unsigned int ibe_reg_base; 3162306a36Sopenharmony_ci unsigned int iev_reg_base; 3262306a36Sopenharmony_ci unsigned int ie_reg_base; 3362306a36Sopenharmony_ci unsigned int ris_reg_base; 3462306a36Sopenharmony_ci unsigned int mis_reg_base; 3562306a36Sopenharmony_ci}; 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_cistruct jh7110_pinctrl_soc_info { 3862306a36Sopenharmony_ci const struct pinctrl_pin_desc *pins; 3962306a36Sopenharmony_ci unsigned int npins; 4062306a36Sopenharmony_ci unsigned int ngpios; 4162306a36Sopenharmony_ci unsigned int gc_base; 4262306a36Sopenharmony_ci 4362306a36Sopenharmony_ci /* gpio dout/doen/din/gpioinput register */ 4462306a36Sopenharmony_ci unsigned int dout_reg_base; 4562306a36Sopenharmony_ci unsigned int dout_mask; 4662306a36Sopenharmony_ci unsigned int doen_reg_base; 4762306a36Sopenharmony_ci unsigned int doen_mask; 4862306a36Sopenharmony_ci unsigned int gpi_reg_base; 4962306a36Sopenharmony_ci unsigned int gpi_mask; 5062306a36Sopenharmony_ci unsigned int gpioin_reg_base; 5162306a36Sopenharmony_ci 5262306a36Sopenharmony_ci const struct jh7110_gpio_irq_reg *irq_reg; 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ci unsigned int nsaved_regs; 5562306a36Sopenharmony_ci 5662306a36Sopenharmony_ci /* generic pinmux */ 5762306a36Sopenharmony_ci int (*jh7110_set_one_pin_mux)(struct jh7110_pinctrl *sfp, 5862306a36Sopenharmony_ci unsigned int pin, 5962306a36Sopenharmony_ci unsigned int din, u32 dout, 6062306a36Sopenharmony_ci u32 doen, u32 func); 6162306a36Sopenharmony_ci /* gpio chip */ 6262306a36Sopenharmony_ci int (*jh7110_get_padcfg_base)(struct jh7110_pinctrl *sfp, 6362306a36Sopenharmony_ci unsigned int pin); 6462306a36Sopenharmony_ci void (*jh7110_gpio_irq_handler)(struct irq_desc *desc); 6562306a36Sopenharmony_ci int (*jh7110_gpio_init_hw)(struct gpio_chip *gc); 6662306a36Sopenharmony_ci}; 6762306a36Sopenharmony_ci 6862306a36Sopenharmony_civoid jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin, 6962306a36Sopenharmony_ci unsigned int din, u32 dout, u32 doen); 7062306a36Sopenharmony_ciint jh7110_pinctrl_probe(struct platform_device *pdev); 7162306a36Sopenharmony_cistruct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc); 7262306a36Sopenharmony_ciextern const struct dev_pm_ops jh7110_pinctrl_pm_ops; 7362306a36Sopenharmony_ci 7462306a36Sopenharmony_ci#endif /* __PINCTRL_STARFIVE_JH7110_H__ */ 75