1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Linaro Limited 5 */ 6 7#include <linux/module.h> 8#include <linux/of.h> 9#include <linux/platform_device.h> 10 11#include "pinctrl-msm.h" 12 13#define REG_SIZE 0x1000 14 15#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 16 { \ 17 .grp = PINCTRL_PINGROUP("gpio" #id, \ 18 gpio##id##_pins, \ 19 ARRAY_SIZE(gpio##id##_pins)), \ 20 .funcs = (int[]){ \ 21 msm_mux_gpio, /* gpio mode */ \ 22 msm_mux_##f1, \ 23 msm_mux_##f2, \ 24 msm_mux_##f3, \ 25 msm_mux_##f4, \ 26 msm_mux_##f5, \ 27 msm_mux_##f6, \ 28 msm_mux_##f7, \ 29 msm_mux_##f8, \ 30 msm_mux_##f9 \ 31 }, \ 32 .nfuncs = 10, \ 33 .ctl_reg = REG_SIZE * id, \ 34 .io_reg = 0x4 + REG_SIZE * id, \ 35 .intr_cfg_reg = 0x8 + REG_SIZE * id, \ 36 .intr_status_reg = 0xc + REG_SIZE * id, \ 37 .intr_target_reg = 0x8 + REG_SIZE * id, \ 38 .mux_bit = 2, \ 39 .pull_bit = 0, \ 40 .drv_bit = 6, \ 41 .egpio_enable = 12, \ 42 .egpio_present = 11, \ 43 .oe_bit = 9, \ 44 .in_bit = 0, \ 45 .out_bit = 1, \ 46 .intr_enable_bit = 0, \ 47 .intr_status_bit = 0, \ 48 .intr_target_bit = 5, \ 49 .intr_target_kpss_val = 3, \ 50 .intr_raw_status_bit = 4, \ 51 .intr_polarity_bit = 1, \ 52 .intr_detection_bit = 2, \ 53 .intr_detection_width = 2, \ 54 } 55 56#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 57 { \ 58 .grp = PINCTRL_PINGROUP(#pg_name, \ 59 pg_name##_pins, \ 60 ARRAY_SIZE(pg_name##_pins)), \ 61 .ctl_reg = ctl, \ 62 .io_reg = 0, \ 63 .intr_cfg_reg = 0, \ 64 .intr_status_reg = 0, \ 65 .intr_target_reg = 0, \ 66 .mux_bit = -1, \ 67 .pull_bit = pull, \ 68 .drv_bit = drv, \ 69 .oe_bit = -1, \ 70 .in_bit = -1, \ 71 .out_bit = -1, \ 72 .intr_enable_bit = -1, \ 73 .intr_status_bit = -1, \ 74 .intr_target_bit = -1, \ 75 .intr_raw_status_bit = -1, \ 76 .intr_polarity_bit = -1, \ 77 .intr_detection_bit = -1, \ 78 .intr_detection_width = -1, \ 79 } 80 81#define UFS_RESET(pg_name, offset) \ 82 { \ 83 .grp = PINCTRL_PINGROUP(#pg_name, \ 84 pg_name##_pins, \ 85 ARRAY_SIZE(pg_name##_pins)), \ 86 .ctl_reg = offset, \ 87 .io_reg = offset + 0x4, \ 88 .intr_cfg_reg = 0, \ 89 .intr_status_reg = 0, \ 90 .intr_target_reg = 0, \ 91 .mux_bit = -1, \ 92 .pull_bit = 3, \ 93 .drv_bit = 0, \ 94 .oe_bit = -1, \ 95 .in_bit = -1, \ 96 .out_bit = 0, \ 97 .intr_enable_bit = -1, \ 98 .intr_status_bit = -1, \ 99 .intr_target_bit = -1, \ 100 .intr_raw_status_bit = -1, \ 101 .intr_polarity_bit = -1, \ 102 .intr_detection_bit = -1, \ 103 .intr_detection_width = -1, \ 104 } 105 106static const struct pinctrl_pin_desc sm8450_pins[] = { 107 PINCTRL_PIN(0, "GPIO_0"), 108 PINCTRL_PIN(1, "GPIO_1"), 109 PINCTRL_PIN(2, "GPIO_2"), 110 PINCTRL_PIN(3, "GPIO_3"), 111 PINCTRL_PIN(4, "GPIO_4"), 112 PINCTRL_PIN(5, "GPIO_5"), 113 PINCTRL_PIN(6, "GPIO_6"), 114 PINCTRL_PIN(7, "GPIO_7"), 115 PINCTRL_PIN(8, "GPIO_8"), 116 PINCTRL_PIN(9, "GPIO_9"), 117 PINCTRL_PIN(10, "GPIO_10"), 118 PINCTRL_PIN(11, "GPIO_11"), 119 PINCTRL_PIN(12, "GPIO_12"), 120 PINCTRL_PIN(13, "GPIO_13"), 121 PINCTRL_PIN(14, "GPIO_14"), 122 PINCTRL_PIN(15, "GPIO_15"), 123 PINCTRL_PIN(16, "GPIO_16"), 124 PINCTRL_PIN(17, "GPIO_17"), 125 PINCTRL_PIN(18, "GPIO_18"), 126 PINCTRL_PIN(19, "GPIO_19"), 127 PINCTRL_PIN(20, "GPIO_20"), 128 PINCTRL_PIN(21, "GPIO_21"), 129 PINCTRL_PIN(22, "GPIO_22"), 130 PINCTRL_PIN(23, "GPIO_23"), 131 PINCTRL_PIN(24, "GPIO_24"), 132 PINCTRL_PIN(25, "GPIO_25"), 133 PINCTRL_PIN(26, "GPIO_26"), 134 PINCTRL_PIN(27, "GPIO_27"), 135 PINCTRL_PIN(28, "GPIO_28"), 136 PINCTRL_PIN(29, "GPIO_29"), 137 PINCTRL_PIN(30, "GPIO_30"), 138 PINCTRL_PIN(31, "GPIO_31"), 139 PINCTRL_PIN(32, "GPIO_32"), 140 PINCTRL_PIN(33, "GPIO_33"), 141 PINCTRL_PIN(34, "GPIO_34"), 142 PINCTRL_PIN(35, "GPIO_35"), 143 PINCTRL_PIN(36, "GPIO_36"), 144 PINCTRL_PIN(37, "GPIO_37"), 145 PINCTRL_PIN(38, "GPIO_38"), 146 PINCTRL_PIN(39, "GPIO_39"), 147 PINCTRL_PIN(40, "GPIO_40"), 148 PINCTRL_PIN(41, "GPIO_41"), 149 PINCTRL_PIN(42, "GPIO_42"), 150 PINCTRL_PIN(43, "GPIO_43"), 151 PINCTRL_PIN(44, "GPIO_44"), 152 PINCTRL_PIN(45, "GPIO_45"), 153 PINCTRL_PIN(46, "GPIO_46"), 154 PINCTRL_PIN(47, "GPIO_47"), 155 PINCTRL_PIN(48, "GPIO_48"), 156 PINCTRL_PIN(49, "GPIO_49"), 157 PINCTRL_PIN(50, "GPIO_50"), 158 PINCTRL_PIN(51, "GPIO_51"), 159 PINCTRL_PIN(52, "GPIO_52"), 160 PINCTRL_PIN(53, "GPIO_53"), 161 PINCTRL_PIN(54, "GPIO_54"), 162 PINCTRL_PIN(55, "GPIO_55"), 163 PINCTRL_PIN(56, "GPIO_56"), 164 PINCTRL_PIN(57, "GPIO_57"), 165 PINCTRL_PIN(58, "GPIO_58"), 166 PINCTRL_PIN(59, "GPIO_59"), 167 PINCTRL_PIN(60, "GPIO_60"), 168 PINCTRL_PIN(61, "GPIO_61"), 169 PINCTRL_PIN(62, "GPIO_62"), 170 PINCTRL_PIN(63, "GPIO_63"), 171 PINCTRL_PIN(64, "GPIO_64"), 172 PINCTRL_PIN(65, "GPIO_65"), 173 PINCTRL_PIN(66, "GPIO_66"), 174 PINCTRL_PIN(67, "GPIO_67"), 175 PINCTRL_PIN(68, "GPIO_68"), 176 PINCTRL_PIN(69, "GPIO_69"), 177 PINCTRL_PIN(70, "GPIO_70"), 178 PINCTRL_PIN(71, "GPIO_71"), 179 PINCTRL_PIN(72, "GPIO_72"), 180 PINCTRL_PIN(73, "GPIO_73"), 181 PINCTRL_PIN(74, "GPIO_74"), 182 PINCTRL_PIN(75, "GPIO_75"), 183 PINCTRL_PIN(76, "GPIO_76"), 184 PINCTRL_PIN(77, "GPIO_77"), 185 PINCTRL_PIN(78, "GPIO_78"), 186 PINCTRL_PIN(79, "GPIO_79"), 187 PINCTRL_PIN(80, "GPIO_80"), 188 PINCTRL_PIN(81, "GPIO_81"), 189 PINCTRL_PIN(82, "GPIO_82"), 190 PINCTRL_PIN(83, "GPIO_83"), 191 PINCTRL_PIN(84, "GPIO_84"), 192 PINCTRL_PIN(85, "GPIO_85"), 193 PINCTRL_PIN(86, "GPIO_86"), 194 PINCTRL_PIN(87, "GPIO_87"), 195 PINCTRL_PIN(88, "GPIO_88"), 196 PINCTRL_PIN(89, "GPIO_89"), 197 PINCTRL_PIN(90, "GPIO_90"), 198 PINCTRL_PIN(91, "GPIO_91"), 199 PINCTRL_PIN(92, "GPIO_92"), 200 PINCTRL_PIN(93, "GPIO_93"), 201 PINCTRL_PIN(94, "GPIO_94"), 202 PINCTRL_PIN(95, "GPIO_95"), 203 PINCTRL_PIN(96, "GPIO_96"), 204 PINCTRL_PIN(97, "GPIO_97"), 205 PINCTRL_PIN(98, "GPIO_98"), 206 PINCTRL_PIN(99, "GPIO_99"), 207 PINCTRL_PIN(100, "GPIO_100"), 208 PINCTRL_PIN(101, "GPIO_101"), 209 PINCTRL_PIN(102, "GPIO_102"), 210 PINCTRL_PIN(103, "GPIO_103"), 211 PINCTRL_PIN(104, "GPIO_104"), 212 PINCTRL_PIN(105, "GPIO_105"), 213 PINCTRL_PIN(106, "GPIO_106"), 214 PINCTRL_PIN(107, "GPIO_107"), 215 PINCTRL_PIN(108, "GPIO_108"), 216 PINCTRL_PIN(109, "GPIO_109"), 217 PINCTRL_PIN(110, "GPIO_110"), 218 PINCTRL_PIN(111, "GPIO_111"), 219 PINCTRL_PIN(112, "GPIO_112"), 220 PINCTRL_PIN(113, "GPIO_113"), 221 PINCTRL_PIN(114, "GPIO_114"), 222 PINCTRL_PIN(115, "GPIO_115"), 223 PINCTRL_PIN(116, "GPIO_116"), 224 PINCTRL_PIN(117, "GPIO_117"), 225 PINCTRL_PIN(118, "GPIO_118"), 226 PINCTRL_PIN(119, "GPIO_119"), 227 PINCTRL_PIN(120, "GPIO_120"), 228 PINCTRL_PIN(121, "GPIO_121"), 229 PINCTRL_PIN(122, "GPIO_122"), 230 PINCTRL_PIN(123, "GPIO_123"), 231 PINCTRL_PIN(124, "GPIO_124"), 232 PINCTRL_PIN(125, "GPIO_125"), 233 PINCTRL_PIN(126, "GPIO_126"), 234 PINCTRL_PIN(127, "GPIO_127"), 235 PINCTRL_PIN(128, "GPIO_128"), 236 PINCTRL_PIN(129, "GPIO_129"), 237 PINCTRL_PIN(130, "GPIO_130"), 238 PINCTRL_PIN(131, "GPIO_131"), 239 PINCTRL_PIN(132, "GPIO_132"), 240 PINCTRL_PIN(133, "GPIO_133"), 241 PINCTRL_PIN(134, "GPIO_134"), 242 PINCTRL_PIN(135, "GPIO_135"), 243 PINCTRL_PIN(136, "GPIO_136"), 244 PINCTRL_PIN(137, "GPIO_137"), 245 PINCTRL_PIN(138, "GPIO_138"), 246 PINCTRL_PIN(139, "GPIO_139"), 247 PINCTRL_PIN(140, "GPIO_140"), 248 PINCTRL_PIN(141, "GPIO_141"), 249 PINCTRL_PIN(142, "GPIO_142"), 250 PINCTRL_PIN(143, "GPIO_143"), 251 PINCTRL_PIN(144, "GPIO_144"), 252 PINCTRL_PIN(145, "GPIO_145"), 253 PINCTRL_PIN(146, "GPIO_146"), 254 PINCTRL_PIN(147, "GPIO_147"), 255 PINCTRL_PIN(148, "GPIO_148"), 256 PINCTRL_PIN(149, "GPIO_149"), 257 PINCTRL_PIN(150, "GPIO_150"), 258 PINCTRL_PIN(151, "GPIO_151"), 259 PINCTRL_PIN(152, "GPIO_152"), 260 PINCTRL_PIN(153, "GPIO_153"), 261 PINCTRL_PIN(154, "GPIO_154"), 262 PINCTRL_PIN(155, "GPIO_155"), 263 PINCTRL_PIN(156, "GPIO_156"), 264 PINCTRL_PIN(157, "GPIO_157"), 265 PINCTRL_PIN(158, "GPIO_158"), 266 PINCTRL_PIN(159, "GPIO_159"), 267 PINCTRL_PIN(160, "GPIO_160"), 268 PINCTRL_PIN(161, "GPIO_161"), 269 PINCTRL_PIN(162, "GPIO_162"), 270 PINCTRL_PIN(163, "GPIO_163"), 271 PINCTRL_PIN(164, "GPIO_164"), 272 PINCTRL_PIN(165, "GPIO_165"), 273 PINCTRL_PIN(166, "GPIO_166"), 274 PINCTRL_PIN(167, "GPIO_167"), 275 PINCTRL_PIN(168, "GPIO_168"), 276 PINCTRL_PIN(169, "GPIO_169"), 277 PINCTRL_PIN(170, "GPIO_170"), 278 PINCTRL_PIN(171, "GPIO_171"), 279 PINCTRL_PIN(172, "GPIO_172"), 280 PINCTRL_PIN(173, "GPIO_173"), 281 PINCTRL_PIN(174, "GPIO_174"), 282 PINCTRL_PIN(175, "GPIO_175"), 283 PINCTRL_PIN(176, "GPIO_176"), 284 PINCTRL_PIN(177, "GPIO_177"), 285 PINCTRL_PIN(178, "GPIO_178"), 286 PINCTRL_PIN(179, "GPIO_179"), 287 PINCTRL_PIN(180, "GPIO_180"), 288 PINCTRL_PIN(181, "GPIO_181"), 289 PINCTRL_PIN(182, "GPIO_182"), 290 PINCTRL_PIN(183, "GPIO_183"), 291 PINCTRL_PIN(184, "GPIO_184"), 292 PINCTRL_PIN(185, "GPIO_185"), 293 PINCTRL_PIN(186, "GPIO_186"), 294 PINCTRL_PIN(187, "GPIO_187"), 295 PINCTRL_PIN(188, "GPIO_188"), 296 PINCTRL_PIN(189, "GPIO_189"), 297 PINCTRL_PIN(190, "GPIO_190"), 298 PINCTRL_PIN(191, "GPIO_191"), 299 PINCTRL_PIN(192, "GPIO_192"), 300 PINCTRL_PIN(193, "GPIO_193"), 301 PINCTRL_PIN(194, "GPIO_194"), 302 PINCTRL_PIN(195, "GPIO_195"), 303 PINCTRL_PIN(196, "GPIO_196"), 304 PINCTRL_PIN(197, "GPIO_197"), 305 PINCTRL_PIN(198, "GPIO_198"), 306 PINCTRL_PIN(199, "GPIO_199"), 307 PINCTRL_PIN(200, "GPIO_200"), 308 PINCTRL_PIN(201, "GPIO_201"), 309 PINCTRL_PIN(202, "GPIO_202"), 310 PINCTRL_PIN(203, "GPIO_203"), 311 PINCTRL_PIN(204, "GPIO_204"), 312 PINCTRL_PIN(205, "GPIO_205"), 313 PINCTRL_PIN(206, "GPIO_206"), 314 PINCTRL_PIN(207, "GPIO_207"), 315 PINCTRL_PIN(208, "GPIO_208"), 316 PINCTRL_PIN(209, "GPIO_209"), 317 PINCTRL_PIN(210, "UFS_RESET"), 318 PINCTRL_PIN(211, "SDC2_CLK"), 319 PINCTRL_PIN(212, "SDC2_CMD"), 320 PINCTRL_PIN(213, "SDC2_DATA"), 321}; 322 323#define DECLARE_MSM_GPIO_PINS(pin) \ 324 static const unsigned int gpio##pin##_pins[] = { pin } 325DECLARE_MSM_GPIO_PINS(0); 326DECLARE_MSM_GPIO_PINS(1); 327DECLARE_MSM_GPIO_PINS(2); 328DECLARE_MSM_GPIO_PINS(3); 329DECLARE_MSM_GPIO_PINS(4); 330DECLARE_MSM_GPIO_PINS(5); 331DECLARE_MSM_GPIO_PINS(6); 332DECLARE_MSM_GPIO_PINS(7); 333DECLARE_MSM_GPIO_PINS(8); 334DECLARE_MSM_GPIO_PINS(9); 335DECLARE_MSM_GPIO_PINS(10); 336DECLARE_MSM_GPIO_PINS(11); 337DECLARE_MSM_GPIO_PINS(12); 338DECLARE_MSM_GPIO_PINS(13); 339DECLARE_MSM_GPIO_PINS(14); 340DECLARE_MSM_GPIO_PINS(15); 341DECLARE_MSM_GPIO_PINS(16); 342DECLARE_MSM_GPIO_PINS(17); 343DECLARE_MSM_GPIO_PINS(18); 344DECLARE_MSM_GPIO_PINS(19); 345DECLARE_MSM_GPIO_PINS(20); 346DECLARE_MSM_GPIO_PINS(21); 347DECLARE_MSM_GPIO_PINS(22); 348DECLARE_MSM_GPIO_PINS(23); 349DECLARE_MSM_GPIO_PINS(24); 350DECLARE_MSM_GPIO_PINS(25); 351DECLARE_MSM_GPIO_PINS(26); 352DECLARE_MSM_GPIO_PINS(27); 353DECLARE_MSM_GPIO_PINS(28); 354DECLARE_MSM_GPIO_PINS(29); 355DECLARE_MSM_GPIO_PINS(30); 356DECLARE_MSM_GPIO_PINS(31); 357DECLARE_MSM_GPIO_PINS(32); 358DECLARE_MSM_GPIO_PINS(33); 359DECLARE_MSM_GPIO_PINS(34); 360DECLARE_MSM_GPIO_PINS(35); 361DECLARE_MSM_GPIO_PINS(36); 362DECLARE_MSM_GPIO_PINS(37); 363DECLARE_MSM_GPIO_PINS(38); 364DECLARE_MSM_GPIO_PINS(39); 365DECLARE_MSM_GPIO_PINS(40); 366DECLARE_MSM_GPIO_PINS(41); 367DECLARE_MSM_GPIO_PINS(42); 368DECLARE_MSM_GPIO_PINS(43); 369DECLARE_MSM_GPIO_PINS(44); 370DECLARE_MSM_GPIO_PINS(45); 371DECLARE_MSM_GPIO_PINS(46); 372DECLARE_MSM_GPIO_PINS(47); 373DECLARE_MSM_GPIO_PINS(48); 374DECLARE_MSM_GPIO_PINS(49); 375DECLARE_MSM_GPIO_PINS(50); 376DECLARE_MSM_GPIO_PINS(51); 377DECLARE_MSM_GPIO_PINS(52); 378DECLARE_MSM_GPIO_PINS(53); 379DECLARE_MSM_GPIO_PINS(54); 380DECLARE_MSM_GPIO_PINS(55); 381DECLARE_MSM_GPIO_PINS(56); 382DECLARE_MSM_GPIO_PINS(57); 383DECLARE_MSM_GPIO_PINS(58); 384DECLARE_MSM_GPIO_PINS(59); 385DECLARE_MSM_GPIO_PINS(60); 386DECLARE_MSM_GPIO_PINS(61); 387DECLARE_MSM_GPIO_PINS(62); 388DECLARE_MSM_GPIO_PINS(63); 389DECLARE_MSM_GPIO_PINS(64); 390DECLARE_MSM_GPIO_PINS(65); 391DECLARE_MSM_GPIO_PINS(66); 392DECLARE_MSM_GPIO_PINS(67); 393DECLARE_MSM_GPIO_PINS(68); 394DECLARE_MSM_GPIO_PINS(69); 395DECLARE_MSM_GPIO_PINS(70); 396DECLARE_MSM_GPIO_PINS(71); 397DECLARE_MSM_GPIO_PINS(72); 398DECLARE_MSM_GPIO_PINS(73); 399DECLARE_MSM_GPIO_PINS(74); 400DECLARE_MSM_GPIO_PINS(75); 401DECLARE_MSM_GPIO_PINS(76); 402DECLARE_MSM_GPIO_PINS(77); 403DECLARE_MSM_GPIO_PINS(78); 404DECLARE_MSM_GPIO_PINS(79); 405DECLARE_MSM_GPIO_PINS(80); 406DECLARE_MSM_GPIO_PINS(81); 407DECLARE_MSM_GPIO_PINS(82); 408DECLARE_MSM_GPIO_PINS(83); 409DECLARE_MSM_GPIO_PINS(84); 410DECLARE_MSM_GPIO_PINS(85); 411DECLARE_MSM_GPIO_PINS(86); 412DECLARE_MSM_GPIO_PINS(87); 413DECLARE_MSM_GPIO_PINS(88); 414DECLARE_MSM_GPIO_PINS(89); 415DECLARE_MSM_GPIO_PINS(90); 416DECLARE_MSM_GPIO_PINS(91); 417DECLARE_MSM_GPIO_PINS(92); 418DECLARE_MSM_GPIO_PINS(93); 419DECLARE_MSM_GPIO_PINS(94); 420DECLARE_MSM_GPIO_PINS(95); 421DECLARE_MSM_GPIO_PINS(96); 422DECLARE_MSM_GPIO_PINS(97); 423DECLARE_MSM_GPIO_PINS(98); 424DECLARE_MSM_GPIO_PINS(99); 425DECLARE_MSM_GPIO_PINS(100); 426DECLARE_MSM_GPIO_PINS(101); 427DECLARE_MSM_GPIO_PINS(102); 428DECLARE_MSM_GPIO_PINS(103); 429DECLARE_MSM_GPIO_PINS(104); 430DECLARE_MSM_GPIO_PINS(105); 431DECLARE_MSM_GPIO_PINS(106); 432DECLARE_MSM_GPIO_PINS(107); 433DECLARE_MSM_GPIO_PINS(108); 434DECLARE_MSM_GPIO_PINS(109); 435DECLARE_MSM_GPIO_PINS(110); 436DECLARE_MSM_GPIO_PINS(111); 437DECLARE_MSM_GPIO_PINS(112); 438DECLARE_MSM_GPIO_PINS(113); 439DECLARE_MSM_GPIO_PINS(114); 440DECLARE_MSM_GPIO_PINS(115); 441DECLARE_MSM_GPIO_PINS(116); 442DECLARE_MSM_GPIO_PINS(117); 443DECLARE_MSM_GPIO_PINS(118); 444DECLARE_MSM_GPIO_PINS(119); 445DECLARE_MSM_GPIO_PINS(120); 446DECLARE_MSM_GPIO_PINS(121); 447DECLARE_MSM_GPIO_PINS(122); 448DECLARE_MSM_GPIO_PINS(123); 449DECLARE_MSM_GPIO_PINS(124); 450DECLARE_MSM_GPIO_PINS(125); 451DECLARE_MSM_GPIO_PINS(126); 452DECLARE_MSM_GPIO_PINS(127); 453DECLARE_MSM_GPIO_PINS(128); 454DECLARE_MSM_GPIO_PINS(129); 455DECLARE_MSM_GPIO_PINS(130); 456DECLARE_MSM_GPIO_PINS(131); 457DECLARE_MSM_GPIO_PINS(132); 458DECLARE_MSM_GPIO_PINS(133); 459DECLARE_MSM_GPIO_PINS(134); 460DECLARE_MSM_GPIO_PINS(135); 461DECLARE_MSM_GPIO_PINS(136); 462DECLARE_MSM_GPIO_PINS(137); 463DECLARE_MSM_GPIO_PINS(138); 464DECLARE_MSM_GPIO_PINS(139); 465DECLARE_MSM_GPIO_PINS(140); 466DECLARE_MSM_GPIO_PINS(141); 467DECLARE_MSM_GPIO_PINS(142); 468DECLARE_MSM_GPIO_PINS(143); 469DECLARE_MSM_GPIO_PINS(144); 470DECLARE_MSM_GPIO_PINS(145); 471DECLARE_MSM_GPIO_PINS(146); 472DECLARE_MSM_GPIO_PINS(147); 473DECLARE_MSM_GPIO_PINS(148); 474DECLARE_MSM_GPIO_PINS(149); 475DECLARE_MSM_GPIO_PINS(150); 476DECLARE_MSM_GPIO_PINS(151); 477DECLARE_MSM_GPIO_PINS(152); 478DECLARE_MSM_GPIO_PINS(153); 479DECLARE_MSM_GPIO_PINS(154); 480DECLARE_MSM_GPIO_PINS(155); 481DECLARE_MSM_GPIO_PINS(156); 482DECLARE_MSM_GPIO_PINS(157); 483DECLARE_MSM_GPIO_PINS(158); 484DECLARE_MSM_GPIO_PINS(159); 485DECLARE_MSM_GPIO_PINS(160); 486DECLARE_MSM_GPIO_PINS(161); 487DECLARE_MSM_GPIO_PINS(162); 488DECLARE_MSM_GPIO_PINS(163); 489DECLARE_MSM_GPIO_PINS(164); 490DECLARE_MSM_GPIO_PINS(165); 491DECLARE_MSM_GPIO_PINS(166); 492DECLARE_MSM_GPIO_PINS(167); 493DECLARE_MSM_GPIO_PINS(168); 494DECLARE_MSM_GPIO_PINS(169); 495DECLARE_MSM_GPIO_PINS(170); 496DECLARE_MSM_GPIO_PINS(171); 497DECLARE_MSM_GPIO_PINS(172); 498DECLARE_MSM_GPIO_PINS(173); 499DECLARE_MSM_GPIO_PINS(174); 500DECLARE_MSM_GPIO_PINS(175); 501DECLARE_MSM_GPIO_PINS(176); 502DECLARE_MSM_GPIO_PINS(177); 503DECLARE_MSM_GPIO_PINS(178); 504DECLARE_MSM_GPIO_PINS(179); 505DECLARE_MSM_GPIO_PINS(180); 506DECLARE_MSM_GPIO_PINS(181); 507DECLARE_MSM_GPIO_PINS(182); 508DECLARE_MSM_GPIO_PINS(183); 509DECLARE_MSM_GPIO_PINS(184); 510DECLARE_MSM_GPIO_PINS(185); 511DECLARE_MSM_GPIO_PINS(186); 512DECLARE_MSM_GPIO_PINS(187); 513DECLARE_MSM_GPIO_PINS(188); 514DECLARE_MSM_GPIO_PINS(189); 515DECLARE_MSM_GPIO_PINS(190); 516DECLARE_MSM_GPIO_PINS(191); 517DECLARE_MSM_GPIO_PINS(192); 518DECLARE_MSM_GPIO_PINS(193); 519DECLARE_MSM_GPIO_PINS(194); 520DECLARE_MSM_GPIO_PINS(195); 521DECLARE_MSM_GPIO_PINS(196); 522DECLARE_MSM_GPIO_PINS(197); 523DECLARE_MSM_GPIO_PINS(198); 524DECLARE_MSM_GPIO_PINS(199); 525DECLARE_MSM_GPIO_PINS(200); 526DECLARE_MSM_GPIO_PINS(201); 527DECLARE_MSM_GPIO_PINS(202); 528DECLARE_MSM_GPIO_PINS(203); 529DECLARE_MSM_GPIO_PINS(204); 530DECLARE_MSM_GPIO_PINS(205); 531DECLARE_MSM_GPIO_PINS(206); 532DECLARE_MSM_GPIO_PINS(207); 533DECLARE_MSM_GPIO_PINS(208); 534DECLARE_MSM_GPIO_PINS(209); 535 536static const unsigned int ufs_reset_pins[] = { 210 }; 537static const unsigned int sdc2_clk_pins[] = { 211 }; 538static const unsigned int sdc2_cmd_pins[] = { 212 }; 539static const unsigned int sdc2_data_pins[] = { 213 }; 540 541enum sm8450_functions { 542 msm_mux_gpio, 543 msm_mux_aon_cam, 544 msm_mux_atest_char, 545 msm_mux_atest_usb, 546 msm_mux_audio_ref, 547 msm_mux_cam_mclk, 548 msm_mux_cci_async, 549 msm_mux_cci_i2c, 550 msm_mux_cci_timer, 551 msm_mux_cmu_rng, 552 msm_mux_coex_uart1, 553 msm_mux_coex_uart2, 554 msm_mux_cri_trng, 555 msm_mux_cri_trng0, 556 msm_mux_cri_trng1, 557 msm_mux_dbg_out, 558 msm_mux_ddr_bist, 559 msm_mux_ddr_pxi0, 560 msm_mux_ddr_pxi1, 561 msm_mux_ddr_pxi2, 562 msm_mux_ddr_pxi3, 563 msm_mux_dp_hot, 564 msm_mux_egpio, 565 msm_mux_gcc_gp1, 566 msm_mux_gcc_gp2, 567 msm_mux_gcc_gp3, 568 msm_mux_ibi_i3c, 569 msm_mux_jitter_bist, 570 msm_mux_mdp_vsync, 571 msm_mux_mdp_vsync0, 572 msm_mux_mdp_vsync1, 573 msm_mux_mdp_vsync2, 574 msm_mux_mdp_vsync3, 575 msm_mux_mi2s0_data0, 576 msm_mux_mi2s0_data1, 577 msm_mux_mi2s0_sck, 578 msm_mux_mi2s0_ws, 579 msm_mux_mi2s2_data0, 580 msm_mux_mi2s2_data1, 581 msm_mux_mi2s2_sck, 582 msm_mux_mi2s2_ws, 583 msm_mux_mss_grfc0, 584 msm_mux_mss_grfc1, 585 msm_mux_mss_grfc10, 586 msm_mux_mss_grfc11, 587 msm_mux_mss_grfc12, 588 msm_mux_mss_grfc2, 589 msm_mux_mss_grfc3, 590 msm_mux_mss_grfc4, 591 msm_mux_mss_grfc5, 592 msm_mux_mss_grfc6, 593 msm_mux_mss_grfc7, 594 msm_mux_mss_grfc8, 595 msm_mux_mss_grfc9, 596 msm_mux_nav, 597 msm_mux_pcie0_clkreqn, 598 msm_mux_pcie1_clkreqn, 599 msm_mux_phase_flag, 600 msm_mux_pll_bist, 601 msm_mux_pll_clk, 602 msm_mux_pri_mi2s, 603 msm_mux_prng_rosc, 604 msm_mux_qdss_cti, 605 msm_mux_qdss_gpio, 606 msm_mux_qlink0_enable, 607 msm_mux_qlink0_request, 608 msm_mux_qlink0_wmss, 609 msm_mux_qlink1_enable, 610 msm_mux_qlink1_request, 611 msm_mux_qlink1_wmss, 612 msm_mux_qlink2_enable, 613 msm_mux_qlink2_request, 614 msm_mux_qlink2_wmss, 615 msm_mux_qspi0, 616 msm_mux_qspi1, 617 msm_mux_qspi2, 618 msm_mux_qspi3, 619 msm_mux_qspi_clk, 620 msm_mux_qspi_cs, 621 msm_mux_qup0, 622 msm_mux_qup1, 623 msm_mux_qup10, 624 msm_mux_qup11, 625 msm_mux_qup12, 626 msm_mux_qup13, 627 msm_mux_qup14, 628 msm_mux_qup15, 629 msm_mux_qup16, 630 msm_mux_qup17, 631 msm_mux_qup18, 632 msm_mux_qup19, 633 msm_mux_qup2, 634 msm_mux_qup20, 635 msm_mux_qup21, 636 msm_mux_qup3, 637 msm_mux_qup4, 638 msm_mux_qup5, 639 msm_mux_qup6, 640 msm_mux_qup7, 641 msm_mux_qup8, 642 msm_mux_qup9, 643 msm_mux_qup_l4, 644 msm_mux_qup_l5, 645 msm_mux_qup_l6, 646 msm_mux_sd_write, 647 msm_mux_sdc40, 648 msm_mux_sdc41, 649 msm_mux_sdc42, 650 msm_mux_sdc43, 651 msm_mux_sdc4_clk, 652 msm_mux_sdc4_cmd, 653 msm_mux_sec_mi2s, 654 msm_mux_tb_trig, 655 msm_mux_tgu_ch0, 656 msm_mux_tgu_ch1, 657 msm_mux_tgu_ch2, 658 msm_mux_tgu_ch3, 659 msm_mux_tmess_prng0, 660 msm_mux_tmess_prng1, 661 msm_mux_tmess_prng2, 662 msm_mux_tmess_prng3, 663 msm_mux_tsense_pwm1, 664 msm_mux_tsense_pwm2, 665 msm_mux_uim0_clk, 666 msm_mux_uim0_data, 667 msm_mux_uim0_present, 668 msm_mux_uim0_reset, 669 msm_mux_uim1_clk, 670 msm_mux_uim1_data, 671 msm_mux_uim1_present, 672 msm_mux_uim1_reset, 673 msm_mux_usb2phy_ac, 674 msm_mux_usb_phy, 675 msm_mux_vfr_0, 676 msm_mux_vfr_1, 677 msm_mux_vsense_trigger, 678 msm_mux__, 679}; 680 681static const char * const gpio_groups[] = { 682 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 683 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 684 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 685 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 686 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 687 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 688 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 689 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 690 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 691 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 692 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 693 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 694 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 695 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 696 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 697 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 698 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 699 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", 700 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", 701 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", 702 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", 703 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", 704 "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", 705 "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", 706 "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", 707 "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", 708 "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", 709 "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", 710 "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", 711 "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", 712 "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", 713 "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", 714 "gpio207", "gpio208", "gpio209", 715}; 716 717static const char * const egpio_groups[] = { 718 "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", 719 "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", 720 "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", 721 "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", 722 "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", 723 "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", 724 "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", 725 "gpio207", "gpio208", "gpio209", 726}; 727 728static const char * const aon_cam_groups[] = { 729 "gpio108", 730}; 731 732static const char * const atest_char_groups[] = { 733 "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", 734}; 735 736static const char * const atest_usb_groups[] = { 737 "gpio37", "gpio39", "gpio55", "gpio148", "gpio149", 738}; 739 740static const char * const audio_ref_groups[] = { 741 "gpio124", 742}; 743 744static const char * const cam_mclk_groups[] = { 745 "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", 746}; 747 748static const char * const cci_async_groups[] = { 749 "gpio109", "gpio119", "gpio120", 750}; 751 752static const char * const cci_i2c_groups[] = { 753 "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio208", "gpio209", 754}; 755 756static const char * const cci_timer_groups[] = { 757 "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", 758}; 759 760static const char * const cmu_rng_groups[] = { 761 "gpio94", "gpio95", "gpio96", "gpio97", 762}; 763 764static const char * const coex_uart1_groups[] = { 765 "gpio148", "gpio149", 766}; 767 768static const char * const coex_uart2_groups[] = { 769 "gpio150", "gpio151", 770}; 771 772static const char * const cri_trng_groups[] = { 773 "gpio99", 774}; 775 776static const char * const cri_trng0_groups[] = { 777 "gpio71", 778}; 779 780static const char * const cri_trng1_groups[] = { 781 "gpio72", 782}; 783 784static const char * const dbg_out_groups[] = { 785 "gpio9", 786}; 787 788static const char * const ddr_bist_groups[] = { 789 "gpio36", "gpio37", "gpio40", "gpio41", 790}; 791 792static const char * const ddr_pxi0_groups[] = { 793 "gpio51", "gpio52", 794}; 795 796static const char * const ddr_pxi1_groups[] = { 797 "gpio40", "gpio41", 798}; 799 800static const char * const ddr_pxi2_groups[] = { 801 "gpio45", "gpio47", 802}; 803 804static const char * const ddr_pxi3_groups[] = { 805 "gpio43", "gpio44", 806}; 807 808static const char * const dp_hot_groups[] = { 809 "gpio47", 810}; 811 812static const char * const gcc_gp1_groups[] = { 813 "gpio86", "gpio134", 814}; 815 816static const char * const gcc_gp2_groups[] = { 817 "gpio87", "gpio135", 818}; 819 820static const char * const gcc_gp3_groups[] = { 821 "gpio88", "gpio136", 822}; 823 824static const char * const ibi_i3c_groups[] = { 825 "gpio28", "gpio29", "gpio32", "gpio33", "gpio56", "gpio57", "gpio60", "gpio61", 826}; 827 828static const char * const jitter_bist_groups[] = { 829 "gpio24", 830}; 831 832static const char * const mdp_vsync_groups[] = { 833 "gpio46", "gpio47", "gpio86", "gpio87", "gpio88", 834}; 835 836static const char * const mdp_vsync0_groups[] = { 837 "gpio86", 838}; 839 840static const char * const mdp_vsync1_groups[] = { 841 "gpio86", 842}; 843 844static const char * const mdp_vsync2_groups[] = { 845 "gpio87", 846}; 847 848static const char * const mdp_vsync3_groups[] = { 849 "gpio87", 850}; 851 852static const char * const mi2s0_data0_groups[] = { 853 "gpio127", 854}; 855 856static const char * const mi2s0_data1_groups[] = { 857 "gpio128", 858}; 859 860static const char * const mi2s0_sck_groups[] = { 861 "gpio126", 862}; 863 864static const char * const mi2s0_ws_groups[] = { 865 "gpio129", 866}; 867 868static const char * const mi2s2_data0_groups[] = { 869 "gpio122", 870}; 871 872static const char * const mi2s2_data1_groups[] = { 873 "gpio124", 874}; 875 876static const char * const mi2s2_sck_groups[] = { 877 "gpio121", 878}; 879 880static const char * const mi2s2_ws_groups[] = { 881 "gpio123", 882}; 883 884static const char * const mss_grfc0_groups[] = { 885 "gpio138", "gpio153", 886}; 887 888static const char * const mss_grfc1_groups[] = { 889 "gpio139", 890}; 891 892static const char * const mss_grfc10_groups[] = { 893 "gpio150", 894}; 895 896static const char * const mss_grfc11_groups[] = { 897 "gpio151", 898}; 899 900static const char * const mss_grfc12_groups[] = { 901 "gpio152", 902}; 903 904static const char * const mss_grfc2_groups[] = { 905 "gpio140", 906}; 907 908static const char * const mss_grfc3_groups[] = { 909 "gpio141", 910}; 911 912static const char * const mss_grfc4_groups[] = { 913 "gpio142", 914}; 915 916static const char * const mss_grfc5_groups[] = { 917 "gpio143", 918}; 919 920static const char * const mss_grfc6_groups[] = { 921 "gpio144", 922}; 923 924static const char * const mss_grfc7_groups[] = { 925 "gpio145", 926}; 927 928static const char * const mss_grfc8_groups[] = { 929 "gpio146", 930}; 931 932static const char * const mss_grfc9_groups[] = { 933 "gpio147", 934}; 935 936static const char * const nav_groups[] = { 937 "gpio153", "gpio154", "gpio155", 938}; 939 940static const char * const pcie0_clkreqn_groups[] = { 941 "gpio95", 942}; 943 944static const char * const pcie1_clkreqn_groups[] = { 945 "gpio98", 946}; 947 948static const char * const phase_flag_groups[] = { 949 "gpio4", "gpio5", "gpio6", "gpio7", "gpio10", "gpio11", "gpio12", "gpio13", 950 "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio25", "gpio26", 951 "gpio76", "gpio77", "gpio78", "gpio79", "gpio81", "gpio82", "gpio83", "gpio92", 952 "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", 953}; 954 955static const char * const pll_bist_groups[] = { 956 "gpio20", 957}; 958 959static const char * const pll_clk_groups[] = { 960 "gpio107", 961}; 962 963static const char * const pri_mi2s_groups[] = { 964 "gpio125", 965}; 966 967static const char * const prng_rosc_groups[] = { 968 "gpio73", "gpio75", "gpio81", "gpio83", "gpio81", 969}; 970 971static const char * const qdss_cti_groups[] = { 972 "gpio2", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", "gpio85", "gpio93", 973}; 974 975static const char * const qdss_gpio_groups[] = { 976 "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", 977 "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio117", "gpio118", 978 "gpio119", "gpio120", "gpio188", "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", 979 "gpio194", "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", "gpio201", 980 "gpio202", "gpio203", "gpio204", "gpio205", 981}; 982 983static const char * const qlink0_enable_groups[] = { 984 "gpio157", 985}; 986 987static const char * const qlink0_request_groups[] = { 988 "gpio156", 989}; 990 991static const char * const qlink0_wmss_groups[] = { 992 "gpio158", 993}; 994 995static const char * const qlink1_enable_groups[] = { 996 "gpio160", 997}; 998 999static const char * const qlink1_request_groups[] = { 1000 "gpio159", 1001}; 1002 1003static const char * const qlink1_wmss_groups[] = { 1004 "gpio161", 1005}; 1006 1007static const char * const qlink2_enable_groups[] = { 1008 "gpio163", 1009}; 1010 1011static const char * const qlink2_request_groups[] = { 1012 "gpio162", 1013}; 1014 1015static const char * const qlink2_wmss_groups[] = { 1016 "gpio164", 1017}; 1018 1019static const char * const qspi0_groups[] = { 1020 "gpio52", 1021}; 1022 1023static const char * const qspi1_groups[] = { 1024 "gpio53", 1025}; 1026 1027static const char * const qspi2_groups[] = { 1028 "gpio48", 1029}; 1030 1031static const char * const qspi3_groups[] = { 1032 "gpio49", 1033}; 1034 1035static const char * const qspi_clk_groups[] = { 1036 "gpio50", 1037}; 1038 1039static const char * const qspi_cs_groups[] = { 1040 "gpio51", "gpio54", 1041}; 1042 1043static const char * const qup0_groups[] = { 1044 "gpio0", "gpio1", "gpio2", "gpio3", 1045}; 1046 1047static const char * const qup1_groups[] = { 1048 "gpio4", "gpio5", "gpio6", "gpio7", 1049}; 1050 1051static const char * const qup10_groups[] = { 1052 "gpio36", "gpio37", "gpio38", "gpio39", 1053}; 1054 1055static const char * const qup11_groups[] = { 1056 "gpio40", "gpio41", "gpio42", "gpio43", 1057}; 1058 1059static const char * const qup12_groups[] = { 1060 "gpio44", "gpio45", "gpio46", "gpio47", 1061}; 1062 1063static const char * const qup13_groups[] = { 1064 "gpio48", "gpio49", "gpio50", "gpio51", 1065}; 1066 1067static const char * const qup14_groups[] = { 1068 "gpio52", "gpio53", "gpio54", "gpio55", 1069}; 1070 1071static const char * const qup15_groups[] = { 1072 "gpio56", "gpio57", "gpio58", "gpio59", 1073}; 1074 1075static const char * const qup16_groups[] = { 1076 "gpio60", "gpio61", "gpio62", "gpio63", 1077}; 1078 1079static const char * const qup17_groups[] = { 1080 "gpio64", "gpio65", "gpio66", "gpio67", 1081}; 1082 1083static const char * const qup18_groups[] = { 1084 "gpio68", "gpio69", "gpio70", "gpio71", 1085}; 1086 1087static const char * const qup19_groups[] = { 1088 "gpio72", "gpio73", "gpio74", "gpio75", 1089}; 1090 1091static const char * const qup2_groups[] = { 1092 "gpio8", "gpio9", "gpio10", "gpio11", 1093}; 1094 1095static const char * const qup20_groups[] = { 1096 "gpio76", "gpio77", "gpio78", "gpio79", 1097}; 1098 1099static const char * const qup21_groups[] = { 1100 "gpio80", "gpio81", "gpio82", "gpio83", 1101}; 1102 1103static const char * const qup3_groups[] = { 1104 "gpio12", "gpio13", "gpio14", "gpio15", 1105}; 1106 1107static const char * const qup4_groups[] = { 1108 "gpio16", "gpio17", "gpio18", "gpio19", 1109}; 1110 1111static const char * const qup5_groups[] = { 1112 "gpio84", "gpio85", "gpio206", "gpio207", 1113}; 1114 1115static const char * const qup6_groups[] = { 1116 "gpio20", "gpio21", "gpio22", "gpio23", 1117}; 1118 1119static const char * const qup7_groups[] = { 1120 "gpio24", "gpio25", "gpio26", "gpio27", 1121}; 1122 1123static const char * const qup8_groups[] = { 1124 "gpio28", "gpio29", "gpio30", "gpio31", 1125}; 1126 1127static const char * const qup9_groups[] = { 1128 "gpio32", "gpio33", "gpio34", "gpio35", 1129}; 1130 1131static const char * const qup_l4_groups[] = { 1132 "gpio24", "gpio40", "gpio58", "gpio63", 1133}; 1134 1135static const char * const qup_l5_groups[] = { 1136 "gpio25", "gpio41", "gpio59", "gpio66", 1137}; 1138 1139static const char * const qup_l6_groups[] = { 1140 "gpio26", "gpio42", "gpio62", "gpio67", 1141}; 1142 1143static const char * const sd_write_groups[] = { 1144 "gpio93", 1145}; 1146 1147static const char * const sdc40_groups[] = { 1148 "gpio52", 1149}; 1150 1151static const char * const sdc41_groups[] = { 1152 "gpio53", 1153}; 1154 1155static const char * const sdc42_groups[] = { 1156 "gpio48", 1157}; 1158 1159static const char * const sdc43_groups[] = { 1160 "gpio49", 1161}; 1162 1163static const char * const sdc4_clk_groups[] = { 1164 "gpio50", 1165}; 1166 1167static const char * const sdc4_cmd_groups[] = { 1168 "gpio51", 1169}; 1170 1171static const char * const sec_mi2s_groups[] = { 1172 "gpio124", 1173}; 1174 1175static const char * const tb_trig_groups[] = { 1176 "gpio64", "gpio137", 1177}; 1178 1179static const char * const tgu_ch0_groups[] = { 1180 "gpio64", 1181}; 1182 1183static const char * const tgu_ch1_groups[] = { 1184 "gpio65", 1185}; 1186 1187static const char * const tgu_ch2_groups[] = { 1188 "gpio66", 1189}; 1190 1191static const char * const tgu_ch3_groups[] = { 1192 "gpio67", 1193}; 1194 1195static const char * const tmess_prng0_groups[] = { 1196 "gpio80", 1197}; 1198 1199static const char * const tmess_prng1_groups[] = { 1200 "gpio79", 1201}; 1202 1203static const char * const tmess_prng2_groups[] = { 1204 "gpio77", 1205}; 1206 1207static const char * const tmess_prng3_groups[] = { 1208 "gpio76", 1209}; 1210 1211static const char * const tsense_pwm1_groups[] = { 1212 "gpio91", 1213}; 1214 1215static const char * const tsense_pwm2_groups[] = { 1216 "gpio91", 1217}; 1218 1219static const char * const uim0_clk_groups[] = { 1220 "gpio131", 1221}; 1222 1223static const char * const uim0_data_groups[] = { 1224 "gpio130", 1225}; 1226 1227static const char * const uim0_present_groups[] = { 1228 "gpio133", 1229}; 1230 1231static const char * const uim0_reset_groups[] = { 1232 "gpio132", 1233}; 1234 1235static const char * const uim1_clk_groups[] = { 1236 "gpio135", 1237}; 1238 1239static const char * const uim1_data_groups[] = { 1240 "gpio134", 1241}; 1242 1243static const char * const uim1_present_groups[] = { 1244 "gpio137", 1245}; 1246 1247static const char * const uim1_reset_groups[] = { 1248 "gpio136", 1249}; 1250 1251static const char * const usb2phy_ac_groups[] = { 1252 "gpio90", 1253}; 1254 1255static const char * const usb_phy_groups[] = { 1256 "gpio91", 1257}; 1258 1259static const char * const vfr_0_groups[] = { 1260 "gpio89", 1261}; 1262 1263static const char * const vfr_1_groups[] = { 1264 "gpio155", 1265}; 1266 1267static const char * const vsense_trigger_groups[] = { 1268 "gpio18", 1269}; 1270 1271static const struct pinfunction sm8450_functions[] = { 1272 MSM_PIN_FUNCTION(gpio), 1273 MSM_PIN_FUNCTION(aon_cam), 1274 MSM_PIN_FUNCTION(atest_char), 1275 MSM_PIN_FUNCTION(atest_usb), 1276 MSM_PIN_FUNCTION(audio_ref), 1277 MSM_PIN_FUNCTION(cam_mclk), 1278 MSM_PIN_FUNCTION(cci_async), 1279 MSM_PIN_FUNCTION(cci_i2c), 1280 MSM_PIN_FUNCTION(cci_timer), 1281 MSM_PIN_FUNCTION(cmu_rng), 1282 MSM_PIN_FUNCTION(coex_uart1), 1283 MSM_PIN_FUNCTION(coex_uart2), 1284 MSM_PIN_FUNCTION(cri_trng), 1285 MSM_PIN_FUNCTION(cri_trng0), 1286 MSM_PIN_FUNCTION(cri_trng1), 1287 MSM_PIN_FUNCTION(dbg_out), 1288 MSM_PIN_FUNCTION(ddr_bist), 1289 MSM_PIN_FUNCTION(ddr_pxi0), 1290 MSM_PIN_FUNCTION(ddr_pxi1), 1291 MSM_PIN_FUNCTION(ddr_pxi2), 1292 MSM_PIN_FUNCTION(ddr_pxi3), 1293 MSM_PIN_FUNCTION(dp_hot), 1294 MSM_PIN_FUNCTION(egpio), 1295 MSM_PIN_FUNCTION(gcc_gp1), 1296 MSM_PIN_FUNCTION(gcc_gp2), 1297 MSM_PIN_FUNCTION(gcc_gp3), 1298 MSM_PIN_FUNCTION(ibi_i3c), 1299 MSM_PIN_FUNCTION(jitter_bist), 1300 MSM_PIN_FUNCTION(mdp_vsync), 1301 MSM_PIN_FUNCTION(mdp_vsync0), 1302 MSM_PIN_FUNCTION(mdp_vsync1), 1303 MSM_PIN_FUNCTION(mdp_vsync2), 1304 MSM_PIN_FUNCTION(mdp_vsync3), 1305 MSM_PIN_FUNCTION(mi2s0_data0), 1306 MSM_PIN_FUNCTION(mi2s0_data1), 1307 MSM_PIN_FUNCTION(mi2s0_sck), 1308 MSM_PIN_FUNCTION(mi2s0_ws), 1309 MSM_PIN_FUNCTION(mi2s2_data0), 1310 MSM_PIN_FUNCTION(mi2s2_data1), 1311 MSM_PIN_FUNCTION(mi2s2_sck), 1312 MSM_PIN_FUNCTION(mi2s2_ws), 1313 MSM_PIN_FUNCTION(mss_grfc0), 1314 MSM_PIN_FUNCTION(mss_grfc1), 1315 MSM_PIN_FUNCTION(mss_grfc10), 1316 MSM_PIN_FUNCTION(mss_grfc11), 1317 MSM_PIN_FUNCTION(mss_grfc12), 1318 MSM_PIN_FUNCTION(mss_grfc2), 1319 MSM_PIN_FUNCTION(mss_grfc3), 1320 MSM_PIN_FUNCTION(mss_grfc4), 1321 MSM_PIN_FUNCTION(mss_grfc5), 1322 MSM_PIN_FUNCTION(mss_grfc6), 1323 MSM_PIN_FUNCTION(mss_grfc7), 1324 MSM_PIN_FUNCTION(mss_grfc8), 1325 MSM_PIN_FUNCTION(mss_grfc9), 1326 MSM_PIN_FUNCTION(nav), 1327 MSM_PIN_FUNCTION(pcie0_clkreqn), 1328 MSM_PIN_FUNCTION(pcie1_clkreqn), 1329 MSM_PIN_FUNCTION(phase_flag), 1330 MSM_PIN_FUNCTION(pll_bist), 1331 MSM_PIN_FUNCTION(pll_clk), 1332 MSM_PIN_FUNCTION(pri_mi2s), 1333 MSM_PIN_FUNCTION(prng_rosc), 1334 MSM_PIN_FUNCTION(qdss_cti), 1335 MSM_PIN_FUNCTION(qdss_gpio), 1336 MSM_PIN_FUNCTION(qlink0_enable), 1337 MSM_PIN_FUNCTION(qlink0_request), 1338 MSM_PIN_FUNCTION(qlink0_wmss), 1339 MSM_PIN_FUNCTION(qlink1_enable), 1340 MSM_PIN_FUNCTION(qlink1_request), 1341 MSM_PIN_FUNCTION(qlink1_wmss), 1342 MSM_PIN_FUNCTION(qlink2_enable), 1343 MSM_PIN_FUNCTION(qlink2_request), 1344 MSM_PIN_FUNCTION(qlink2_wmss), 1345 MSM_PIN_FUNCTION(qspi0), 1346 MSM_PIN_FUNCTION(qspi1), 1347 MSM_PIN_FUNCTION(qspi2), 1348 MSM_PIN_FUNCTION(qspi3), 1349 MSM_PIN_FUNCTION(qspi_clk), 1350 MSM_PIN_FUNCTION(qspi_cs), 1351 MSM_PIN_FUNCTION(qup0), 1352 MSM_PIN_FUNCTION(qup1), 1353 MSM_PIN_FUNCTION(qup10), 1354 MSM_PIN_FUNCTION(qup11), 1355 MSM_PIN_FUNCTION(qup12), 1356 MSM_PIN_FUNCTION(qup13), 1357 MSM_PIN_FUNCTION(qup14), 1358 MSM_PIN_FUNCTION(qup15), 1359 MSM_PIN_FUNCTION(qup16), 1360 MSM_PIN_FUNCTION(qup17), 1361 MSM_PIN_FUNCTION(qup18), 1362 MSM_PIN_FUNCTION(qup19), 1363 MSM_PIN_FUNCTION(qup2), 1364 MSM_PIN_FUNCTION(qup20), 1365 MSM_PIN_FUNCTION(qup21), 1366 MSM_PIN_FUNCTION(qup3), 1367 MSM_PIN_FUNCTION(qup4), 1368 MSM_PIN_FUNCTION(qup5), 1369 MSM_PIN_FUNCTION(qup6), 1370 MSM_PIN_FUNCTION(qup7), 1371 MSM_PIN_FUNCTION(qup8), 1372 MSM_PIN_FUNCTION(qup9), 1373 MSM_PIN_FUNCTION(qup_l4), 1374 MSM_PIN_FUNCTION(qup_l5), 1375 MSM_PIN_FUNCTION(qup_l6), 1376 MSM_PIN_FUNCTION(sd_write), 1377 MSM_PIN_FUNCTION(sdc40), 1378 MSM_PIN_FUNCTION(sdc41), 1379 MSM_PIN_FUNCTION(sdc42), 1380 MSM_PIN_FUNCTION(sdc43), 1381 MSM_PIN_FUNCTION(sdc4_clk), 1382 MSM_PIN_FUNCTION(sdc4_cmd), 1383 MSM_PIN_FUNCTION(sec_mi2s), 1384 MSM_PIN_FUNCTION(tb_trig), 1385 MSM_PIN_FUNCTION(tgu_ch0), 1386 MSM_PIN_FUNCTION(tgu_ch1), 1387 MSM_PIN_FUNCTION(tgu_ch2), 1388 MSM_PIN_FUNCTION(tgu_ch3), 1389 MSM_PIN_FUNCTION(tmess_prng0), 1390 MSM_PIN_FUNCTION(tmess_prng1), 1391 MSM_PIN_FUNCTION(tmess_prng2), 1392 MSM_PIN_FUNCTION(tmess_prng3), 1393 MSM_PIN_FUNCTION(tsense_pwm1), 1394 MSM_PIN_FUNCTION(tsense_pwm2), 1395 MSM_PIN_FUNCTION(uim0_clk), 1396 MSM_PIN_FUNCTION(uim0_data), 1397 MSM_PIN_FUNCTION(uim0_present), 1398 MSM_PIN_FUNCTION(uim0_reset), 1399 MSM_PIN_FUNCTION(uim1_clk), 1400 MSM_PIN_FUNCTION(uim1_data), 1401 MSM_PIN_FUNCTION(uim1_present), 1402 MSM_PIN_FUNCTION(uim1_reset), 1403 MSM_PIN_FUNCTION(usb2phy_ac), 1404 MSM_PIN_FUNCTION(usb_phy), 1405 MSM_PIN_FUNCTION(vfr_0), 1406 MSM_PIN_FUNCTION(vfr_1), 1407 MSM_PIN_FUNCTION(vsense_trigger), 1408}; 1409 1410/* Every pin is maintained as a single group, and missing or non-existing pin 1411 * would be maintained as dummy group to synchronize pin group index with 1412 * pin descriptor registered with pinctrl core. 1413 * Clients would not be able to request these dummy pin groups. 1414 */ 1415static const struct msm_pingroup sm8450_groups[] = { 1416 [0] = PINGROUP(0, qup0, _, _, _, _, _, _, _, _), 1417 [1] = PINGROUP(1, qup0, _, _, _, _, _, _, _, _), 1418 [2] = PINGROUP(2, qup0, qdss_cti, _, _, _, _, _, _, _), 1419 [3] = PINGROUP(3, qup0, _, _, _, _, _, _, _, _), 1420 [4] = PINGROUP(4, qup1, phase_flag, _, _, _, _, _, _, _), 1421 [5] = PINGROUP(5, qup1, phase_flag, _, _, _, _, _, _, _), 1422 [6] = PINGROUP(6, qup1, phase_flag, _, _, _, _, _, _, _), 1423 [7] = PINGROUP(7, qup1, phase_flag, _, _, _, _, _, _, _), 1424 [8] = PINGROUP(8, qup2, _, _, _, _, _, _, _, _), 1425 [9] = PINGROUP(9, qup2, dbg_out, _, _, _, _, _, _, _), 1426 [10] = PINGROUP(10, qup2, phase_flag, _, _, _, _, _, _, _), 1427 [11] = PINGROUP(11, qup2, phase_flag, _, _, _, _, _, _, _), 1428 [12] = PINGROUP(12, qup3, phase_flag, _, _, _, _, _, _, _), 1429 [13] = PINGROUP(13, qup3, phase_flag, _, _, _, _, _, _, _), 1430 [14] = PINGROUP(14, qup3, phase_flag, _, _, _, _, _, _, _), 1431 [15] = PINGROUP(15, qup3, phase_flag, _, _, _, _, _, _, _), 1432 [16] = PINGROUP(16, qup4, phase_flag, _, _, _, _, _, _, _), 1433 [17] = PINGROUP(17, qup4, phase_flag, _, _, _, _, _, _, _), 1434 [18] = PINGROUP(18, qup4, phase_flag, _, vsense_trigger, _, _, _, _, _), 1435 [19] = PINGROUP(19, qup4, phase_flag, _, _, _, _, _, _, _), 1436 [20] = PINGROUP(20, qup6, pll_bist, _, _, _, _, _, _, _), 1437 [21] = PINGROUP(21, qup6, _, _, _, _, _, _, _, _), 1438 [22] = PINGROUP(22, qup6, _, _, _, _, _, _, _, _), 1439 [23] = PINGROUP(23, qup6, _, _, _, _, _, _, _, _), 1440 [24] = PINGROUP(24, qup7, qup_l4, jitter_bist, _, _, _, _, _, _), 1441 [25] = PINGROUP(25, qup7, qup_l5, phase_flag, _, _, _, _, _, _), 1442 [26] = PINGROUP(26, qup7, qup_l6, phase_flag, _, _, _, _, _, _), 1443 [27] = PINGROUP(27, qup7, _, _, _, _, _, _, _, _), 1444 [28] = PINGROUP(28, qup8, ibi_i3c, _, _, _, _, _, _, _), 1445 [29] = PINGROUP(29, qup8, ibi_i3c, _, _, _, _, _, _, _), 1446 [30] = PINGROUP(30, qup8, _, _, _, _, _, _, _, _), 1447 [31] = PINGROUP(31, qup8, _, _, _, _, _, _, _, _), 1448 [32] = PINGROUP(32, qup9, ibi_i3c, _, _, _, _, _, _, _), 1449 [33] = PINGROUP(33, qup9, ibi_i3c, _, _, _, _, _, _, _), 1450 [34] = PINGROUP(34, qup9, _, _, _, _, _, _, _, _), 1451 [35] = PINGROUP(35, qup9, _, _, _, _, _, _, _, _), 1452 [36] = PINGROUP(36, qup10, ddr_bist, _, _, _, _, _, _, _), 1453 [37] = PINGROUP(37, qup10, ddr_bist, atest_usb, _, _, _, _, _, _), 1454 [38] = PINGROUP(38, qup10, _, _, _, _, _, _, _, _), 1455 [39] = PINGROUP(39, qup10, atest_usb, _, _, _, _, _, _, _), 1456 [40] = PINGROUP(40, qup11, qup_l4, ddr_bist, ddr_pxi1, _, _, _, _, _), 1457 [41] = PINGROUP(41, qup11, qup_l5, ddr_bist, ddr_pxi1, _, _, _, _, _), 1458 [42] = PINGROUP(42, qup11, qup_l6, _, _, _, _, _, _, _), 1459 [43] = PINGROUP(43, qup11, ddr_pxi3, _, _, _, _, _, _, _), 1460 [44] = PINGROUP(44, qup12, ddr_pxi3, _, _, _, _, _, _, _), 1461 [45] = PINGROUP(45, qup12, ddr_pxi2, _, _, _, _, _, _, _), 1462 [46] = PINGROUP(46, qup12, mdp_vsync, _, _, _, _, _, _, _), 1463 [47] = PINGROUP(47, qup12, dp_hot, mdp_vsync, ddr_pxi2, _, _, _, _, _), 1464 [48] = PINGROUP(48, qup13, qspi2, sdc42, _, _, _, _, _, _), 1465 [49] = PINGROUP(49, qup13, qspi3, sdc43, _, _, _, _, _, _), 1466 [50] = PINGROUP(50, qup13, qspi_clk, sdc4_clk, _, _, _, _, _, _), 1467 [51] = PINGROUP(51, qup13, qspi_cs, sdc4_cmd, ddr_pxi0, _, _, _, _, _), 1468 [52] = PINGROUP(52, qup14, qspi0, sdc40, ddr_pxi0, _, _, _, _, _), 1469 [53] = PINGROUP(53, qup14, qspi1, sdc41, _, _, _, _, _, _), 1470 [54] = PINGROUP(54, qup14, qspi_cs, _, _, _, _, _, _, _), 1471 [55] = PINGROUP(55, qup14, atest_usb, _, _, _, _, _, _, _), 1472 [56] = PINGROUP(56, qup15, ibi_i3c, _, _, _, _, _, _, _), 1473 [57] = PINGROUP(57, qup15, ibi_i3c, _, _, _, _, _, _, _), 1474 [58] = PINGROUP(58, qup15, qup_l4, _, _, _, _, _, _, _), 1475 [59] = PINGROUP(59, qup15, qup_l5, _, _, _, _, _, _, _), 1476 [60] = PINGROUP(60, qup16, ibi_i3c, _, _, _, _, _, _, _), 1477 [61] = PINGROUP(61, qup16, ibi_i3c, _, _, _, _, _, _, _), 1478 [62] = PINGROUP(62, qup16, qup_l6, _, _, _, _, _, _, _), 1479 [63] = PINGROUP(63, qup16, qup_l4, _, _, _, _, _, _, _), 1480 [64] = PINGROUP(64, qup17, tb_trig, tgu_ch0, _, _, _, _, _, _), 1481 [65] = PINGROUP(65, qup17, tgu_ch1, _, _, _, _, _, _, _), 1482 [66] = PINGROUP(66, qup17, qup_l5, tgu_ch2, _, _, _, _, _, _), 1483 [67] = PINGROUP(67, qup17, qup_l6, tgu_ch3, _, _, _, _, _, _), 1484 [68] = PINGROUP(68, qup18, _, _, _, _, _, _, _, _), 1485 [69] = PINGROUP(69, qup18, _, _, _, _, _, _, _, _), 1486 [70] = PINGROUP(70, qup18, _, _, _, _, _, _, _, _), 1487 [71] = PINGROUP(71, qup18, cri_trng0, _, _, _, _, _, _, _), 1488 [72] = PINGROUP(72, qup19, cri_trng1, _, _, _, _, _, _, _), 1489 [73] = PINGROUP(73, qup19, prng_rosc, _, _, _, _, _, _, _), 1490 [74] = PINGROUP(74, qup19, _, _, _, _, _, _, _, _), 1491 [75] = PINGROUP(75, qup19, prng_rosc, _, _, _, _, _, _, _), 1492 [76] = PINGROUP(76, qup20, phase_flag, tmess_prng3, _, _, _, _, _, _), 1493 [77] = PINGROUP(77, qup20, phase_flag, tmess_prng2, _, _, _, _, _, _), 1494 [78] = PINGROUP(78, qup20, phase_flag, _, _, _, _, _, _, _), 1495 [79] = PINGROUP(79, qup20, phase_flag, tmess_prng1, _, _, _, _, _, _), 1496 [80] = PINGROUP(80, qup21, qdss_cti, phase_flag, tmess_prng0, _, _, _, _, _), 1497 [81] = PINGROUP(81, qup21, qdss_cti, phase_flag, prng_rosc, _, _, _, _, _), 1498 [82] = PINGROUP(82, qup21, qdss_cti, phase_flag, _, _, _, _, _, _), 1499 [83] = PINGROUP(83, qup21, qdss_cti, phase_flag, prng_rosc, _, _, _, _, _), 1500 [84] = PINGROUP(84, qup5, qdss_cti, _, _, _, _, _, _, _), 1501 [85] = PINGROUP(85, qup5, qdss_cti, _, _, _, _, _, _, _), 1502 [86] = PINGROUP(86, mdp_vsync, mdp_vsync0, mdp_vsync1, gcc_gp1, atest_char, _, _, _, _), 1503 [87] = PINGROUP(87, mdp_vsync, mdp_vsync2, mdp_vsync3, gcc_gp2, atest_char, _, _, _, _), 1504 [88] = PINGROUP(88, mdp_vsync, gcc_gp3, atest_char, _, _, _, _, _, _), 1505 [89] = PINGROUP(89, vfr_0, atest_char, _, _, _, _, _, _, _), 1506 [90] = PINGROUP(90, usb2phy_ac, atest_char, _, _, _, _, _, _, _), 1507 [91] = PINGROUP(91, usb_phy, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _), 1508 [92] = PINGROUP(92, phase_flag, _, _, _, _, _, _, _, _), 1509 [93] = PINGROUP(93, sd_write, qdss_cti, phase_flag, _, _, _, _, _, _), 1510 [94] = PINGROUP(94, cmu_rng, phase_flag, _, _, _, _, _, _, _), 1511 [95] = PINGROUP(95, pcie0_clkreqn, cmu_rng, phase_flag, _, _, _, _, _, _), 1512 [96] = PINGROUP(96, cmu_rng, phase_flag, _, _, _, _, _, _, _), 1513 [97] = PINGROUP(97, cmu_rng, phase_flag, _, _, _, _, _, _, _), 1514 [98] = PINGROUP(98, pcie1_clkreqn, phase_flag, _, _, _, _, _, _, _), 1515 [99] = PINGROUP(99, phase_flag, cri_trng, _, _, _, _, _, _, _), 1516 [100] = PINGROUP(100, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1517 [101] = PINGROUP(101, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1518 [102] = PINGROUP(102, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1519 [103] = PINGROUP(103, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1520 [104] = PINGROUP(104, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1521 [105] = PINGROUP(105, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1522 [106] = PINGROUP(106, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 1523 [107] = PINGROUP(107, cam_mclk, qdss_gpio, pll_clk, _, _, _, _, _, _), 1524 [108] = PINGROUP(108, aon_cam, _, _, _, _, _, _, _, _), 1525 [109] = PINGROUP(109, cci_async, _, _, _, _, _, _, _, _), 1526 [110] = PINGROUP(110, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1527 [111] = PINGROUP(111, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1528 [112] = PINGROUP(112, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1529 [113] = PINGROUP(113, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1530 [114] = PINGROUP(114, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1531 [115] = PINGROUP(115, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), 1532 [116] = PINGROUP(116, cci_timer, _, _, _, _, _, _, _, _), 1533 [117] = PINGROUP(117, cci_timer, qdss_gpio, _, _, _, _, _, _, _), 1534 [118] = PINGROUP(118, cci_timer, qdss_gpio, _, _, _, _, _, _, _), 1535 [119] = PINGROUP(119, cci_timer, cci_async, qdss_gpio, _, _, _, _, _, _), 1536 [120] = PINGROUP(120, cci_timer, cci_async, qdss_gpio, _, _, _, _, _, _), 1537 [121] = PINGROUP(121, mi2s2_sck, _, _, _, _, _, _, _, _), 1538 [122] = PINGROUP(122, mi2s2_data0, _, _, _, _, _, _, _, _), 1539 [123] = PINGROUP(123, mi2s2_ws, _, _, _, _, _, _, _, _), 1540 [124] = PINGROUP(124, mi2s2_data1, sec_mi2s, audio_ref, _, _, _, _, _, _), 1541 [125] = PINGROUP(125, pri_mi2s, _, _, _, _, _, _, _, _), 1542 [126] = PINGROUP(126, mi2s0_sck, _, _, _, _, _, _, _, _), 1543 [127] = PINGROUP(127, mi2s0_data0, _, _, _, _, _, _, _, _), 1544 [128] = PINGROUP(128, mi2s0_data1, _, _, _, _, _, _, _, _), 1545 [129] = PINGROUP(129, mi2s0_ws, _, _, _, _, _, _, _, _), 1546 [130] = PINGROUP(130, uim0_data, _, _, _, _, _, _, _, _), 1547 [131] = PINGROUP(131, uim0_clk, _, _, _, _, _, _, _, _), 1548 [132] = PINGROUP(132, uim0_reset, _, _, _, _, _, _, _, _), 1549 [133] = PINGROUP(133, uim0_present, _, _, _, _, _, _, _, _), 1550 [134] = PINGROUP(134, uim1_data, gcc_gp1, _, _, _, _, _, _, _), 1551 [135] = PINGROUP(135, uim1_clk, gcc_gp2, _, _, _, _, _, _, _), 1552 [136] = PINGROUP(136, uim1_reset, gcc_gp3, _, _, _, _, _, _, _), 1553 [137] = PINGROUP(137, uim1_present, tb_trig, _, _, _, _, _, _, _), 1554 [138] = PINGROUP(138, _, mss_grfc0, _, _, _, _, _, _, _), 1555 [139] = PINGROUP(139, _, mss_grfc1, _, _, _, _, _, _, _), 1556 [140] = PINGROUP(140, _, mss_grfc2, _, _, _, _, _, _, _), 1557 [141] = PINGROUP(141, _, mss_grfc3, _, _, _, _, _, _, _), 1558 [142] = PINGROUP(142, _, mss_grfc4, _, _, _, _, _, _, _), 1559 [143] = PINGROUP(143, _, mss_grfc5, _, _, _, _, _, _, _), 1560 [144] = PINGROUP(144, _, mss_grfc6, _, _, _, _, _, _, _), 1561 [145] = PINGROUP(145, _, mss_grfc7, _, _, _, _, _, _, _), 1562 [146] = PINGROUP(146, _, mss_grfc8, _, _, _, _, _, _, _), 1563 [147] = PINGROUP(147, _, mss_grfc9, _, _, _, _, _, _, _), 1564 [148] = PINGROUP(148, coex_uart1, atest_usb, _, _, _, _, _, _, _), 1565 [149] = PINGROUP(149, coex_uart1, atest_usb, _, _, _, _, _, _, _), 1566 [150] = PINGROUP(150, coex_uart2, mss_grfc10, _, _, _, _, _, _, _), 1567 [151] = PINGROUP(151, coex_uart2, mss_grfc11, _, _, _, _, _, _, _), 1568 [152] = PINGROUP(152, mss_grfc12, _, _, _, _, _, _, _, _), 1569 [153] = PINGROUP(153, mss_grfc0, nav, _, _, _, _, _, _, _), 1570 [154] = PINGROUP(154, nav, _, _, _, _, _, _, _, _), 1571 [155] = PINGROUP(155, nav, vfr_1, _, _, _, _, _, _, _), 1572 [156] = PINGROUP(156, qlink0_request, _, _, _, _, _, _, _, _), 1573 [157] = PINGROUP(157, qlink0_enable, _, _, _, _, _, _, _, _), 1574 [158] = PINGROUP(158, qlink0_wmss, _, _, _, _, _, _, _, _), 1575 [159] = PINGROUP(159, qlink1_request, _, _, _, _, _, _, _, _), 1576 [160] = PINGROUP(160, qlink1_enable, _, _, _, _, _, _, _, _), 1577 [161] = PINGROUP(161, qlink1_wmss, _, _, _, _, _, _, _, _), 1578 [162] = PINGROUP(162, qlink2_request, _, _, _, _, _, _, _, _), 1579 [163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _), 1580 [164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _), 1581 [165] = PINGROUP(165, _, _, _, _, _, _, _, _, egpio), 1582 [166] = PINGROUP(166, _, _, _, _, _, _, _, _, egpio), 1583 [167] = PINGROUP(167, _, _, _, _, _, _, _, _, egpio), 1584 [168] = PINGROUP(168, _, _, _, _, _, _, _, _, egpio), 1585 [169] = PINGROUP(169, _, _, _, _, _, _, _, _, egpio), 1586 [170] = PINGROUP(170, _, _, _, _, _, _, _, _, egpio), 1587 [171] = PINGROUP(171, _, _, _, _, _, _, _, _, egpio), 1588 [172] = PINGROUP(172, _, _, _, _, _, _, _, _, egpio), 1589 [173] = PINGROUP(173, _, _, _, _, _, _, _, _, egpio), 1590 [174] = PINGROUP(174, _, _, _, _, _, _, _, _, egpio), 1591 [175] = PINGROUP(175, _, _, _, _, _, _, _, _, egpio), 1592 [176] = PINGROUP(176, _, _, _, _, _, _, _, _, egpio), 1593 [177] = PINGROUP(177, _, _, _, _, _, _, _, _, egpio), 1594 [178] = PINGROUP(178, _, _, _, _, _, _, _, _, egpio), 1595 [179] = PINGROUP(179, _, _, _, _, _, _, _, _, egpio), 1596 [180] = PINGROUP(180, _, _, _, _, _, _, _, _, egpio), 1597 [181] = PINGROUP(181, _, _, _, _, _, _, _, _, egpio), 1598 [182] = PINGROUP(182, _, _, _, _, _, _, _, _, egpio), 1599 [183] = PINGROUP(183, _, _, _, _, _, _, _, _, egpio), 1600 [184] = PINGROUP(184, _, _, _, _, _, _, _, _, egpio), 1601 [185] = PINGROUP(185, _, _, _, _, _, _, _, _, egpio), 1602 [186] = PINGROUP(186, _, _, _, _, _, _, _, _, egpio), 1603 [187] = PINGROUP(187, _, _, _, _, _, _, _, _, egpio), 1604 [188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, egpio), 1605 [189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, egpio), 1606 [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, egpio), 1607 [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, egpio), 1608 [192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, egpio), 1609 [193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, egpio), 1610 [194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, egpio), 1611 [195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, egpio), 1612 [196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, egpio), 1613 [197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, egpio), 1614 [198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, egpio), 1615 [199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, egpio), 1616 [200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, egpio), 1617 [201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, egpio), 1618 [202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, egpio), 1619 [203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, egpio), 1620 [204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, egpio), 1621 [205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, egpio), 1622 [206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, egpio), 1623 [207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, egpio), 1624 [208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, egpio), 1625 [209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, egpio), 1626 [210] = UFS_RESET(ufs_reset, 0xde000), 1627 [211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6), 1628 [212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3), 1629 [213] = SDC_QDSD_PINGROUP(sdc2_data, 0xd6000, 9, 0), 1630}; 1631 1632static const struct msm_gpio_wakeirq_map sm8450_pdc_map[] = { 1633 { 2, 70 }, { 3, 77 }, { 7, 52 }, { 8, 108 }, { 10, 128 }, { 11, 53 }, 1634 { 12, 129 }, { 13, 130 }, { 14, 131 }, { 15, 67 }, { 19, 69 }, { 21, 132 }, 1635 { 23, 54 }, { 26, 56 }, { 27, 71 }, { 28, 57 }, { 31, 55 }, { 32, 58 }, 1636 { 34, 72 }, { 35, 43 }, { 36, 78 }, { 38, 79 }, { 39, 62 }, { 40, 80 }, 1637 { 41, 133 }, { 43, 81 }, { 44, 87 }, { 45, 134 }, { 46, 66 }, { 47, 63 }, 1638 { 50, 88 }, { 51, 89 }, { 55, 90 }, { 56, 59 }, { 59, 82 }, { 60, 60 }, 1639 { 62, 135 }, { 63, 91 }, { 66, 136 }, { 67, 44 }, { 69, 137 }, { 71, 97 }, 1640 { 75, 73 }, { 79, 74 }, { 80, 96 }, { 81, 98 }, { 82, 45 }, { 83, 99 }, 1641 { 84, 94 }, { 85, 100 }, { 86, 101 }, { 87, 102 }, { 88, 92 }, { 89, 83 }, 1642 { 90, 84 }, { 91, 85 }, { 92, 46 }, { 95, 103 }, { 96, 104 }, { 98, 105 }, 1643 { 99, 106 }, { 115, 95 }, { 116, 76 }, { 117, 75 }, { 118, 86 }, { 119, 93 }, 1644 { 133, 47 }, { 137, 42 }, { 148, 61 }, { 150, 68 }, { 153, 65 }, { 154, 48 }, 1645 { 155, 49 }, { 156, 64 }, { 159, 50 }, { 162, 51 }, { 166, 111 }, { 169, 114 }, 1646 { 171, 115 }, { 172, 116 }, { 174, 117 }, { 176, 107 }, { 181, 109 }, 1647 { 182, 110 }, { 185, 112 }, { 187, 113 }, { 188, 118 }, { 190, 122 }, 1648 { 192, 123 }, { 195, 124 }, { 201, 119 }, { 203, 120 }, { 205, 121 }, 1649}; 1650 1651static const struct msm_pinctrl_soc_data sm8450_tlmm = { 1652 .pins = sm8450_pins, 1653 .npins = ARRAY_SIZE(sm8450_pins), 1654 .functions = sm8450_functions, 1655 .nfunctions = ARRAY_SIZE(sm8450_functions), 1656 .groups = sm8450_groups, 1657 .ngroups = ARRAY_SIZE(sm8450_groups), 1658 .ngpios = 211, 1659 .wakeirq_map = sm8450_pdc_map, 1660 .nwakeirq_map = ARRAY_SIZE(sm8450_pdc_map), 1661 .egpio_func = 9, 1662}; 1663 1664static int sm8450_tlmm_probe(struct platform_device *pdev) 1665{ 1666 return msm_pinctrl_probe(pdev, &sm8450_tlmm); 1667} 1668 1669static const struct of_device_id sm8450_tlmm_of_match[] = { 1670 { .compatible = "qcom,sm8450-tlmm", }, 1671 { }, 1672}; 1673 1674static struct platform_driver sm8450_tlmm_driver = { 1675 .driver = { 1676 .name = "sm8450-tlmm", 1677 .of_match_table = sm8450_tlmm_of_match, 1678 }, 1679 .probe = sm8450_tlmm_probe, 1680 .remove = msm_pinctrl_remove, 1681}; 1682 1683static int __init sm8450_tlmm_init(void) 1684{ 1685 return platform_driver_register(&sm8450_tlmm_driver); 1686} 1687arch_initcall(sm8450_tlmm_init); 1688 1689static void __exit sm8450_tlmm_exit(void) 1690{ 1691 platform_driver_unregister(&sm8450_tlmm_driver); 1692} 1693module_exit(sm8450_tlmm_exit); 1694 1695MODULE_DESCRIPTION("QTI SM8450 TLMM driver"); 1696MODULE_LICENSE("GPL v2"); 1697MODULE_DEVICE_TABLE(of, sm8450_tlmm_of_match); 1698