1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <linux/module.h> 7#include <linux/of.h> 8#include <linux/platform_device.h> 9 10#include "pinctrl-msm.h" 11 12#define REG_BASE 0x0 13#define REG_SIZE 0x1000 14#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 15 { \ 16 .grp = PINCTRL_PINGROUP("gpio" #id, \ 17 gpio##id##_pins, \ 18 ARRAY_SIZE(gpio##id##_pins)), \ 19 .funcs = (int[]){ \ 20 msm_mux_gpio, /* gpio mode */ \ 21 msm_mux_##f1, \ 22 msm_mux_##f2, \ 23 msm_mux_##f3, \ 24 msm_mux_##f4, \ 25 msm_mux_##f5, \ 26 msm_mux_##f6, \ 27 msm_mux_##f7, \ 28 msm_mux_##f8, \ 29 msm_mux_##f9 \ 30 }, \ 31 .nfuncs = 10, \ 32 .ctl_reg = REG_BASE + REG_SIZE * id, \ 33 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 34 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 35 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 36 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 37 .mux_bit = 2, \ 38 .pull_bit = 0, \ 39 .drv_bit = 6, \ 40 .oe_bit = 9, \ 41 .in_bit = 0, \ 42 .out_bit = 1, \ 43 .intr_enable_bit = 0, \ 44 .intr_status_bit = 0, \ 45 .intr_target_bit = 5, \ 46 .intr_target_kpss_val = 3, \ 47 .intr_raw_status_bit = 4, \ 48 .intr_polarity_bit = 1, \ 49 .intr_detection_bit = 2, \ 50 .intr_detection_width = 2, \ 51 } 52 53#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 54 { \ 55 .grp = PINCTRL_PINGROUP(#pg_name, \ 56 pg_name##_pins, \ 57 ARRAY_SIZE(pg_name##_pins)), \ 58 .ctl_reg = ctl, \ 59 .io_reg = 0, \ 60 .intr_cfg_reg = 0, \ 61 .intr_status_reg = 0, \ 62 .intr_target_reg = 0, \ 63 .mux_bit = -1, \ 64 .pull_bit = pull, \ 65 .drv_bit = drv, \ 66 .oe_bit = -1, \ 67 .in_bit = -1, \ 68 .out_bit = -1, \ 69 .intr_enable_bit = -1, \ 70 .intr_status_bit = -1, \ 71 .intr_target_bit = -1, \ 72 .intr_raw_status_bit = -1, \ 73 .intr_polarity_bit = -1, \ 74 .intr_detection_bit = -1, \ 75 .intr_detection_width = -1, \ 76 } 77 78#define UFS_RESET(pg_name, offset) \ 79 { \ 80 .grp = PINCTRL_PINGROUP(#pg_name, \ 81 pg_name##_pins, \ 82 ARRAY_SIZE(pg_name##_pins)), \ 83 .ctl_reg = offset, \ 84 .io_reg = offset + 0x4, \ 85 .intr_cfg_reg = 0, \ 86 .intr_status_reg = 0, \ 87 .intr_target_reg = 0, \ 88 .mux_bit = -1, \ 89 .pull_bit = 3, \ 90 .drv_bit = 0, \ 91 .oe_bit = -1, \ 92 .in_bit = -1, \ 93 .out_bit = 0, \ 94 .intr_enable_bit = -1, \ 95 .intr_status_bit = -1, \ 96 .intr_target_bit = -1, \ 97 .intr_raw_status_bit = -1, \ 98 .intr_polarity_bit = -1, \ 99 .intr_detection_bit = -1, \ 100 .intr_detection_width = -1, \ 101 } 102 103static const struct pinctrl_pin_desc sdx65_pins[] = { 104 PINCTRL_PIN(0, "GPIO_0"), 105 PINCTRL_PIN(1, "GPIO_1"), 106 PINCTRL_PIN(2, "GPIO_2"), 107 PINCTRL_PIN(3, "GPIO_3"), 108 PINCTRL_PIN(4, "GPIO_4"), 109 PINCTRL_PIN(5, "GPIO_5"), 110 PINCTRL_PIN(6, "GPIO_6"), 111 PINCTRL_PIN(7, "GPIO_7"), 112 PINCTRL_PIN(8, "GPIO_8"), 113 PINCTRL_PIN(9, "GPIO_9"), 114 PINCTRL_PIN(10, "GPIO_10"), 115 PINCTRL_PIN(11, "GPIO_11"), 116 PINCTRL_PIN(12, "GPIO_12"), 117 PINCTRL_PIN(13, "GPIO_13"), 118 PINCTRL_PIN(14, "GPIO_14"), 119 PINCTRL_PIN(15, "GPIO_15"), 120 PINCTRL_PIN(16, "GPIO_16"), 121 PINCTRL_PIN(17, "GPIO_17"), 122 PINCTRL_PIN(18, "GPIO_18"), 123 PINCTRL_PIN(19, "GPIO_19"), 124 PINCTRL_PIN(20, "GPIO_20"), 125 PINCTRL_PIN(21, "GPIO_21"), 126 PINCTRL_PIN(22, "GPIO_22"), 127 PINCTRL_PIN(23, "GPIO_23"), 128 PINCTRL_PIN(24, "GPIO_24"), 129 PINCTRL_PIN(25, "GPIO_25"), 130 PINCTRL_PIN(26, "GPIO_26"), 131 PINCTRL_PIN(27, "GPIO_27"), 132 PINCTRL_PIN(28, "GPIO_28"), 133 PINCTRL_PIN(29, "GPIO_29"), 134 PINCTRL_PIN(30, "GPIO_30"), 135 PINCTRL_PIN(31, "GPIO_31"), 136 PINCTRL_PIN(32, "GPIO_32"), 137 PINCTRL_PIN(33, "GPIO_33"), 138 PINCTRL_PIN(34, "GPIO_34"), 139 PINCTRL_PIN(35, "GPIO_35"), 140 PINCTRL_PIN(36, "GPIO_36"), 141 PINCTRL_PIN(37, "GPIO_37"), 142 PINCTRL_PIN(38, "GPIO_38"), 143 PINCTRL_PIN(39, "GPIO_39"), 144 PINCTRL_PIN(40, "GPIO_40"), 145 PINCTRL_PIN(41, "GPIO_41"), 146 PINCTRL_PIN(42, "GPIO_42"), 147 PINCTRL_PIN(43, "GPIO_43"), 148 PINCTRL_PIN(44, "GPIO_44"), 149 PINCTRL_PIN(45, "GPIO_45"), 150 PINCTRL_PIN(46, "GPIO_46"), 151 PINCTRL_PIN(47, "GPIO_47"), 152 PINCTRL_PIN(48, "GPIO_48"), 153 PINCTRL_PIN(49, "GPIO_49"), 154 PINCTRL_PIN(50, "GPIO_50"), 155 PINCTRL_PIN(51, "GPIO_51"), 156 PINCTRL_PIN(52, "GPIO_52"), 157 PINCTRL_PIN(53, "GPIO_53"), 158 PINCTRL_PIN(54, "GPIO_54"), 159 PINCTRL_PIN(55, "GPIO_55"), 160 PINCTRL_PIN(56, "GPIO_56"), 161 PINCTRL_PIN(57, "GPIO_57"), 162 PINCTRL_PIN(58, "GPIO_58"), 163 PINCTRL_PIN(59, "GPIO_59"), 164 PINCTRL_PIN(60, "GPIO_60"), 165 PINCTRL_PIN(61, "GPIO_61"), 166 PINCTRL_PIN(62, "GPIO_62"), 167 PINCTRL_PIN(63, "GPIO_63"), 168 PINCTRL_PIN(64, "GPIO_64"), 169 PINCTRL_PIN(65, "GPIO_65"), 170 PINCTRL_PIN(66, "GPIO_66"), 171 PINCTRL_PIN(67, "GPIO_67"), 172 PINCTRL_PIN(68, "GPIO_68"), 173 PINCTRL_PIN(69, "GPIO_69"), 174 PINCTRL_PIN(70, "GPIO_70"), 175 PINCTRL_PIN(71, "GPIO_71"), 176 PINCTRL_PIN(72, "GPIO_72"), 177 PINCTRL_PIN(73, "GPIO_73"), 178 PINCTRL_PIN(74, "GPIO_74"), 179 PINCTRL_PIN(75, "GPIO_75"), 180 PINCTRL_PIN(76, "GPIO_76"), 181 PINCTRL_PIN(77, "GPIO_77"), 182 PINCTRL_PIN(78, "GPIO_78"), 183 PINCTRL_PIN(79, "GPIO_79"), 184 PINCTRL_PIN(80, "GPIO_80"), 185 PINCTRL_PIN(81, "GPIO_81"), 186 PINCTRL_PIN(82, "GPIO_82"), 187 PINCTRL_PIN(83, "GPIO_83"), 188 PINCTRL_PIN(84, "GPIO_84"), 189 PINCTRL_PIN(85, "GPIO_85"), 190 PINCTRL_PIN(86, "GPIO_86"), 191 PINCTRL_PIN(87, "GPIO_87"), 192 PINCTRL_PIN(88, "GPIO_88"), 193 PINCTRL_PIN(89, "GPIO_89"), 194 PINCTRL_PIN(90, "GPIO_90"), 195 PINCTRL_PIN(91, "GPIO_91"), 196 PINCTRL_PIN(92, "GPIO_92"), 197 PINCTRL_PIN(93, "GPIO_93"), 198 PINCTRL_PIN(94, "GPIO_94"), 199 PINCTRL_PIN(95, "GPIO_95"), 200 PINCTRL_PIN(96, "GPIO_96"), 201 PINCTRL_PIN(97, "GPIO_97"), 202 PINCTRL_PIN(98, "GPIO_98"), 203 PINCTRL_PIN(99, "GPIO_99"), 204 PINCTRL_PIN(100, "GPIO_100"), 205 PINCTRL_PIN(101, "GPIO_101"), 206 PINCTRL_PIN(102, "GPIO_102"), 207 PINCTRL_PIN(103, "GPIO_103"), 208 PINCTRL_PIN(104, "GPIO_104"), 209 PINCTRL_PIN(105, "GPIO_105"), 210 PINCTRL_PIN(106, "GPIO_106"), 211 PINCTRL_PIN(107, "GPIO_107"), 212 PINCTRL_PIN(108, "UFS_RESET"), 213 PINCTRL_PIN(109, "SDC1_RCLK"), 214 PINCTRL_PIN(110, "SDC1_CLK"), 215 PINCTRL_PIN(111, "SDC1_CMD"), 216 PINCTRL_PIN(112, "SDC1_DATA"), 217}; 218 219#define DECLARE_MSM_GPIO_PINS(pin) \ 220 static const unsigned int gpio##pin##_pins[] = { pin } 221DECLARE_MSM_GPIO_PINS(0); 222DECLARE_MSM_GPIO_PINS(1); 223DECLARE_MSM_GPIO_PINS(2); 224DECLARE_MSM_GPIO_PINS(3); 225DECLARE_MSM_GPIO_PINS(4); 226DECLARE_MSM_GPIO_PINS(5); 227DECLARE_MSM_GPIO_PINS(6); 228DECLARE_MSM_GPIO_PINS(7); 229DECLARE_MSM_GPIO_PINS(8); 230DECLARE_MSM_GPIO_PINS(9); 231DECLARE_MSM_GPIO_PINS(10); 232DECLARE_MSM_GPIO_PINS(11); 233DECLARE_MSM_GPIO_PINS(12); 234DECLARE_MSM_GPIO_PINS(13); 235DECLARE_MSM_GPIO_PINS(14); 236DECLARE_MSM_GPIO_PINS(15); 237DECLARE_MSM_GPIO_PINS(16); 238DECLARE_MSM_GPIO_PINS(17); 239DECLARE_MSM_GPIO_PINS(18); 240DECLARE_MSM_GPIO_PINS(19); 241DECLARE_MSM_GPIO_PINS(20); 242DECLARE_MSM_GPIO_PINS(21); 243DECLARE_MSM_GPIO_PINS(22); 244DECLARE_MSM_GPIO_PINS(23); 245DECLARE_MSM_GPIO_PINS(24); 246DECLARE_MSM_GPIO_PINS(25); 247DECLARE_MSM_GPIO_PINS(26); 248DECLARE_MSM_GPIO_PINS(27); 249DECLARE_MSM_GPIO_PINS(28); 250DECLARE_MSM_GPIO_PINS(29); 251DECLARE_MSM_GPIO_PINS(30); 252DECLARE_MSM_GPIO_PINS(31); 253DECLARE_MSM_GPIO_PINS(32); 254DECLARE_MSM_GPIO_PINS(33); 255DECLARE_MSM_GPIO_PINS(34); 256DECLARE_MSM_GPIO_PINS(35); 257DECLARE_MSM_GPIO_PINS(36); 258DECLARE_MSM_GPIO_PINS(37); 259DECLARE_MSM_GPIO_PINS(38); 260DECLARE_MSM_GPIO_PINS(39); 261DECLARE_MSM_GPIO_PINS(40); 262DECLARE_MSM_GPIO_PINS(41); 263DECLARE_MSM_GPIO_PINS(42); 264DECLARE_MSM_GPIO_PINS(43); 265DECLARE_MSM_GPIO_PINS(44); 266DECLARE_MSM_GPIO_PINS(45); 267DECLARE_MSM_GPIO_PINS(46); 268DECLARE_MSM_GPIO_PINS(47); 269DECLARE_MSM_GPIO_PINS(48); 270DECLARE_MSM_GPIO_PINS(49); 271DECLARE_MSM_GPIO_PINS(50); 272DECLARE_MSM_GPIO_PINS(51); 273DECLARE_MSM_GPIO_PINS(52); 274DECLARE_MSM_GPIO_PINS(53); 275DECLARE_MSM_GPIO_PINS(54); 276DECLARE_MSM_GPIO_PINS(55); 277DECLARE_MSM_GPIO_PINS(56); 278DECLARE_MSM_GPIO_PINS(57); 279DECLARE_MSM_GPIO_PINS(58); 280DECLARE_MSM_GPIO_PINS(59); 281DECLARE_MSM_GPIO_PINS(60); 282DECLARE_MSM_GPIO_PINS(61); 283DECLARE_MSM_GPIO_PINS(62); 284DECLARE_MSM_GPIO_PINS(63); 285DECLARE_MSM_GPIO_PINS(64); 286DECLARE_MSM_GPIO_PINS(65); 287DECLARE_MSM_GPIO_PINS(66); 288DECLARE_MSM_GPIO_PINS(67); 289DECLARE_MSM_GPIO_PINS(68); 290DECLARE_MSM_GPIO_PINS(69); 291DECLARE_MSM_GPIO_PINS(70); 292DECLARE_MSM_GPIO_PINS(71); 293DECLARE_MSM_GPIO_PINS(72); 294DECLARE_MSM_GPIO_PINS(73); 295DECLARE_MSM_GPIO_PINS(74); 296DECLARE_MSM_GPIO_PINS(75); 297DECLARE_MSM_GPIO_PINS(76); 298DECLARE_MSM_GPIO_PINS(77); 299DECLARE_MSM_GPIO_PINS(78); 300DECLARE_MSM_GPIO_PINS(79); 301DECLARE_MSM_GPIO_PINS(80); 302DECLARE_MSM_GPIO_PINS(81); 303DECLARE_MSM_GPIO_PINS(82); 304DECLARE_MSM_GPIO_PINS(83); 305DECLARE_MSM_GPIO_PINS(84); 306DECLARE_MSM_GPIO_PINS(85); 307DECLARE_MSM_GPIO_PINS(86); 308DECLARE_MSM_GPIO_PINS(87); 309DECLARE_MSM_GPIO_PINS(88); 310DECLARE_MSM_GPIO_PINS(89); 311DECLARE_MSM_GPIO_PINS(90); 312DECLARE_MSM_GPIO_PINS(91); 313DECLARE_MSM_GPIO_PINS(92); 314DECLARE_MSM_GPIO_PINS(93); 315DECLARE_MSM_GPIO_PINS(94); 316DECLARE_MSM_GPIO_PINS(95); 317DECLARE_MSM_GPIO_PINS(96); 318DECLARE_MSM_GPIO_PINS(97); 319DECLARE_MSM_GPIO_PINS(98); 320DECLARE_MSM_GPIO_PINS(99); 321DECLARE_MSM_GPIO_PINS(100); 322DECLARE_MSM_GPIO_PINS(101); 323DECLARE_MSM_GPIO_PINS(102); 324DECLARE_MSM_GPIO_PINS(103); 325DECLARE_MSM_GPIO_PINS(104); 326DECLARE_MSM_GPIO_PINS(105); 327DECLARE_MSM_GPIO_PINS(106); 328DECLARE_MSM_GPIO_PINS(107); 329 330static const unsigned int ufs_reset_pins[] = { 108 }; 331static const unsigned int sdc1_rclk_pins[] = { 109 }; 332static const unsigned int sdc1_clk_pins[] = { 110 }; 333static const unsigned int sdc1_cmd_pins[] = { 111 }; 334static const unsigned int sdc1_data_pins[] = { 112 }; 335 336enum sdx65_functions { 337 msm_mux_qlink0_wmss, 338 msm_mux_adsp_ext, 339 msm_mux_atest_char, 340 msm_mux_atest_char0, 341 msm_mux_atest_char1, 342 msm_mux_atest_char2, 343 msm_mux_atest_char3, 344 msm_mux_audio_ref, 345 msm_mux_bimc_dte0, 346 msm_mux_bimc_dte1, 347 msm_mux_blsp_i2c1, 348 msm_mux_blsp_i2c2, 349 msm_mux_blsp_i2c3, 350 msm_mux_blsp_i2c4, 351 msm_mux_blsp_spi1, 352 msm_mux_blsp_spi2, 353 msm_mux_blsp_spi3, 354 msm_mux_blsp_spi4, 355 msm_mux_blsp_uart1, 356 msm_mux_blsp_uart2, 357 msm_mux_blsp_uart3, 358 msm_mux_blsp_uart4, 359 msm_mux_char_exec, 360 msm_mux_coex_uart, 361 msm_mux_coex_uart2, 362 msm_mux_cri_trng, 363 msm_mux_cri_trng0, 364 msm_mux_cri_trng1, 365 msm_mux_dbg_out, 366 msm_mux_ddr_bist, 367 msm_mux_ddr_pxi0, 368 msm_mux_ebi0_wrcdc, 369 msm_mux_ebi2_a, 370 msm_mux_ebi2_lcd, 371 msm_mux_ext_dbg, 372 msm_mux_gcc_gp1, 373 msm_mux_gcc_gp2, 374 msm_mux_gcc_gp3, 375 msm_mux_gcc_plltest, 376 msm_mux_gpio, 377 msm_mux_i2s_mclk, 378 msm_mux_jitter_bist, 379 msm_mux_ldo_en, 380 msm_mux_ldo_update, 381 msm_mux_m_voc, 382 msm_mux_mgpi_clk, 383 msm_mux_native_char, 384 msm_mux_native_tsens, 385 msm_mux_native_tsense, 386 msm_mux_nav_gpio, 387 msm_mux_pa_indicator, 388 msm_mux_pci_e, 389 msm_mux_pcie_clkreq, 390 msm_mux_pll_bist, 391 msm_mux_pll_ref, 392 msm_mux_pri_mi2s, 393 msm_mux_pri_mi2s_ws, 394 msm_mux_prng_rosc, 395 msm_mux_qdss_cti, 396 msm_mux_qdss_gpio, 397 msm_mux_qlink0_en, 398 msm_mux_qlink0_req, 399 msm_mux_qlink1_en, 400 msm_mux_qlink1_req, 401 msm_mux_qlink1_wmss, 402 msm_mux_qlink2_en, 403 msm_mux_qlink2_req, 404 msm_mux_qlink2_wmss, 405 msm_mux_sdc1_tb, 406 msm_mux_sec_mi2s, 407 msm_mux_spmi_coex, 408 msm_mux_spmi_vgi, 409 msm_mux_tgu_ch0, 410 msm_mux_uim1_clk, 411 msm_mux_uim1_data, 412 msm_mux_uim1_present, 413 msm_mux_uim1_reset, 414 msm_mux_uim2_clk, 415 msm_mux_uim2_data, 416 msm_mux_uim2_present, 417 msm_mux_uim2_reset, 418 msm_mux_usb2phy_ac, 419 msm_mux_vsense_trigger, 420 msm_mux__, 421}; 422 423static const char * const gpio_groups[] = { 424 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 425 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 426 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 427 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 428 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 429 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 430 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 431 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 432 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 433 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 434 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 435 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 436 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 437 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 438 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 439 "gpio105", "gpio106", "gpio107", 440}; 441static const char * const uim2_data_groups[] = { 442 "gpio0", 443}; 444static const char * const blsp_uart1_groups[] = { 445 "gpio0", "gpio1", "gpio2", "gpio3", "gpio48", "gpio49", "gpio80", 446 "gpio81", 447}; 448static const char * const ebi0_wrcdc_groups[] = { 449 "gpio0", "gpio2", 450}; 451static const char * const uim2_present_groups[] = { 452 "gpio1", 453}; 454static const char * const uim2_reset_groups[] = { 455 "gpio2", 456}; 457static const char * const blsp_i2c1_groups[] = { 458 "gpio2", "gpio3", "gpio82", "gpio83", 459}; 460static const char * const uim2_clk_groups[] = { 461 "gpio3", 462}; 463static const char * const blsp_spi2_groups[] = { 464 "gpio4", "gpio5", "gpio6", "gpio7", "gpio23", "gpio47", "gpio62", 465}; 466static const char * const blsp_uart2_groups[] = { 467 "gpio4", "gpio5", "gpio6", "gpio7", "gpio63", "gpio64", "gpio65", 468 "gpio66", 469}; 470static const char * const blsp_i2c2_groups[] = { 471 "gpio6", "gpio7", "gpio65", "gpio66", 472}; 473static const char * const char_exec_groups[] = { 474 "gpio6", "gpio7", 475}; 476static const char * const qdss_gpio_groups[] = { 477 "gpio4", "gpio5", "gpio6", "gpio7", "gpio12", "gpio13", 478 "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", 479 "gpio33", "gpio42", "gpio63", "gpio64", "gpio65", "gpio66", 480}; 481static const char * const blsp_spi3_groups[] = { 482 "gpio8", "gpio9", "gpio10", "gpio11", "gpio23", "gpio47", "gpio62", 483}; 484static const char * const blsp_uart3_groups[] = { 485 "gpio8", "gpio9", "gpio10", "gpio11", 486}; 487static const char * const ext_dbg_groups[] = { 488 "gpio8", "gpio9", "gpio10", "gpio11", 489}; 490static const char * const ldo_en_groups[] = { 491 "gpio8", 492}; 493static const char * const blsp_i2c3_groups[] = { 494 "gpio10", "gpio11", 495}; 496static const char * const gcc_gp3_groups[] = { 497 "gpio11", 498}; 499static const char * const pri_mi2s_ws_groups[] = { 500 "gpio12", 501}; 502static const char * const pri_mi2s_groups[] = { 503 "gpio13", "gpio14", "gpio15", 504}; 505static const char * const vsense_trigger_groups[] = { 506 "gpio13", 507}; 508static const char * const native_tsens_groups[] = { 509 "gpio14", 510}; 511static const char * const bimc_dte0_groups[] = { 512 "gpio14", "gpio59", 513}; 514static const char * const bimc_dte1_groups[] = { 515 "gpio15", "gpio61", 516}; 517static const char * const sec_mi2s_groups[] = { 518 "gpio16", "gpio17", "gpio18", "gpio19", 519}; 520static const char * const blsp_spi4_groups[] = { 521 "gpio16", "gpio17", "gpio18", "gpio19", "gpio23", "gpio47", "gpio62", 522}; 523static const char * const blsp_uart4_groups[] = { 524 "gpio16", "gpio17", "gpio18", "gpio19", "gpio22", "gpio23", "gpio48", 525 "gpio49", 526}; 527static const char * const qdss_cti_groups[] = { 528 "gpio16", "gpio16", "gpio17", "gpio17", "gpio54", "gpio54", "gpio55", 529 "gpio55", "gpio59", "gpio60", "gpio65", "gpio65", "gpio66", "gpio66", 530 "gpio94", "gpio94", "gpio95", "gpio95", 531}; 532static const char * const blsp_i2c4_groups[] = { 533 "gpio18", "gpio19", "gpio84", "gpio85", 534}; 535static const char * const gcc_gp1_groups[] = { 536 "gpio18", 537}; 538static const char * const jitter_bist_groups[] = { 539 "gpio19", 540}; 541static const char * const gcc_gp2_groups[] = { 542 "gpio19", 543}; 544static const char * const pll_bist_groups[] = { 545 "gpio22", 546}; 547static const char * const blsp_spi1_groups[] = { 548 "gpio23", "gpio47", "gpio62", "gpio80", "gpio81", "gpio82", "gpio83", 549}; 550static const char * const adsp_ext_groups[] = { 551 "gpio24", "gpio25", 552}; 553static const char * const qlink0_wmss_groups[] = { 554 "gpio28", 555}; 556static const char * const native_tsense_groups[] = { 557 "gpio29", "gpio72", 558}; 559static const char * const nav_gpio_groups[] = { 560 "gpio31", "gpio32", 561}; 562static const char * const pll_ref_groups[] = { 563 "gpio32", 564}; 565static const char * const pa_indicator_groups[] = { 566 "gpio33", 567}; 568static const char * const qlink0_en_groups[] = { 569 "gpio34", 570}; 571static const char * const qlink0_req_groups[] = { 572 "gpio35", 573}; 574static const char * const dbg_out_groups[] = { 575 "gpio35", 576}; 577static const char * const cri_trng_groups[] = { 578 "gpio36", 579}; 580static const char * const prng_rosc_groups[] = { 581 "gpio38", 582}; 583static const char * const cri_trng0_groups[] = { 584 "gpio40", 585}; 586static const char * const cri_trng1_groups[] = { 587 "gpio41", 588}; 589static const char * const coex_uart_groups[] = { 590 "gpio44", "gpio45", 591}; 592static const char * const ddr_pxi0_groups[] = { 593 "gpio45", "gpio46", 594}; 595static const char * const m_voc_groups[] = { 596 "gpio46", "gpio48", "gpio49", "gpio59", "gpio60", 597}; 598static const char * const ddr_bist_groups[] = { 599 "gpio46", "gpio47", "gpio48", "gpio49", 600}; 601static const char * const pci_e_groups[] = { 602 "gpio53", 603}; 604static const char * const tgu_ch0_groups[] = { 605 "gpio55", 606}; 607static const char * const pcie_clkreq_groups[] = { 608 "gpio56", 609}; 610static const char * const native_char_groups[] = { 611 "gpio26", "gpio29", "gpio33", "gpio42", "gpio57", 612}; 613static const char * const mgpi_clk_groups[] = { 614 "gpio61", "gpio71", 615}; 616static const char * const qlink2_wmss_groups[] = { 617 "gpio61", 618}; 619static const char * const i2s_mclk_groups[] = { 620 "gpio62", 621}; 622static const char * const audio_ref_groups[] = { 623 "gpio62", 624}; 625static const char * const ldo_update_groups[] = { 626 "gpio62", 627}; 628static const char * const atest_char_groups[] = { 629 "gpio63", 630}; 631static const char * const atest_char3_groups[] = { 632 "gpio64", 633}; 634static const char * const atest_char2_groups[] = { 635 "gpio65", 636}; 637static const char * const atest_char1_groups[] = { 638 "gpio66", 639}; 640static const char * const uim1_data_groups[] = { 641 "gpio67", 642}; 643static const char * const atest_char0_groups[] = { 644 "gpio67", 645}; 646static const char * const uim1_present_groups[] = { 647 "gpio68", 648}; 649static const char * const uim1_reset_groups[] = { 650 "gpio69", 651}; 652static const char * const uim1_clk_groups[] = { 653 "gpio70", 654}; 655static const char * const qlink2_en_groups[] = { 656 "gpio71", 657}; 658static const char * const qlink1_en_groups[] = { 659 "gpio72", 660}; 661static const char * const qlink1_req_groups[] = { 662 "gpio73", 663}; 664static const char * const qlink1_wmss_groups[] = { 665 "gpio74", 666}; 667static const char * const coex_uart2_groups[] = { 668 "gpio75", "gpio76", "gpio102", "gpio103", 669}; 670static const char * const spmi_coex_groups[] = { 671 "gpio75", "gpio76", 672}; 673static const char * const qlink2_req_groups[] = { 674 "gpio77", 675}; 676static const char * const spmi_vgi_groups[] = { 677 "gpio78", "gpio79", 678}; 679static const char * const gcc_plltest_groups[] = { 680 "gpio81", "gpio82", 681}; 682static const char * const ebi2_lcd_groups[] = { 683 "gpio84", "gpio85", "gpio90", 684}; 685static const char * const ebi2_a_groups[] = { 686 "gpio89", 687}; 688static const char * const usb2phy_ac_groups[] = { 689 "gpio93", 690}; 691static const char * const sdc1_tb_groups[] = { 692 "gpio106", 693}; 694 695static const struct pinfunction sdx65_functions[] = { 696 MSM_PIN_FUNCTION(qlink0_wmss), 697 MSM_PIN_FUNCTION(adsp_ext), 698 MSM_PIN_FUNCTION(atest_char), 699 MSM_PIN_FUNCTION(atest_char0), 700 MSM_PIN_FUNCTION(atest_char1), 701 MSM_PIN_FUNCTION(atest_char2), 702 MSM_PIN_FUNCTION(atest_char3), 703 MSM_PIN_FUNCTION(audio_ref), 704 MSM_PIN_FUNCTION(bimc_dte0), 705 MSM_PIN_FUNCTION(bimc_dte1), 706 MSM_PIN_FUNCTION(blsp_i2c1), 707 MSM_PIN_FUNCTION(blsp_i2c2), 708 MSM_PIN_FUNCTION(blsp_i2c3), 709 MSM_PIN_FUNCTION(blsp_i2c4), 710 MSM_PIN_FUNCTION(blsp_spi1), 711 MSM_PIN_FUNCTION(blsp_spi2), 712 MSM_PIN_FUNCTION(blsp_spi3), 713 MSM_PIN_FUNCTION(blsp_spi4), 714 MSM_PIN_FUNCTION(blsp_uart1), 715 MSM_PIN_FUNCTION(blsp_uart2), 716 MSM_PIN_FUNCTION(blsp_uart3), 717 MSM_PIN_FUNCTION(blsp_uart4), 718 MSM_PIN_FUNCTION(char_exec), 719 MSM_PIN_FUNCTION(coex_uart), 720 MSM_PIN_FUNCTION(coex_uart2), 721 MSM_PIN_FUNCTION(cri_trng), 722 MSM_PIN_FUNCTION(cri_trng0), 723 MSM_PIN_FUNCTION(cri_trng1), 724 MSM_PIN_FUNCTION(dbg_out), 725 MSM_PIN_FUNCTION(ddr_bist), 726 MSM_PIN_FUNCTION(ddr_pxi0), 727 MSM_PIN_FUNCTION(ebi0_wrcdc), 728 MSM_PIN_FUNCTION(ebi2_a), 729 MSM_PIN_FUNCTION(ebi2_lcd), 730 MSM_PIN_FUNCTION(ext_dbg), 731 MSM_PIN_FUNCTION(gcc_gp1), 732 MSM_PIN_FUNCTION(gcc_gp2), 733 MSM_PIN_FUNCTION(gcc_gp3), 734 MSM_PIN_FUNCTION(gcc_plltest), 735 MSM_PIN_FUNCTION(gpio), 736 MSM_PIN_FUNCTION(i2s_mclk), 737 MSM_PIN_FUNCTION(jitter_bist), 738 MSM_PIN_FUNCTION(ldo_en), 739 MSM_PIN_FUNCTION(ldo_update), 740 MSM_PIN_FUNCTION(m_voc), 741 MSM_PIN_FUNCTION(mgpi_clk), 742 MSM_PIN_FUNCTION(native_char), 743 MSM_PIN_FUNCTION(native_tsens), 744 MSM_PIN_FUNCTION(native_tsense), 745 MSM_PIN_FUNCTION(nav_gpio), 746 MSM_PIN_FUNCTION(pa_indicator), 747 MSM_PIN_FUNCTION(pci_e), 748 MSM_PIN_FUNCTION(pcie_clkreq), 749 MSM_PIN_FUNCTION(pll_bist), 750 MSM_PIN_FUNCTION(pll_ref), 751 MSM_PIN_FUNCTION(pri_mi2s), 752 MSM_PIN_FUNCTION(pri_mi2s_ws), 753 MSM_PIN_FUNCTION(prng_rosc), 754 MSM_PIN_FUNCTION(qdss_cti), 755 MSM_PIN_FUNCTION(qdss_gpio), 756 MSM_PIN_FUNCTION(qlink0_en), 757 MSM_PIN_FUNCTION(qlink0_req), 758 MSM_PIN_FUNCTION(qlink1_en), 759 MSM_PIN_FUNCTION(qlink1_req), 760 MSM_PIN_FUNCTION(qlink1_wmss), 761 MSM_PIN_FUNCTION(qlink2_en), 762 MSM_PIN_FUNCTION(qlink2_req), 763 MSM_PIN_FUNCTION(qlink2_wmss), 764 MSM_PIN_FUNCTION(sdc1_tb), 765 MSM_PIN_FUNCTION(sec_mi2s), 766 MSM_PIN_FUNCTION(spmi_coex), 767 MSM_PIN_FUNCTION(spmi_vgi), 768 MSM_PIN_FUNCTION(tgu_ch0), 769 MSM_PIN_FUNCTION(uim1_clk), 770 MSM_PIN_FUNCTION(uim1_data), 771 MSM_PIN_FUNCTION(uim1_present), 772 MSM_PIN_FUNCTION(uim1_reset), 773 MSM_PIN_FUNCTION(uim2_clk), 774 MSM_PIN_FUNCTION(uim2_data), 775 MSM_PIN_FUNCTION(uim2_present), 776 MSM_PIN_FUNCTION(uim2_reset), 777 MSM_PIN_FUNCTION(usb2phy_ac), 778 MSM_PIN_FUNCTION(vsense_trigger), 779}; 780 781/* Every pin is maintained as a single group, and missing or non-existing pin 782 * would be maintained as dummy group to synchronize pin group index with 783 * pin descriptor registered with pinctrl core. 784 * Clients would not be able to request these dummy pin groups. 785 */ 786static const struct msm_pingroup sdx65_groups[] = { 787 [0] = PINGROUP(0, uim2_data, blsp_uart1, ebi0_wrcdc, _, _, _, _, _, _), 788 [1] = PINGROUP(1, uim2_present, blsp_uart1, _, _, _, _, _, _, _), 789 [2] = PINGROUP(2, uim2_reset, blsp_uart1, blsp_i2c1, ebi0_wrcdc, _, _, _, _, _), 790 [3] = PINGROUP(3, uim2_clk, blsp_uart1, blsp_i2c1, _, _, _, _, _, _), 791 [4] = PINGROUP(4, blsp_spi2, blsp_uart2, _, qdss_gpio, _, _, _, _, _), 792 [5] = PINGROUP(5, blsp_spi2, blsp_uart2, _, qdss_gpio, _, _, _, _, _), 793 [6] = PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_gpio, _, _, _), 794 [7] = PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_gpio, _, _, _), 795 [8] = PINGROUP(8, blsp_spi3, blsp_uart3, ext_dbg, ldo_en, _, _, _, _, _), 796 [9] = PINGROUP(9, blsp_spi3, blsp_uart3, ext_dbg, _, _, _, _, _, _), 797 [10] = PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, _, _, _, _, _), 798 [11] = PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, gcc_gp3, _, _, _, _), 799 [12] = PINGROUP(12, pri_mi2s_ws, _, qdss_gpio, _, _, _, _, _, _), 800 [13] = PINGROUP(13, pri_mi2s, _, qdss_gpio, vsense_trigger, _, _, _, _, _), 801 [14] = PINGROUP(14, pri_mi2s, _, _, qdss_gpio, native_tsens, bimc_dte0, _, _, _), 802 [15] = PINGROUP(15, pri_mi2s, _, _, qdss_gpio, bimc_dte1, _, _, _, _), 803 [16] = PINGROUP(16, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, _, qdss_gpio, _), 804 [17] = PINGROUP(17, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, qdss_gpio, _, _), 805 [18] = PINGROUP(18, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, gcc_gp1, qdss_gpio, _, _, _), 806 [19] = PINGROUP(19, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, jitter_bist, gcc_gp2, _, qdss_gpio, _), 807 [20] = PINGROUP(20, _, _, _, _, _, _, _, _, _), 808 [21] = PINGROUP(21, _, _, _, _, _, _, _, _, _), 809 [22] = PINGROUP(22, blsp_uart4, pll_bist, _, _, _, _, _, _, _), 810 [23] = PINGROUP(23, blsp_uart4, blsp_spi2, blsp_spi1, blsp_spi3, blsp_spi4, _, _, _, _), 811 [24] = PINGROUP(24, adsp_ext, _, _, _, _, _, _, _, _), 812 [25] = PINGROUP(25, adsp_ext, _, _, _, _, _, _, _, _), 813 [26] = PINGROUP(26, _, _, _, native_char, _, _, _, _, _), 814 [27] = PINGROUP(27, _, _, _, _, _, _, _, _, _), 815 [28] = PINGROUP(28, qlink0_wmss, _, _, _, _, _, _, _, _), 816 [29] = PINGROUP(29, _, _, _, native_tsense, native_char, _, _, _, _), 817 [30] = PINGROUP(30, _, _, _, _, _, _, _, _, _), 818 [31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _), 819 [32] = PINGROUP(32, nav_gpio, pll_ref, _, _, _, _, _, _, _), 820 [33] = PINGROUP(33, _, pa_indicator, qdss_gpio, native_char, _, _, _, _, _), 821 [34] = PINGROUP(34, qlink0_en, _, _, _, _, _, _, _, _), 822 [35] = PINGROUP(35, qlink0_req, dbg_out, _, _, _, _, _, _, _), 823 [36] = PINGROUP(36, _, _, cri_trng, _, _, _, _, _, _), 824 [37] = PINGROUP(37, _, _, _, _, _, _, _, _, _), 825 [38] = PINGROUP(38, _, _, prng_rosc, _, _, _, _, _, _), 826 [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _), 827 [40] = PINGROUP(40, _, _, cri_trng0, _, _, _, _, _, _), 828 [41] = PINGROUP(41, _, _, cri_trng1, _, _, _, _, _, _), 829 [42] = PINGROUP(42, _, qdss_gpio, native_char, _, _, _, _, _, _), 830 [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _), 831 [44] = PINGROUP(44, coex_uart, _, _, _, _, _, _, _, _), 832 [45] = PINGROUP(45, coex_uart, ddr_pxi0, _, _, _, _, _, _, _), 833 [46] = PINGROUP(46, m_voc, ddr_bist, ddr_pxi0, _, _, _, _, _, _), 834 [47] = PINGROUP(47, ddr_bist, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, _, _, _, _), 835 [48] = PINGROUP(48, m_voc, blsp_uart1, blsp_uart4, ddr_bist, _, _, _, _, _), 836 [49] = PINGROUP(49, m_voc, blsp_uart1, blsp_uart4, ddr_bist, _, _, _, _, _), 837 [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), 838 [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), 839 [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _), 840 [53] = PINGROUP(53, pci_e, _, _, _, _, _, _, _, _), 841 [54] = PINGROUP(54, qdss_cti, qdss_cti, _, _, _, _, _, _, _), 842 [55] = PINGROUP(55, qdss_cti, qdss_cti, tgu_ch0, _, _, _, _, _, _), 843 [56] = PINGROUP(56, pcie_clkreq, _, _, _, _, _, _, _, _), 844 [57] = PINGROUP(57, _, native_char, _, _, _, _, _, _, _), 845 [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), 846 [59] = PINGROUP(59, qdss_cti, m_voc, bimc_dte0, _, _, _, _, _, _), 847 [60] = PINGROUP(60, qdss_cti, _, m_voc, _, _, _, _, _, _), 848 [61] = PINGROUP(61, mgpi_clk, qlink2_wmss, bimc_dte1, _, _, _, _, _, _), 849 [62] = PINGROUP(62, i2s_mclk, audio_ref, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, ldo_update, _, _), 850 [63] = PINGROUP(63, blsp_uart2, _, qdss_gpio, atest_char, _, _, _, _, _), 851 [64] = PINGROUP(64, blsp_uart2, qdss_gpio, atest_char3, _, _, _, _, _, _), 852 [65] = PINGROUP(65, blsp_uart2, blsp_i2c2, qdss_cti, qdss_cti, _, qdss_gpio, atest_char2, _, _), 853 [66] = PINGROUP(66, blsp_uart2, blsp_i2c2, qdss_cti, qdss_cti, qdss_gpio, atest_char1, _, _, _), 854 [67] = PINGROUP(67, uim1_data, atest_char0, _, _, _, _, _, _, _), 855 [68] = PINGROUP(68, uim1_present, _, _, _, _, _, _, _, _), 856 [69] = PINGROUP(69, uim1_reset, _, _, _, _, _, _, _, _), 857 [70] = PINGROUP(70, uim1_clk, _, _, _, _, _, _, _, _), 858 [71] = PINGROUP(71, mgpi_clk, qlink2_en, _, _, _, _, _, _, _), 859 [72] = PINGROUP(72, qlink1_en, _, native_tsense, _, _, _, _, _, _), 860 [73] = PINGROUP(73, qlink1_req, _, _, _, _, _, _, _, _), 861 [74] = PINGROUP(74, qlink1_wmss, _, _, _, _, _, _, _, _), 862 [75] = PINGROUP(75, coex_uart2, spmi_coex, _, _, _, _, _, _, _), 863 [76] = PINGROUP(76, coex_uart2, spmi_coex, _, _, _, _, _, _, _), 864 [77] = PINGROUP(77, _, qlink2_req, _, _, _, _, _, _, _), 865 [78] = PINGROUP(78, spmi_vgi, _, _, _, _, _, _, _, _), 866 [79] = PINGROUP(79, spmi_vgi, _, _, _, _, _, _, _, _), 867 [80] = PINGROUP(80, _, blsp_spi1, _, blsp_uart1, _, _, _, _, _), 868 [81] = PINGROUP(81, _, blsp_spi1, _, blsp_uart1, gcc_plltest, _, _, _, _), 869 [82] = PINGROUP(82, _, blsp_spi1, _, blsp_i2c1, gcc_plltest, _, _, _, _), 870 [83] = PINGROUP(83, _, blsp_spi1, _, blsp_i2c1, _, _, _, _, _), 871 [84] = PINGROUP(84, _, ebi2_lcd, _, blsp_i2c4, _, _, _, _, _), 872 [85] = PINGROUP(85, _, ebi2_lcd, _, blsp_i2c4, _, _, _, _, _), 873 [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _), 874 [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _), 875 [88] = PINGROUP(88, _, _, _, _, _, _, _, _, _), 876 [89] = PINGROUP(89, _, _, _, _, ebi2_a, _, _, _, _), 877 [90] = PINGROUP(90, _, _, _, _, ebi2_lcd, _, _, _, _), 878 [91] = PINGROUP(91, _, _, _, _, _, _, _, _, _), 879 [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _), 880 [93] = PINGROUP(93, _, _, usb2phy_ac, _, _, _, _, _, _), 881 [94] = PINGROUP(94, qdss_cti, qdss_cti, _, _, _, _, _, _, _), 882 [95] = PINGROUP(95, qdss_cti, qdss_cti, _, _, _, _, _, _, _), 883 [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _), 884 [97] = PINGROUP(97, _, _, _, _, _, _, _, _, _), 885 [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _), 886 [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _), 887 [100] = PINGROUP(100, _, _, _, _, _, _, _, _, _), 888 [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _), 889 [102] = PINGROUP(102, _, _, coex_uart2, _, _, _, _, _, _), 890 [103] = PINGROUP(103, _, _, coex_uart2, _, _, _, _, _, _), 891 [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _), 892 [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _), 893 [106] = PINGROUP(106, sdc1_tb, _, _, _, _, _, _, _, _), 894 [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _), 895 [108] = UFS_RESET(ufs_reset, 0x0), 896 [109] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x9a000, 15, 0), 897 [110] = SDC_QDSD_PINGROUP(sdc1_clk, 0x9a000, 13, 6), 898 [111] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x9a000, 11, 3), 899 [112] = SDC_QDSD_PINGROUP(sdc1_data, 0x9a000, 9, 0), 900}; 901 902static const struct msm_gpio_wakeirq_map sdx65_pdc_map[] = { 903 {1, 20}, {2, 21}, {5, 22}, {6, 23}, {9, 24}, {10, 25}, 904 {11, 26}, {12, 27}, {13, 28}, {14, 29}, {15, 30}, {16, 31}, 905 {17, 32}, {18, 33}, {19, 34}, {21, 35}, {22, 36}, {23, 70}, 906 {24, 37}, {25, 38}, {35, 40}, {43, 41}, {46, 44}, {48, 45}, 907 {49, 57}, {50, 46}, {52, 47}, {54, 49}, {55, 50}, {60, 53}, 908 {61, 54}, {64, 55}, {65, 81}, {68, 56}, {71, 58}, {73, 59}, 909 {77, 77}, {81, 65}, {83, 63}, {84, 64}, {86, 66}, {88, 67}, 910 {89, 68}, {90, 69}, {93, 71}, {94, 72}, {95, 73}, {96, 74}, 911 {99, 75}, {103, 78}, {104, 79} 912}; 913 914static const struct msm_pinctrl_soc_data sdx65_pinctrl = { 915 .pins = sdx65_pins, 916 .npins = ARRAY_SIZE(sdx65_pins), 917 .functions = sdx65_functions, 918 .nfunctions = ARRAY_SIZE(sdx65_functions), 919 .groups = sdx65_groups, 920 .ngroups = ARRAY_SIZE(sdx65_groups), 921 .ngpios = 109, 922 .wakeirq_map = sdx65_pdc_map, 923 .nwakeirq_map = ARRAY_SIZE(sdx65_pdc_map), 924}; 925 926static int sdx65_pinctrl_probe(struct platform_device *pdev) 927{ 928 return msm_pinctrl_probe(pdev, &sdx65_pinctrl); 929} 930 931static const struct of_device_id sdx65_pinctrl_of_match[] = { 932 { .compatible = "qcom,sdx65-tlmm", }, 933 { }, 934}; 935 936static struct platform_driver sdx65_pinctrl_driver = { 937 .driver = { 938 .name = "sdx65-tlmm", 939 .of_match_table = sdx65_pinctrl_of_match, 940 }, 941 .probe = sdx65_pinctrl_probe, 942 .remove = msm_pinctrl_remove, 943}; 944 945static int __init sdx65_pinctrl_init(void) 946{ 947 return platform_driver_register(&sdx65_pinctrl_driver); 948} 949arch_initcall(sdx65_pinctrl_init); 950 951static void __exit sdx65_pinctrl_exit(void) 952{ 953 platform_driver_unregister(&sdx65_pinctrl_driver); 954} 955module_exit(sdx65_pinctrl_exit); 956 957MODULE_DESCRIPTION("QTI sdx65 pinctrl driver"); 958MODULE_LICENSE("GPL v2"); 959MODULE_DEVICE_TABLE(of, sdx65_pinctrl_of_match); 960