1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020 Linaro Ltd.
5 */
6
7#include <linux/bitfield.h>
8#include <linux/clk.h>
9#include <linux/gpio/driver.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13#include <linux/seq_file.h>
14
15#include <linux/pinctrl/pinconf-generic.h>
16#include <linux/pinctrl/pinconf.h>
17#include <linux/pinctrl/pinmux.h>
18
19#include "../pinctrl-utils.h"
20
21#include "pinctrl-lpass-lpi.h"
22
23#define MAX_NR_GPIO		23
24#define GPIO_FUNC		0
25#define MAX_LPI_NUM_CLKS	2
26
27struct lpi_pinctrl {
28	struct device *dev;
29	struct pinctrl_dev *ctrl;
30	struct gpio_chip chip;
31	struct pinctrl_desc desc;
32	char __iomem *tlmm_base;
33	char __iomem *slew_base;
34	struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
35	/* Protects from concurrent register updates */
36	struct mutex lock;
37	DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO);
38	const struct lpi_pinctrl_variant_data *data;
39};
40
41static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
42			 unsigned int addr)
43{
44	return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
45}
46
47static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
48			  unsigned int addr, unsigned int val)
49{
50	iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
51
52	return 0;
53}
54
55static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {
56	.get_groups_count	= pinctrl_generic_get_group_count,
57	.get_group_name		= pinctrl_generic_get_group_name,
58	.get_group_pins		= pinctrl_generic_get_group_pins,
59	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
60	.dt_free_map		= pinctrl_utils_free_map,
61};
62
63static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev)
64{
65	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
66
67	return pctrl->data->nfunctions;
68}
69
70static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev,
71					      unsigned int function)
72{
73	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
74
75	return pctrl->data->functions[function].name;
76}
77
78static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev,
79					unsigned int function,
80					const char *const **groups,
81					unsigned *const num_qgroups)
82{
83	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
84
85	*groups = pctrl->data->functions[function].groups;
86	*num_qgroups = pctrl->data->functions[function].ngroups;
87
88	return 0;
89}
90
91static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
92			    unsigned int group)
93{
94	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
95	const struct lpi_pingroup *g = &pctrl->data->groups[group];
96	u32 val;
97	int i, pin = g->pin;
98
99	for (i = 0; i < g->nfuncs; i++) {
100		if (g->funcs[i] == function)
101			break;
102	}
103
104	if (WARN_ON(i == g->nfuncs))
105		return -EINVAL;
106
107	mutex_lock(&pctrl->lock);
108	val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);
109
110	/*
111	 * If this is the first time muxing to GPIO and the direction is
112	 * output, make sure that we're not going to be glitching the pin
113	 * by reading the current state of the pin and setting it as the
114	 * output.
115	 */
116	if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) &&
117	    !test_and_set_bit(group, pctrl->ever_gpio)) {
118		u32 io_val = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG);
119
120		if (io_val & LPI_GPIO_VALUE_IN_MASK) {
121			if (!(io_val & LPI_GPIO_VALUE_OUT_MASK))
122				lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,
123					       io_val | LPI_GPIO_VALUE_OUT_MASK);
124		} else {
125			if (io_val & LPI_GPIO_VALUE_OUT_MASK)
126				lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,
127					       io_val & ~LPI_GPIO_VALUE_OUT_MASK);
128		}
129	}
130
131	u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);
132	lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);
133	mutex_unlock(&pctrl->lock);
134
135	return 0;
136}
137
138static const struct pinmux_ops lpi_gpio_pinmux_ops = {
139	.get_functions_count	= lpi_gpio_get_functions_count,
140	.get_function_name	= lpi_gpio_get_function_name,
141	.get_function_groups	= lpi_gpio_get_function_groups,
142	.set_mux		= lpi_gpio_set_mux,
143};
144
145static int lpi_config_get(struct pinctrl_dev *pctldev,
146			  unsigned int pin, unsigned long *config)
147{
148	unsigned int param = pinconf_to_config_param(*config);
149	struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);
150	unsigned int arg = 0;
151	int is_out;
152	int pull;
153	u32 ctl_reg;
154
155	ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);
156	is_out = ctl_reg & LPI_GPIO_OE_MASK;
157	pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
158
159	switch (param) {
160	case PIN_CONFIG_BIAS_DISABLE:
161		if (pull == LPI_GPIO_BIAS_DISABLE)
162			arg = 1;
163		break;
164	case PIN_CONFIG_BIAS_PULL_DOWN:
165		if (pull == LPI_GPIO_PULL_DOWN)
166			arg = 1;
167		break;
168	case PIN_CONFIG_BIAS_BUS_HOLD:
169		if (pull == LPI_GPIO_KEEPER)
170			arg = 1;
171		break;
172	case PIN_CONFIG_BIAS_PULL_UP:
173		if (pull == LPI_GPIO_PULL_UP)
174			arg = 1;
175		break;
176	case PIN_CONFIG_INPUT_ENABLE:
177	case PIN_CONFIG_OUTPUT:
178		if (is_out)
179			arg = 1;
180		break;
181	default:
182		return -EINVAL;
183	}
184
185	*config = pinconf_to_config_packed(param, arg);
186	return 0;
187}
188
189static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
190			  unsigned long *configs, unsigned int nconfs)
191{
192	struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
193	unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
194	bool value, output_enabled = false;
195	const struct lpi_pingroup *g;
196	unsigned long sval;
197	int i, slew_offset;
198	u32 val;
199
200	g = &pctrl->data->groups[group];
201	for (i = 0; i < nconfs; i++) {
202		param = pinconf_to_config_param(configs[i]);
203		arg = pinconf_to_config_argument(configs[i]);
204
205		switch (param) {
206		case PIN_CONFIG_BIAS_DISABLE:
207			pullup = LPI_GPIO_BIAS_DISABLE;
208			break;
209		case PIN_CONFIG_BIAS_PULL_DOWN:
210			pullup = LPI_GPIO_PULL_DOWN;
211			break;
212		case PIN_CONFIG_BIAS_BUS_HOLD:
213			pullup = LPI_GPIO_KEEPER;
214			break;
215		case PIN_CONFIG_BIAS_PULL_UP:
216			pullup = LPI_GPIO_PULL_UP;
217			break;
218		case PIN_CONFIG_INPUT_ENABLE:
219			output_enabled = false;
220			break;
221		case PIN_CONFIG_OUTPUT:
222			output_enabled = true;
223			value = arg;
224			break;
225		case PIN_CONFIG_DRIVE_STRENGTH:
226			strength = arg;
227			break;
228		case PIN_CONFIG_SLEW_RATE:
229			if (arg > LPI_SLEW_RATE_MAX) {
230				dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n",
231					arg, group);
232				return -EINVAL;
233			}
234
235			slew_offset = g->slew_offset;
236			if (slew_offset == LPI_NO_SLEW)
237				break;
238
239			mutex_lock(&pctrl->lock);
240
241			sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
242			sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
243			sval |= arg << slew_offset;
244			iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
245
246			mutex_unlock(&pctrl->lock);
247			break;
248		default:
249			return -EINVAL;
250		}
251	}
252
253	/*
254	 * As per Hardware Programming Guide, when configuring pin as output,
255	 * set the pin value before setting output-enable (OE).
256	 */
257	if (output_enabled) {
258		val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);
259		lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val);
260	}
261
262	mutex_lock(&pctrl->lock);
263	val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);
264
265	u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
266	u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
267			  LPI_GPIO_OUT_STRENGTH_MASK);
268	u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);
269
270	lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);
271	mutex_unlock(&pctrl->lock);
272
273	return 0;
274}
275
276static const struct pinconf_ops lpi_gpio_pinconf_ops = {
277	.is_generic			= true,
278	.pin_config_group_get		= lpi_config_get,
279	.pin_config_group_set		= lpi_config_set,
280};
281
282static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
283{
284	struct lpi_pinctrl *state = gpiochip_get_data(chip);
285	unsigned long config;
286
287	config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
288
289	return lpi_config_set(state->ctrl, pin, &config, 1);
290}
291
292static int lpi_gpio_direction_output(struct gpio_chip *chip,
293				     unsigned int pin, int val)
294{
295	struct lpi_pinctrl *state = gpiochip_get_data(chip);
296	unsigned long config;
297
298	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
299
300	return lpi_config_set(state->ctrl, pin, &config, 1);
301}
302
303static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)
304{
305	struct lpi_pinctrl *state = gpiochip_get_data(chip);
306
307	return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) &
308		LPI_GPIO_VALUE_IN_MASK;
309}
310
311static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
312{
313	struct lpi_pinctrl *state = gpiochip_get_data(chip);
314	unsigned long config;
315
316	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
317
318	lpi_config_set(state->ctrl, pin, &config, 1);
319}
320
321#ifdef CONFIG_DEBUG_FS
322#include <linux/seq_file.h>
323
324static unsigned int lpi_regval_to_drive(u32 val)
325{
326	return (val + 1) * 2;
327}
328
329static void lpi_gpio_dbg_show_one(struct seq_file *s,
330				  struct pinctrl_dev *pctldev,
331				  struct gpio_chip *chip,
332				  unsigned int offset,
333				  unsigned int gpio)
334{
335	struct lpi_pinctrl *state = gpiochip_get_data(chip);
336	struct pinctrl_pin_desc pindesc;
337	unsigned int func;
338	int is_out;
339	int drive;
340	int pull;
341	u32 ctl_reg;
342
343	static const char * const pulls[] = {
344		"no pull",
345		"pull down",
346		"keeper",
347		"pull up"
348	};
349
350	pctldev = pctldev ? : state->ctrl;
351	pindesc = pctldev->desc->pins[offset];
352	ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG);
353	is_out = ctl_reg & LPI_GPIO_OE_MASK;
354
355	func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg);
356	drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg);
357	pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
358
359	seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func);
360	seq_printf(s, " %dmA", lpi_regval_to_drive(drive));
361	seq_printf(s, " %s", pulls[pull]);
362}
363
364static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
365{
366	unsigned int gpio = chip->base;
367	unsigned int i;
368
369	for (i = 0; i < chip->ngpio; i++, gpio++) {
370		lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio);
371		seq_puts(s, "\n");
372	}
373}
374
375#else
376#define lpi_gpio_dbg_show NULL
377#endif
378
379static const struct gpio_chip lpi_gpio_template = {
380	.direction_input	= lpi_gpio_direction_input,
381	.direction_output	= lpi_gpio_direction_output,
382	.get			= lpi_gpio_get,
383	.set			= lpi_gpio_set,
384	.request		= gpiochip_generic_request,
385	.free			= gpiochip_generic_free,
386	.dbg_show		= lpi_gpio_dbg_show,
387};
388
389static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl)
390{
391	int i, ret;
392
393	for (i = 0; i < pctrl->data->npins; i++) {
394		const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i;
395
396		ret = pinctrl_generic_add_group(pctrl->ctrl, pin_info->name,
397						  (int *)&pin_info->number, 1, NULL);
398		if (ret < 0)
399			goto err_pinctrl;
400	}
401
402	return 0;
403
404err_pinctrl:
405	for (; i > 0; i--)
406		pinctrl_generic_remove_group(pctrl->ctrl, i - 1);
407
408	return ret;
409}
410
411int lpi_pinctrl_probe(struct platform_device *pdev)
412{
413	const struct lpi_pinctrl_variant_data *data;
414	struct device *dev = &pdev->dev;
415	struct lpi_pinctrl *pctrl;
416	int ret;
417
418	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
419	if (!pctrl)
420		return -ENOMEM;
421
422	platform_set_drvdata(pdev, pctrl);
423
424	data = of_device_get_match_data(dev);
425	if (!data)
426		return -EINVAL;
427
428	if (WARN_ON(data->npins > MAX_NR_GPIO))
429		return -EINVAL;
430
431	pctrl->data = data;
432	pctrl->dev = &pdev->dev;
433
434	pctrl->clks[0].id = "core";
435	pctrl->clks[1].id = "audio";
436
437	pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);
438	if (IS_ERR(pctrl->tlmm_base))
439		return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),
440				     "TLMM resource not provided\n");
441
442	pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
443	if (IS_ERR(pctrl->slew_base))
444		return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
445				     "Slew resource not provided\n");
446
447	ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
448	if (ret)
449		return ret;
450
451	ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);
452	if (ret)
453		return dev_err_probe(dev, ret, "Can't enable clocks\n");
454
455	pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;
456	pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;
457	pctrl->desc.confops = &lpi_gpio_pinconf_ops;
458	pctrl->desc.owner = THIS_MODULE;
459	pctrl->desc.name = dev_name(dev);
460	pctrl->desc.pins = data->pins;
461	pctrl->desc.npins = data->npins;
462	pctrl->chip = lpi_gpio_template;
463	pctrl->chip.parent = dev;
464	pctrl->chip.base = -1;
465	pctrl->chip.ngpio = data->npins;
466	pctrl->chip.label = dev_name(dev);
467	pctrl->chip.can_sleep = false;
468
469	mutex_init(&pctrl->lock);
470
471	pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl);
472	if (IS_ERR(pctrl->ctrl)) {
473		ret = PTR_ERR(pctrl->ctrl);
474		dev_err(dev, "failed to add pin controller\n");
475		goto err_pinctrl;
476	}
477
478	ret = lpi_build_pin_desc_groups(pctrl);
479	if (ret)
480		goto err_pinctrl;
481
482	ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl);
483	if (ret) {
484		dev_err(pctrl->dev, "can't add gpio chip\n");
485		goto err_pinctrl;
486	}
487
488	return 0;
489
490err_pinctrl:
491	mutex_destroy(&pctrl->lock);
492	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
493
494	return ret;
495}
496EXPORT_SYMBOL_GPL(lpi_pinctrl_probe);
497
498int lpi_pinctrl_remove(struct platform_device *pdev)
499{
500	struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
501	int i;
502
503	mutex_destroy(&pctrl->lock);
504	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
505
506	for (i = 0; i < pctrl->data->npins; i++)
507		pinctrl_generic_remove_group(pctrl->ctrl, i);
508
509	return 0;
510}
511EXPORT_SYMBOL_GPL(lpi_pinctrl_remove);
512
513MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
514MODULE_LICENSE("GPL");
515