1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Biao Huang <biao.huang@mediatek.com> 5 */ 6 7#include <dt-bindings/pinctrl/mt65xx.h> 8#include <linux/module.h> 9#include <linux/of.h> 10#include <linux/platform_device.h> 11#include <linux/pinctrl/pinctrl.h> 12#include <linux/regmap.h> 13 14#include "pinctrl-mtk-common.h" 15#include "pinctrl-mtk-mt2701.h" 16 17/** 18 * struct mtk_spec_pinmux_set 19 * - For special pins' mode setting 20 * @pin: The pin number. 21 * @offset: The offset of extra setting register. 22 * @bit: The bit of extra setting register. 23 */ 24struct mtk_spec_pinmux_set { 25 unsigned short pin; 26 unsigned short offset; 27 unsigned char bit; 28}; 29 30#define MTK_PINMUX_SPEC(_pin, _offset, _bit) \ 31 { \ 32 .pin = _pin, \ 33 .offset = _offset, \ 34 .bit = _bit, \ 35 } 36 37static const struct mtk_drv_group_desc mt2701_drv_grp[] = { 38 /* 0E4E8SR 4/8/12/16 */ 39 MTK_DRV_GRP(4, 16, 1, 2, 4), 40 /* 0E2E4SR 2/4/6/8 */ 41 MTK_DRV_GRP(2, 8, 1, 2, 2), 42 /* E8E4E2 2/4/6/8/10/12/14/16 */ 43 MTK_DRV_GRP(2, 16, 0, 2, 2) 44}; 45 46static const struct mtk_pin_drv_grp mt2701_pin_drv[] = { 47 MTK_PIN_DRV_GRP(0, 0xf50, 0, 1), 48 MTK_PIN_DRV_GRP(1, 0xf50, 0, 1), 49 MTK_PIN_DRV_GRP(2, 0xf50, 0, 1), 50 MTK_PIN_DRV_GRP(3, 0xf50, 0, 1), 51 MTK_PIN_DRV_GRP(4, 0xf50, 0, 1), 52 MTK_PIN_DRV_GRP(5, 0xf50, 0, 1), 53 MTK_PIN_DRV_GRP(6, 0xf50, 0, 1), 54 MTK_PIN_DRV_GRP(7, 0xf50, 4, 1), 55 MTK_PIN_DRV_GRP(8, 0xf50, 4, 1), 56 MTK_PIN_DRV_GRP(9, 0xf50, 4, 1), 57 MTK_PIN_DRV_GRP(10, 0xf50, 8, 1), 58 MTK_PIN_DRV_GRP(11, 0xf50, 8, 1), 59 MTK_PIN_DRV_GRP(12, 0xf50, 8, 1), 60 MTK_PIN_DRV_GRP(13, 0xf50, 8, 1), 61 MTK_PIN_DRV_GRP(14, 0xf50, 12, 0), 62 MTK_PIN_DRV_GRP(15, 0xf50, 12, 0), 63 MTK_PIN_DRV_GRP(16, 0xf60, 0, 0), 64 MTK_PIN_DRV_GRP(17, 0xf60, 0, 0), 65 MTK_PIN_DRV_GRP(18, 0xf60, 4, 0), 66 MTK_PIN_DRV_GRP(19, 0xf60, 4, 0), 67 MTK_PIN_DRV_GRP(20, 0xf60, 4, 0), 68 MTK_PIN_DRV_GRP(21, 0xf60, 4, 0), 69 MTK_PIN_DRV_GRP(22, 0xf60, 8, 0), 70 MTK_PIN_DRV_GRP(23, 0xf60, 8, 0), 71 MTK_PIN_DRV_GRP(24, 0xf60, 8, 0), 72 MTK_PIN_DRV_GRP(25, 0xf60, 8, 0), 73 MTK_PIN_DRV_GRP(26, 0xf60, 8, 0), 74 MTK_PIN_DRV_GRP(27, 0xf60, 12, 0), 75 MTK_PIN_DRV_GRP(28, 0xf60, 12, 0), 76 MTK_PIN_DRV_GRP(29, 0xf60, 12, 0), 77 MTK_PIN_DRV_GRP(30, 0xf60, 0, 0), 78 MTK_PIN_DRV_GRP(31, 0xf60, 0, 0), 79 MTK_PIN_DRV_GRP(32, 0xf60, 0, 0), 80 MTK_PIN_DRV_GRP(33, 0xf70, 0, 0), 81 MTK_PIN_DRV_GRP(34, 0xf70, 0, 0), 82 MTK_PIN_DRV_GRP(35, 0xf70, 0, 0), 83 MTK_PIN_DRV_GRP(36, 0xf70, 0, 0), 84 MTK_PIN_DRV_GRP(37, 0xf70, 0, 0), 85 MTK_PIN_DRV_GRP(38, 0xf70, 4, 0), 86 MTK_PIN_DRV_GRP(39, 0xf70, 8, 1), 87 MTK_PIN_DRV_GRP(40, 0xf70, 8, 1), 88 MTK_PIN_DRV_GRP(41, 0xf70, 8, 1), 89 MTK_PIN_DRV_GRP(42, 0xf70, 8, 1), 90 MTK_PIN_DRV_GRP(43, 0xf70, 12, 0), 91 MTK_PIN_DRV_GRP(44, 0xf70, 12, 0), 92 MTK_PIN_DRV_GRP(45, 0xf70, 12, 0), 93 MTK_PIN_DRV_GRP(47, 0xf80, 0, 0), 94 MTK_PIN_DRV_GRP(48, 0xf80, 0, 0), 95 MTK_PIN_DRV_GRP(49, 0xf80, 4, 0), 96 MTK_PIN_DRV_GRP(50, 0xf70, 4, 0), 97 MTK_PIN_DRV_GRP(51, 0xf70, 4, 0), 98 MTK_PIN_DRV_GRP(52, 0xf70, 4, 0), 99 MTK_PIN_DRV_GRP(53, 0xf80, 12, 0), 100 MTK_PIN_DRV_GRP(54, 0xf80, 12, 0), 101 MTK_PIN_DRV_GRP(55, 0xf80, 12, 0), 102 MTK_PIN_DRV_GRP(56, 0xf80, 12, 0), 103 MTK_PIN_DRV_GRP(60, 0xf90, 8, 1), 104 MTK_PIN_DRV_GRP(61, 0xf90, 8, 1), 105 MTK_PIN_DRV_GRP(62, 0xf90, 8, 1), 106 MTK_PIN_DRV_GRP(63, 0xf90, 12, 1), 107 MTK_PIN_DRV_GRP(64, 0xf90, 12, 1), 108 MTK_PIN_DRV_GRP(65, 0xf90, 12, 1), 109 MTK_PIN_DRV_GRP(66, 0xfa0, 0, 1), 110 MTK_PIN_DRV_GRP(67, 0xfa0, 0, 1), 111 MTK_PIN_DRV_GRP(68, 0xfa0, 0, 1), 112 MTK_PIN_DRV_GRP(69, 0xfa0, 0, 1), 113 MTK_PIN_DRV_GRP(70, 0xfa0, 0, 1), 114 MTK_PIN_DRV_GRP(71, 0xfa0, 0, 1), 115 MTK_PIN_DRV_GRP(72, 0xf80, 4, 0), 116 MTK_PIN_DRV_GRP(73, 0xf80, 4, 0), 117 MTK_PIN_DRV_GRP(74, 0xf80, 4, 0), 118 MTK_PIN_DRV_GRP(85, 0xda0, 0, 2), 119 MTK_PIN_DRV_GRP(86, 0xd90, 0, 2), 120 MTK_PIN_DRV_GRP(87, 0xdb0, 0, 2), 121 MTK_PIN_DRV_GRP(88, 0xdb0, 0, 2), 122 MTK_PIN_DRV_GRP(89, 0xdb0, 0, 2), 123 MTK_PIN_DRV_GRP(90, 0xdb0, 0, 2), 124 MTK_PIN_DRV_GRP(105, 0xd40, 0, 2), 125 MTK_PIN_DRV_GRP(106, 0xd30, 0, 2), 126 MTK_PIN_DRV_GRP(107, 0xd50, 0, 2), 127 MTK_PIN_DRV_GRP(108, 0xd50, 0, 2), 128 MTK_PIN_DRV_GRP(109, 0xd50, 0, 2), 129 MTK_PIN_DRV_GRP(110, 0xd50, 0, 2), 130 MTK_PIN_DRV_GRP(111, 0xce0, 0, 2), 131 MTK_PIN_DRV_GRP(112, 0xce0, 0, 2), 132 MTK_PIN_DRV_GRP(113, 0xce0, 0, 2), 133 MTK_PIN_DRV_GRP(114, 0xce0, 0, 2), 134 MTK_PIN_DRV_GRP(115, 0xce0, 0, 2), 135 MTK_PIN_DRV_GRP(116, 0xcd0, 0, 2), 136 MTK_PIN_DRV_GRP(117, 0xcc0, 0, 2), 137 MTK_PIN_DRV_GRP(118, 0xce0, 0, 2), 138 MTK_PIN_DRV_GRP(119, 0xce0, 0, 2), 139 MTK_PIN_DRV_GRP(120, 0xce0, 0, 2), 140 MTK_PIN_DRV_GRP(121, 0xce0, 0, 2), 141 MTK_PIN_DRV_GRP(126, 0xf80, 4, 0), 142 MTK_PIN_DRV_GRP(188, 0xf70, 4, 0), 143 MTK_PIN_DRV_GRP(189, 0xfe0, 8, 0), 144 MTK_PIN_DRV_GRP(190, 0xfe0, 8, 0), 145 MTK_PIN_DRV_GRP(191, 0xfe0, 8, 0), 146 MTK_PIN_DRV_GRP(192, 0xfe0, 8, 0), 147 MTK_PIN_DRV_GRP(193, 0xfe0, 8, 0), 148 MTK_PIN_DRV_GRP(194, 0xfe0, 12, 0), 149 MTK_PIN_DRV_GRP(195, 0xfe0, 12, 0), 150 MTK_PIN_DRV_GRP(196, 0xfe0, 12, 0), 151 MTK_PIN_DRV_GRP(197, 0xfe0, 12, 0), 152 MTK_PIN_DRV_GRP(198, 0xfe0, 12, 0), 153 MTK_PIN_DRV_GRP(199, 0xf50, 4, 1), 154 MTK_PIN_DRV_GRP(200, 0xfd0, 0, 0), 155 MTK_PIN_DRV_GRP(201, 0xfd0, 0, 0), 156 MTK_PIN_DRV_GRP(202, 0xfd0, 0, 0), 157 MTK_PIN_DRV_GRP(203, 0xfd0, 4, 0), 158 MTK_PIN_DRV_GRP(204, 0xfd0, 4, 0), 159 MTK_PIN_DRV_GRP(205, 0xfd0, 4, 0), 160 MTK_PIN_DRV_GRP(206, 0xfd0, 4, 0), 161 MTK_PIN_DRV_GRP(207, 0xfd0, 4, 0), 162 MTK_PIN_DRV_GRP(208, 0xfd0, 8, 0), 163 MTK_PIN_DRV_GRP(209, 0xfd0, 8, 0), 164 MTK_PIN_DRV_GRP(210, 0xfd0, 12, 1), 165 MTK_PIN_DRV_GRP(211, 0xff0, 0, 1), 166 MTK_PIN_DRV_GRP(212, 0xff0, 0, 1), 167 MTK_PIN_DRV_GRP(213, 0xff0, 0, 1), 168 MTK_PIN_DRV_GRP(214, 0xff0, 0, 1), 169 MTK_PIN_DRV_GRP(215, 0xff0, 0, 1), 170 MTK_PIN_DRV_GRP(216, 0xff0, 0, 1), 171 MTK_PIN_DRV_GRP(217, 0xff0, 0, 1), 172 MTK_PIN_DRV_GRP(218, 0xff0, 0, 1), 173 MTK_PIN_DRV_GRP(219, 0xff0, 0, 1), 174 MTK_PIN_DRV_GRP(220, 0xff0, 0, 1), 175 MTK_PIN_DRV_GRP(221, 0xff0, 0, 1), 176 MTK_PIN_DRV_GRP(222, 0xff0, 0, 1), 177 MTK_PIN_DRV_GRP(223, 0xff0, 0, 1), 178 MTK_PIN_DRV_GRP(224, 0xff0, 0, 1), 179 MTK_PIN_DRV_GRP(225, 0xff0, 0, 1), 180 MTK_PIN_DRV_GRP(226, 0xff0, 0, 1), 181 MTK_PIN_DRV_GRP(227, 0xff0, 0, 1), 182 MTK_PIN_DRV_GRP(228, 0xff0, 0, 1), 183 MTK_PIN_DRV_GRP(229, 0xff0, 0, 1), 184 MTK_PIN_DRV_GRP(230, 0xff0, 0, 1), 185 MTK_PIN_DRV_GRP(231, 0xff0, 0, 1), 186 MTK_PIN_DRV_GRP(232, 0xff0, 0, 1), 187 MTK_PIN_DRV_GRP(233, 0xff0, 0, 1), 188 MTK_PIN_DRV_GRP(234, 0xff0, 0, 1), 189 MTK_PIN_DRV_GRP(235, 0xff0, 0, 1), 190 MTK_PIN_DRV_GRP(236, 0xff0, 4, 0), 191 MTK_PIN_DRV_GRP(237, 0xff0, 4, 0), 192 MTK_PIN_DRV_GRP(238, 0xff0, 4, 0), 193 MTK_PIN_DRV_GRP(239, 0xff0, 4, 0), 194 MTK_PIN_DRV_GRP(240, 0xff0, 4, 0), 195 MTK_PIN_DRV_GRP(241, 0xff0, 4, 0), 196 MTK_PIN_DRV_GRP(242, 0xff0, 8, 0), 197 MTK_PIN_DRV_GRP(243, 0xff0, 8, 0), 198 MTK_PIN_DRV_GRP(248, 0xf00, 0, 0), 199 MTK_PIN_DRV_GRP(249, 0xfc0, 0, 2), 200 MTK_PIN_DRV_GRP(250, 0xfc0, 0, 2), 201 MTK_PIN_DRV_GRP(251, 0xfc0, 0, 2), 202 MTK_PIN_DRV_GRP(252, 0xfc0, 0, 2), 203 MTK_PIN_DRV_GRP(253, 0xfc0, 0, 2), 204 MTK_PIN_DRV_GRP(254, 0xfc0, 0, 2), 205 MTK_PIN_DRV_GRP(255, 0xfc0, 0, 2), 206 MTK_PIN_DRV_GRP(256, 0xfc0, 0, 2), 207 MTK_PIN_DRV_GRP(257, 0xce0, 0, 2), 208 MTK_PIN_DRV_GRP(258, 0xcb0, 0, 2), 209 MTK_PIN_DRV_GRP(259, 0xc90, 0, 2), 210 MTK_PIN_DRV_GRP(260, 0x3a0, 0, 2), 211 MTK_PIN_DRV_GRP(261, 0xd50, 0, 2), 212 MTK_PIN_DRV_GRP(262, 0xf00, 8, 0), 213 MTK_PIN_DRV_GRP(263, 0xf00, 8, 0), 214 MTK_PIN_DRV_GRP(264, 0xf00, 8, 0), 215 MTK_PIN_DRV_GRP(265, 0xf00, 8, 0), 216 MTK_PIN_DRV_GRP(266, 0xf00, 8, 0), 217 MTK_PIN_DRV_GRP(267, 0xf00, 8, 0), 218 MTK_PIN_DRV_GRP(268, 0xf00, 8, 0), 219 MTK_PIN_DRV_GRP(269, 0xf00, 8, 0), 220 MTK_PIN_DRV_GRP(270, 0xf00, 8, 0), 221 MTK_PIN_DRV_GRP(271, 0xf00, 8, 0), 222 MTK_PIN_DRV_GRP(272, 0xf00, 8, 0), 223 MTK_PIN_DRV_GRP(273, 0xf00, 8, 0), 224 MTK_PIN_DRV_GRP(274, 0xf00, 8, 0), 225 MTK_PIN_DRV_GRP(275, 0xf00, 8, 0), 226 MTK_PIN_DRV_GRP(276, 0xf00, 8, 0), 227 MTK_PIN_DRV_GRP(277, 0xf00, 8, 0), 228 MTK_PIN_DRV_GRP(278, 0xf70, 8, 1), 229}; 230 231static const struct mtk_pin_spec_pupd_set_samereg mt2701_spec_pupd[] = { 232 MTK_PIN_PUPD_SPEC_SR(111, 0xd00, 12, 13, 14), /* ms0 data7 */ 233 MTK_PIN_PUPD_SPEC_SR(112, 0xd00, 8, 9, 10), /* ms0 data6 */ 234 MTK_PIN_PUPD_SPEC_SR(113, 0xd00, 4, 5, 6), /* ms0 data5 */ 235 MTK_PIN_PUPD_SPEC_SR(114, 0xd00, 0, 1, 2), /* ms0 data4 */ 236 MTK_PIN_PUPD_SPEC_SR(115, 0xd10, 0, 1, 2), /* ms0 rstb */ 237 MTK_PIN_PUPD_SPEC_SR(116, 0xcd0, 8, 9, 10), /* ms0 cmd */ 238 MTK_PIN_PUPD_SPEC_SR(117, 0xcc0, 8, 9, 10), /* ms0 clk */ 239 MTK_PIN_PUPD_SPEC_SR(118, 0xcf0, 12, 13, 14), /* ms0 data3 */ 240 MTK_PIN_PUPD_SPEC_SR(119, 0xcf0, 8, 9, 10), /* ms0 data2 */ 241 MTK_PIN_PUPD_SPEC_SR(120, 0xcf0, 4, 5, 6), /* ms0 data1 */ 242 MTK_PIN_PUPD_SPEC_SR(121, 0xcf0, 0, 1, 2), /* ms0 data0 */ 243 244 MTK_PIN_PUPD_SPEC_SR(105, 0xd40, 8, 9, 10), /* ms1 cmd */ 245 MTK_PIN_PUPD_SPEC_SR(106, 0xd30, 8, 9, 10), /* ms1 clk */ 246 MTK_PIN_PUPD_SPEC_SR(107, 0xd60, 0, 1, 2), /* ms1 dat0 */ 247 MTK_PIN_PUPD_SPEC_SR(108, 0xd60, 10, 9, 8), /* ms1 dat1 */ 248 MTK_PIN_PUPD_SPEC_SR(109, 0xd60, 4, 5, 6), /* ms1 dat2 */ 249 MTK_PIN_PUPD_SPEC_SR(110, 0xc60, 12, 13, 14), /* ms1 dat3 */ 250 251 MTK_PIN_PUPD_SPEC_SR(85, 0xda0, 8, 9, 10), /* ms2 cmd */ 252 MTK_PIN_PUPD_SPEC_SR(86, 0xd90, 8, 9, 10), /* ms2 clk */ 253 MTK_PIN_PUPD_SPEC_SR(87, 0xdc0, 0, 1, 2), /* ms2 dat0 */ 254 MTK_PIN_PUPD_SPEC_SR(88, 0xdc0, 10, 9, 8), /* ms2 dat1 */ 255 MTK_PIN_PUPD_SPEC_SR(89, 0xdc0, 4, 5, 6), /* ms2 dat2 */ 256 MTK_PIN_PUPD_SPEC_SR(90, 0xdc0, 12, 13, 14), /* ms2 dat3 */ 257 258 MTK_PIN_PUPD_SPEC_SR(249, 0x140, 0, 1, 2), /* ms0e rstb */ 259 MTK_PIN_PUPD_SPEC_SR(250, 0x130, 12, 13, 14), /* ms0e dat7 */ 260 MTK_PIN_PUPD_SPEC_SR(251, 0x130, 8, 9, 10), /* ms0e dat6 */ 261 MTK_PIN_PUPD_SPEC_SR(252, 0x130, 4, 5, 6), /* ms0e dat5 */ 262 MTK_PIN_PUPD_SPEC_SR(253, 0x130, 0, 1, 2), /* ms0e dat4 */ 263 MTK_PIN_PUPD_SPEC_SR(254, 0xf40, 12, 13, 14), /* ms0e dat3 */ 264 MTK_PIN_PUPD_SPEC_SR(255, 0xf40, 8, 9, 10), /* ms0e dat2 */ 265 MTK_PIN_PUPD_SPEC_SR(256, 0xf40, 4, 5, 6), /* ms0e dat1 */ 266 MTK_PIN_PUPD_SPEC_SR(257, 0xf40, 0, 1, 2), /* ms0e dat0 */ 267 MTK_PIN_PUPD_SPEC_SR(258, 0xcb0, 8, 9, 10), /* ms0e cmd */ 268 MTK_PIN_PUPD_SPEC_SR(259, 0xc90, 8, 9, 10), /* ms0e clk */ 269 MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10), /* ms1 ins */ 270}; 271 272static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = { 273 MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0), 274 MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1), 275 MTK_PIN_IES_SMT_SPEC(10, 13, 0xb30, 3), 276 MTK_PIN_IES_SMT_SPEC(14, 15, 0xb30, 13), 277 MTK_PIN_IES_SMT_SPEC(16, 17, 0xb40, 7), 278 MTK_PIN_IES_SMT_SPEC(18, 21, 0xb40, 13), 279 MTK_PIN_IES_SMT_SPEC(22, 26, 0xb40, 13), 280 MTK_PIN_IES_SMT_SPEC(27, 29, 0xb40, 13), 281 MTK_PIN_IES_SMT_SPEC(30, 32, 0xb40, 7), 282 MTK_PIN_IES_SMT_SPEC(33, 37, 0xb40, 13), 283 MTK_PIN_IES_SMT_SPEC(38, 38, 0xb20, 13), 284 MTK_PIN_IES_SMT_SPEC(39, 42, 0xb40, 13), 285 MTK_PIN_IES_SMT_SPEC(43, 45, 0xb20, 10), 286 MTK_PIN_IES_SMT_SPEC(47, 48, 0xb20, 11), 287 MTK_PIN_IES_SMT_SPEC(49, 49, 0xb20, 12), 288 MTK_PIN_IES_SMT_SPEC(50, 52, 0xb20, 13), 289 MTK_PIN_IES_SMT_SPEC(53, 56, 0xb20, 14), 290 MTK_PIN_IES_SMT_SPEC(57, 58, 0xb20, 15), 291 MTK_PIN_IES_SMT_SPEC(59, 59, 0xb30, 10), 292 MTK_PIN_IES_SMT_SPEC(60, 62, 0xb30, 0), 293 MTK_PIN_IES_SMT_SPEC(63, 65, 0xb30, 1), 294 MTK_PIN_IES_SMT_SPEC(66, 71, 0xb30, 2), 295 MTK_PIN_IES_SMT_SPEC(72, 74, 0xb20, 12), 296 MTK_PIN_IES_SMT_SPEC(75, 76, 0xb30, 3), 297 MTK_PIN_IES_SMT_SPEC(77, 78, 0xb30, 4), 298 MTK_PIN_IES_SMT_SPEC(79, 82, 0xb30, 5), 299 MTK_PIN_IES_SMT_SPEC(83, 84, 0xb30, 2), 300 MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 4), 301 MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 4), 302 MTK_PIN_IES_SMT_SPEC(87, 90, 0xdb0, 4), 303 MTK_PIN_IES_SMT_SPEC(101, 104, 0xb30, 6), 304 MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 4), 305 MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 4), 306 MTK_PIN_IES_SMT_SPEC(107, 110, 0xd50, 4), 307 MTK_PIN_IES_SMT_SPEC(111, 115, 0xce0, 4), 308 MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 4), 309 MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 4), 310 MTK_PIN_IES_SMT_SPEC(118, 121, 0xce0, 4), 311 MTK_PIN_IES_SMT_SPEC(122, 125, 0xb30, 7), 312 MTK_PIN_IES_SMT_SPEC(126, 126, 0xb20, 12), 313 MTK_PIN_IES_SMT_SPEC(127, 142, 0xb30, 9), 314 MTK_PIN_IES_SMT_SPEC(143, 160, 0xb30, 10), 315 MTK_PIN_IES_SMT_SPEC(161, 168, 0xb30, 12), 316 MTK_PIN_IES_SMT_SPEC(169, 183, 0xb30, 10), 317 MTK_PIN_IES_SMT_SPEC(184, 186, 0xb30, 9), 318 MTK_PIN_IES_SMT_SPEC(187, 187, 0xb30, 14), 319 MTK_PIN_IES_SMT_SPEC(188, 188, 0xb20, 13), 320 MTK_PIN_IES_SMT_SPEC(189, 193, 0xb30, 15), 321 MTK_PIN_IES_SMT_SPEC(194, 198, 0xb40, 0), 322 MTK_PIN_IES_SMT_SPEC(199, 199, 0xb20, 1), 323 MTK_PIN_IES_SMT_SPEC(200, 202, 0xb40, 1), 324 MTK_PIN_IES_SMT_SPEC(203, 207, 0xb40, 2), 325 MTK_PIN_IES_SMT_SPEC(208, 209, 0xb40, 3), 326 MTK_PIN_IES_SMT_SPEC(210, 210, 0xb40, 4), 327 MTK_PIN_IES_SMT_SPEC(211, 235, 0xb40, 5), 328 MTK_PIN_IES_SMT_SPEC(236, 241, 0xb40, 6), 329 MTK_PIN_IES_SMT_SPEC(242, 243, 0xb40, 7), 330 MTK_PIN_IES_SMT_SPEC(244, 247, 0xb40, 8), 331 MTK_PIN_IES_SMT_SPEC(248, 248, 0xb40, 9), 332 MTK_PIN_IES_SMT_SPEC(249, 257, 0xfc0, 4), 333 MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 4), 334 MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 4), 335 MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 4), 336 MTK_PIN_IES_SMT_SPEC(261, 261, 0xd50, 4), 337 MTK_PIN_IES_SMT_SPEC(262, 277, 0xb40, 12), 338 MTK_PIN_IES_SMT_SPEC(278, 278, 0xb40, 13), 339}; 340 341static const struct mtk_pin_ies_smt_set mt2701_smt_set[] = { 342 MTK_PIN_IES_SMT_SPEC(0, 6, 0xb50, 0), 343 MTK_PIN_IES_SMT_SPEC(7, 9, 0xb50, 1), 344 MTK_PIN_IES_SMT_SPEC(10, 13, 0xb60, 3), 345 MTK_PIN_IES_SMT_SPEC(14, 15, 0xb60, 13), 346 MTK_PIN_IES_SMT_SPEC(16, 17, 0xb70, 7), 347 MTK_PIN_IES_SMT_SPEC(18, 21, 0xb70, 13), 348 MTK_PIN_IES_SMT_SPEC(22, 26, 0xb70, 13), 349 MTK_PIN_IES_SMT_SPEC(27, 29, 0xb70, 13), 350 MTK_PIN_IES_SMT_SPEC(30, 32, 0xb70, 7), 351 MTK_PIN_IES_SMT_SPEC(33, 37, 0xb70, 13), 352 MTK_PIN_IES_SMT_SPEC(38, 38, 0xb50, 13), 353 MTK_PIN_IES_SMT_SPEC(39, 42, 0xb70, 13), 354 MTK_PIN_IES_SMT_SPEC(43, 45, 0xb50, 10), 355 MTK_PIN_IES_SMT_SPEC(47, 48, 0xb50, 11), 356 MTK_PIN_IES_SMT_SPEC(49, 49, 0xb50, 12), 357 MTK_PIN_IES_SMT_SPEC(50, 52, 0xb50, 13), 358 MTK_PIN_IES_SMT_SPEC(53, 56, 0xb50, 14), 359 MTK_PIN_IES_SMT_SPEC(57, 58, 0xb50, 15), 360 MTK_PIN_IES_SMT_SPEC(59, 59, 0xb60, 10), 361 MTK_PIN_IES_SMT_SPEC(60, 62, 0xb60, 0), 362 MTK_PIN_IES_SMT_SPEC(63, 65, 0xb60, 1), 363 MTK_PIN_IES_SMT_SPEC(66, 71, 0xb60, 2), 364 MTK_PIN_IES_SMT_SPEC(72, 74, 0xb50, 12), 365 MTK_PIN_IES_SMT_SPEC(75, 76, 0xb60, 3), 366 MTK_PIN_IES_SMT_SPEC(77, 78, 0xb60, 4), 367 MTK_PIN_IES_SMT_SPEC(79, 82, 0xb60, 5), 368 MTK_PIN_IES_SMT_SPEC(83, 84, 0xb60, 2), 369 MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 11), 370 MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 11), 371 MTK_PIN_IES_SMT_SPEC(87, 87, 0xdc0, 3), 372 MTK_PIN_IES_SMT_SPEC(88, 88, 0xdc0, 7), 373 MTK_PIN_IES_SMT_SPEC(89, 89, 0xdc0, 11), 374 MTK_PIN_IES_SMT_SPEC(90, 90, 0xdc0, 15), 375 MTK_PIN_IES_SMT_SPEC(101, 104, 0xb60, 6), 376 MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 11), 377 MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 11), 378 MTK_PIN_IES_SMT_SPEC(107, 107, 0xd60, 3), 379 MTK_PIN_IES_SMT_SPEC(108, 108, 0xd60, 7), 380 MTK_PIN_IES_SMT_SPEC(109, 109, 0xd60, 11), 381 MTK_PIN_IES_SMT_SPEC(110, 110, 0xd60, 15), 382 MTK_PIN_IES_SMT_SPEC(111, 111, 0xd00, 15), 383 MTK_PIN_IES_SMT_SPEC(112, 112, 0xd00, 11), 384 MTK_PIN_IES_SMT_SPEC(113, 113, 0xd00, 7), 385 MTK_PIN_IES_SMT_SPEC(114, 114, 0xd00, 3), 386 MTK_PIN_IES_SMT_SPEC(115, 115, 0xd10, 3), 387 MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 11), 388 MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 11), 389 MTK_PIN_IES_SMT_SPEC(118, 118, 0xcf0, 15), 390 MTK_PIN_IES_SMT_SPEC(119, 119, 0xcf0, 11), 391 MTK_PIN_IES_SMT_SPEC(120, 120, 0xcf0, 7), 392 MTK_PIN_IES_SMT_SPEC(121, 121, 0xcf0, 3), 393 MTK_PIN_IES_SMT_SPEC(122, 125, 0xb60, 7), 394 MTK_PIN_IES_SMT_SPEC(126, 126, 0xb50, 12), 395 MTK_PIN_IES_SMT_SPEC(127, 142, 0xb60, 9), 396 MTK_PIN_IES_SMT_SPEC(143, 160, 0xb60, 10), 397 MTK_PIN_IES_SMT_SPEC(161, 168, 0xb60, 12), 398 MTK_PIN_IES_SMT_SPEC(169, 183, 0xb60, 10), 399 MTK_PIN_IES_SMT_SPEC(184, 186, 0xb60, 9), 400 MTK_PIN_IES_SMT_SPEC(187, 187, 0xb60, 14), 401 MTK_PIN_IES_SMT_SPEC(188, 188, 0xb50, 13), 402 MTK_PIN_IES_SMT_SPEC(189, 193, 0xb60, 15), 403 MTK_PIN_IES_SMT_SPEC(194, 198, 0xb70, 0), 404 MTK_PIN_IES_SMT_SPEC(199, 199, 0xb50, 1), 405 MTK_PIN_IES_SMT_SPEC(200, 202, 0xb70, 1), 406 MTK_PIN_IES_SMT_SPEC(203, 207, 0xb70, 2), 407 MTK_PIN_IES_SMT_SPEC(208, 209, 0xb70, 3), 408 MTK_PIN_IES_SMT_SPEC(210, 210, 0xb70, 4), 409 MTK_PIN_IES_SMT_SPEC(211, 235, 0xb70, 5), 410 MTK_PIN_IES_SMT_SPEC(236, 241, 0xb70, 6), 411 MTK_PIN_IES_SMT_SPEC(242, 243, 0xb70, 7), 412 MTK_PIN_IES_SMT_SPEC(244, 247, 0xb70, 8), 413 MTK_PIN_IES_SMT_SPEC(248, 248, 0xb70, 9), 414 MTK_PIN_IES_SMT_SPEC(249, 249, 0x140, 3), 415 MTK_PIN_IES_SMT_SPEC(250, 250, 0x130, 15), 416 MTK_PIN_IES_SMT_SPEC(251, 251, 0x130, 11), 417 MTK_PIN_IES_SMT_SPEC(252, 252, 0x130, 7), 418 MTK_PIN_IES_SMT_SPEC(253, 253, 0x130, 3), 419 MTK_PIN_IES_SMT_SPEC(254, 254, 0xf40, 15), 420 MTK_PIN_IES_SMT_SPEC(255, 255, 0xf40, 11), 421 MTK_PIN_IES_SMT_SPEC(256, 256, 0xf40, 7), 422 MTK_PIN_IES_SMT_SPEC(257, 257, 0xf40, 3), 423 MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 11), 424 MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 11), 425 MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 11), 426 MTK_PIN_IES_SMT_SPEC(261, 261, 0x0b0, 3), 427 MTK_PIN_IES_SMT_SPEC(262, 277, 0xb70, 12), 428 MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13), 429}; 430 431static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = { 432 MTK_PINMUX_SPEC(22, 0xb10, 3), 433 MTK_PINMUX_SPEC(23, 0xb10, 4), 434 MTK_PINMUX_SPEC(24, 0xb10, 5), 435 MTK_PINMUX_SPEC(29, 0xb10, 9), 436 MTK_PINMUX_SPEC(208, 0xb10, 7), 437 MTK_PINMUX_SPEC(209, 0xb10, 8), 438 MTK_PINMUX_SPEC(203, 0xf20, 0), 439 MTK_PINMUX_SPEC(204, 0xf20, 1), 440 MTK_PINMUX_SPEC(249, 0xef0, 0), 441 MTK_PINMUX_SPEC(250, 0xef0, 0), 442 MTK_PINMUX_SPEC(251, 0xef0, 0), 443 MTK_PINMUX_SPEC(252, 0xef0, 0), 444 MTK_PINMUX_SPEC(253, 0xef0, 0), 445 MTK_PINMUX_SPEC(254, 0xef0, 0), 446 MTK_PINMUX_SPEC(255, 0xef0, 0), 447 MTK_PINMUX_SPEC(256, 0xef0, 0), 448 MTK_PINMUX_SPEC(257, 0xef0, 0), 449 MTK_PINMUX_SPEC(258, 0xef0, 0), 450 MTK_PINMUX_SPEC(259, 0xef0, 0), 451 MTK_PINMUX_SPEC(260, 0xef0, 0), 452}; 453 454static void mt2701_spec_pinmux_set(struct regmap *reg, unsigned int pin, 455 unsigned int mode) 456{ 457 unsigned int i, value, mask; 458 unsigned int info_num = ARRAY_SIZE(mt2701_spec_pinmux); 459 unsigned int spec_flag; 460 461 for (i = 0; i < info_num; i++) { 462 if (pin == mt2701_spec_pinmux[i].pin) 463 break; 464 } 465 466 if (i == info_num) 467 return; 468 469 spec_flag = (mode >> 3); 470 mask = BIT(mt2701_spec_pinmux[i].bit); 471 if (!spec_flag) 472 value = mask; 473 else 474 value = 0; 475 regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value); 476} 477 478static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int pin) 479{ 480 if (pin > 175) 481 *reg_addr += 0x10; 482} 483 484static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = { 485 .pins = mtk_pins_mt2701, 486 .npins = ARRAY_SIZE(mtk_pins_mt2701), 487 .grp_desc = mt2701_drv_grp, 488 .n_grp_cls = ARRAY_SIZE(mt2701_drv_grp), 489 .pin_drv_grp = mt2701_pin_drv, 490 .n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv), 491 .spec_ies = mt2701_ies_set, 492 .n_spec_ies = ARRAY_SIZE(mt2701_ies_set), 493 .spec_pupd = mt2701_spec_pupd, 494 .n_spec_pupd = ARRAY_SIZE(mt2701_spec_pupd), 495 .spec_smt = mt2701_smt_set, 496 .n_spec_smt = ARRAY_SIZE(mt2701_smt_set), 497 .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, 498 .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, 499 .spec_pinmux_set = mt2701_spec_pinmux_set, 500 .spec_dir_set = mt2701_spec_dir_set, 501 .dir_offset = 0x0000, 502 .pullen_offset = 0x0150, 503 .pullsel_offset = 0x0280, 504 .dout_offset = 0x0500, 505 .din_offset = 0x0630, 506 .pinmux_offset = 0x0760, 507 .type1_start = 280, 508 .type1_end = 280, 509 .port_shf = 4, 510 .port_mask = 0x1f, 511 .port_align = 4, 512 .mode_mask = 0xf, 513 .mode_per_reg = 5, 514 .mode_shf = 4, 515 .eint_hw = { 516 .port_mask = 6, 517 .ports = 6, 518 .ap_num = 169, 519 .db_cnt = 16, 520 .db_time = debounce_time_mt2701, 521 }, 522}; 523 524static const struct of_device_id mt2701_pctrl_match[] = { 525 { .compatible = "mediatek,mt2701-pinctrl", .data = &mt2701_pinctrl_data }, 526 { .compatible = "mediatek,mt7623-pinctrl", .data = &mt2701_pinctrl_data }, 527 {} 528}; 529MODULE_DEVICE_TABLE(of, mt2701_pctrl_match); 530 531static struct platform_driver mtk_pinctrl_driver = { 532 .probe = mtk_pctrl_common_probe, 533 .driver = { 534 .name = "mediatek-mt2701-pinctrl", 535 .of_match_table = mt2701_pctrl_match, 536 .pm = &mtk_eint_pm_ops, 537 }, 538}; 539 540static int __init mtk_pinctrl_init(void) 541{ 542 return platform_driver_register(&mtk_pinctrl_driver); 543} 544arch_initcall(mtk_pinctrl_init); 545