1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Intel Lynxpoint PCH pinctrl/GPIO driver 4 * 5 * Copyright (c) 2012, 2019, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Andy Shevchenko <andriy.shevchenko@linux.intel.com> 8 */ 9 10#include <linux/acpi.h> 11#include <linux/bitops.h> 12#include <linux/gpio/driver.h> 13#include <linux/interrupt.h> 14#include <linux/io.h> 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/platform_device.h> 18#include <linux/pm_runtime.h> 19#include <linux/seq_file.h> 20#include <linux/slab.h> 21#include <linux/types.h> 22 23#include <linux/pinctrl/consumer.h> 24#include <linux/pinctrl/pinconf-generic.h> 25#include <linux/pinctrl/pinconf.h> 26#include <linux/pinctrl/pinctrl.h> 27#include <linux/pinctrl/pinmux.h> 28 29#include "pinctrl-intel.h" 30 31#define COMMUNITY(p, n) \ 32 { \ 33 .pin_base = (p), \ 34 .npins = (n), \ 35 } 36 37static const struct pinctrl_pin_desc lptlp_pins[] = { 38 PINCTRL_PIN(0, "GP0_UART1_RXD"), 39 PINCTRL_PIN(1, "GP1_UART1_TXD"), 40 PINCTRL_PIN(2, "GP2_UART1_RTSB"), 41 PINCTRL_PIN(3, "GP3_UART1_CTSB"), 42 PINCTRL_PIN(4, "GP4_I2C0_SDA"), 43 PINCTRL_PIN(5, "GP5_I2C0_SCL"), 44 PINCTRL_PIN(6, "GP6_I2C1_SDA"), 45 PINCTRL_PIN(7, "GP7_I2C1_SCL"), 46 PINCTRL_PIN(8, "GP8"), 47 PINCTRL_PIN(9, "GP9"), 48 PINCTRL_PIN(10, "GP10"), 49 PINCTRL_PIN(11, "GP11_SMBALERTB"), 50 PINCTRL_PIN(12, "GP12_LANPHYPC"), 51 PINCTRL_PIN(13, "GP13"), 52 PINCTRL_PIN(14, "GP14"), 53 PINCTRL_PIN(15, "GP15"), 54 PINCTRL_PIN(16, "GP16_MGPIO9"), 55 PINCTRL_PIN(17, "GP17_MGPIO10"), 56 PINCTRL_PIN(18, "GP18_SRC0CLKRQB"), 57 PINCTRL_PIN(19, "GP19_SRC1CLKRQB"), 58 PINCTRL_PIN(20, "GP20_SRC2CLKRQB"), 59 PINCTRL_PIN(21, "GP21_SRC3CLKRQB"), 60 PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"), 61 PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"), 62 PINCTRL_PIN(24, "GP24_MGPIO0"), 63 PINCTRL_PIN(25, "GP25_USBWAKEOUTB"), 64 PINCTRL_PIN(26, "GP26_MGPIO5"), 65 PINCTRL_PIN(27, "GP27_MGPIO6"), 66 PINCTRL_PIN(28, "GP28_MGPIO7"), 67 PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"), 68 PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"), 69 PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"), 70 PINCTRL_PIN(32, "GP32_CLKRUNB"), 71 PINCTRL_PIN(33, "GP33_DEVSLP0"), 72 PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"), 73 PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"), 74 PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"), 75 PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"), 76 PINCTRL_PIN(38, "GP38_DEVSLP1"), 77 PINCTRL_PIN(39, "GP39_DEVSLP2"), 78 PINCTRL_PIN(40, "GP40_OC0B"), 79 PINCTRL_PIN(41, "GP41_OC1B"), 80 PINCTRL_PIN(42, "GP42_OC2B"), 81 PINCTRL_PIN(43, "GP43_OC3B"), 82 PINCTRL_PIN(44, "GP44"), 83 PINCTRL_PIN(45, "GP45_TMS2"), 84 PINCTRL_PIN(46, "GP46_TDO2"), 85 PINCTRL_PIN(47, "GP47"), 86 PINCTRL_PIN(48, "GP48"), 87 PINCTRL_PIN(49, "GP49"), 88 PINCTRL_PIN(50, "GP50"), 89 PINCTRL_PIN(51, "GP51_GSXDOUT"), 90 PINCTRL_PIN(52, "GP52_GSXSLOAD"), 91 PINCTRL_PIN(53, "GP53_GSXDIN"), 92 PINCTRL_PIN(54, "GP54_GSXSRESETB"), 93 PINCTRL_PIN(55, "GP55_GSXCLK"), 94 PINCTRL_PIN(56, "GP56"), 95 PINCTRL_PIN(57, "GP57"), 96 PINCTRL_PIN(58, "GP58"), 97 PINCTRL_PIN(59, "GP59"), 98 PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"), 99 PINCTRL_PIN(61, "GP61_SUS_STATB"), 100 PINCTRL_PIN(62, "GP62_SUSCLK"), 101 PINCTRL_PIN(63, "GP63_SLP_S5B"), 102 PINCTRL_PIN(64, "GP64_SDIO_CLK"), 103 PINCTRL_PIN(65, "GP65_SDIO_CMD"), 104 PINCTRL_PIN(66, "GP66_SDIO_D0"), 105 PINCTRL_PIN(67, "GP67_SDIO_D1"), 106 PINCTRL_PIN(68, "GP68_SDIO_D2"), 107 PINCTRL_PIN(69, "GP69_SDIO_D3"), 108 PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"), 109 PINCTRL_PIN(71, "GP71_MPHYPC"), 110 PINCTRL_PIN(72, "GP72_BATLOWB"), 111 PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"), 112 PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"), 113 PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"), 114 PINCTRL_PIN(76, "GP76_BMBUSYB"), 115 PINCTRL_PIN(77, "GP77_PIRQAB"), 116 PINCTRL_PIN(78, "GP78_PIRQBB"), 117 PINCTRL_PIN(79, "GP79_PIRQCB"), 118 PINCTRL_PIN(80, "GP80_PIRQDB"), 119 PINCTRL_PIN(81, "GP81_SPKR"), 120 PINCTRL_PIN(82, "GP82_RCINB"), 121 PINCTRL_PIN(83, "GP83_GSPI0_CSB"), 122 PINCTRL_PIN(84, "GP84_GSPI0_CLK"), 123 PINCTRL_PIN(85, "GP85_GSPI0_MISO"), 124 PINCTRL_PIN(86, "GP86_GSPI0_MOSI"), 125 PINCTRL_PIN(87, "GP87_GSPI1_CSB"), 126 PINCTRL_PIN(88, "GP88_GSPI1_CLK"), 127 PINCTRL_PIN(89, "GP89_GSPI1_MISO"), 128 PINCTRL_PIN(90, "GP90_GSPI1_MOSI"), 129 PINCTRL_PIN(91, "GP91_UART0_RXD"), 130 PINCTRL_PIN(92, "GP92_UART0_TXD"), 131 PINCTRL_PIN(93, "GP93_UART0_RTSB"), 132 PINCTRL_PIN(94, "GP94_UART0_CTSB"), 133}; 134 135static const struct intel_community lptlp_communities[] = { 136 COMMUNITY(0, 95), 137}; 138 139static const struct intel_pinctrl_soc_data lptlp_soc_data = { 140 .pins = lptlp_pins, 141 .npins = ARRAY_SIZE(lptlp_pins), 142 .communities = lptlp_communities, 143 .ncommunities = ARRAY_SIZE(lptlp_communities), 144}; 145 146/* LynxPoint chipset has support for 95 GPIO pins */ 147 148#define LP_NUM_GPIO 95 149 150/* Bitmapped register offsets */ 151#define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */ 152#define LP_IRQ2IOXAPIC 0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */ 153#define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */ 154#define LP_INT_STAT 0x80 155#define LP_INT_ENABLE 0x90 156 157/* Each pin has two 32 bit config registers, starting at 0x100 */ 158#define LP_CONFIG1 0x100 159#define LP_CONFIG2 0x104 160 161/* LP_CONFIG1 reg bits */ 162#define OUT_LVL_BIT BIT(31) 163#define IN_LVL_BIT BIT(30) 164#define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */ 165#define INT_INV_BIT BIT(3) /* Invert interrupt triggering */ 166#define DIR_BIT BIT(2) /* 0: Output, 1: Input */ 167#define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */ 168#define USE_SEL_NATIVE (0 << 0) 169#define USE_SEL_GPIO (1 << 0) 170 171/* LP_CONFIG2 reg bits */ 172#define GPINDIS_BIT BIT(2) /* disable input sensing */ 173#define GPIWP_MASK GENMASK(1, 0) /* weak pull options */ 174#define GPIWP_NONE 0 /* none */ 175#define GPIWP_DOWN 1 /* weak pull down */ 176#define GPIWP_UP 2 /* weak pull up */ 177 178/* 179 * Lynxpoint gpios are controlled through both bitmapped registers and 180 * per gpio specific registers. The bitmapped registers are in chunks of 181 * 3 x 32bit registers to cover all 95 GPIOs 182 * 183 * per gpio specific registers consist of two 32bit registers per gpio 184 * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of 185 * 190 config registers. 186 * 187 * A simplified view of the register layout look like this: 188 * 189 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers) 190 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63 191 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94 192 * ... 193 * LP_INT_ENABLE[31:0] ... 194 * LP_INT_ENABLE[63:32] ... 195 * LP_INT_ENABLE[94:64] ... 196 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers) 197 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0 198 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1 199 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1 200 * LP2_CONFIG1 (gpio 2) ... 201 * LP2_CONFIG2 (gpio 2) ... 202 * ... 203 * LP94_CONFIG1 (gpio 94) ... 204 * LP94_CONFIG2 (gpio 94) ... 205 * 206 * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55. 207 */ 208 209static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, 210 int reg) 211{ 212 struct intel_pinctrl *lg = gpiochip_get_data(chip); 213 struct intel_community *comm; 214 int reg_offset; 215 216 comm = intel_get_community(lg, offset); 217 if (!comm) 218 return NULL; 219 220 offset -= comm->pin_base; 221 222 if (reg == LP_CONFIG1 || reg == LP_CONFIG2) 223 /* per gpio specific config registers */ 224 reg_offset = offset * 8; 225 else 226 /* bitmapped registers */ 227 reg_offset = (offset / 32) * 4; 228 229 return comm->regs + reg_offset + reg; 230} 231 232static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin) 233{ 234 void __iomem *acpi_use; 235 236 acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED); 237 if (!acpi_use) 238 return true; 239 240 return !(ioread32(acpi_use) & BIT(pin % 32)); 241} 242 243static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset) 244{ 245 void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC); 246 u32 value; 247 248 value = ioread32(ioxapic_use); 249 250 if (offset >= 8 && offset <= 10) 251 return !!(value & BIT(offset - 8 + 0)); 252 if (offset >= 13 && offset <= 14) 253 return !!(value & BIT(offset - 13 + 3)); 254 if (offset >= 45 && offset <= 55) 255 return !!(value & BIT(offset - 45 + 5)); 256 257 return false; 258} 259 260static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 261 unsigned int pin) 262{ 263 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 264 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 265 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 266 u32 value, mode; 267 268 value = ioread32(reg); 269 270 mode = value & USE_SEL_MASK; 271 if (mode == USE_SEL_GPIO) 272 seq_puts(s, "GPIO "); 273 else 274 seq_printf(s, "mode %d ", mode); 275 276 seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2)); 277 278 if (lp_gpio_acpi_use(lg, pin)) 279 seq_puts(s, " [ACPI]"); 280} 281 282static const struct pinctrl_ops lptlp_pinctrl_ops = { 283 .get_groups_count = intel_get_groups_count, 284 .get_group_name = intel_get_group_name, 285 .get_group_pins = intel_get_group_pins, 286 .pin_dbg_show = lp_pin_dbg_show, 287}; 288 289static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev, 290 unsigned int function, unsigned int group) 291{ 292 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 293 const struct intel_pingroup *grp = &lg->soc->groups[group]; 294 unsigned long flags; 295 int i; 296 297 raw_spin_lock_irqsave(&lg->lock, flags); 298 299 /* Now enable the mux setting for each pin in the group */ 300 for (i = 0; i < grp->grp.npins; i++) { 301 void __iomem *reg = lp_gpio_reg(&lg->chip, grp->grp.pins[i], LP_CONFIG1); 302 u32 value; 303 304 value = ioread32(reg); 305 306 value &= ~USE_SEL_MASK; 307 if (grp->modes) 308 value |= grp->modes[i]; 309 else 310 value |= grp->mode; 311 312 iowrite32(value, reg); 313 } 314 315 raw_spin_unlock_irqrestore(&lg->lock, flags); 316 317 return 0; 318} 319 320static void lp_gpio_enable_input(void __iomem *reg) 321{ 322 iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg); 323} 324 325static void lp_gpio_disable_input(void __iomem *reg) 326{ 327 iowrite32(ioread32(reg) | GPINDIS_BIT, reg); 328} 329 330static int lp_gpio_request_enable(struct pinctrl_dev *pctldev, 331 struct pinctrl_gpio_range *range, 332 unsigned int pin) 333{ 334 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 335 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 336 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 337 unsigned long flags; 338 u32 value; 339 340 pm_runtime_get(lg->dev); 341 342 raw_spin_lock_irqsave(&lg->lock, flags); 343 344 /* 345 * Reconfigure pin to GPIO mode if needed and issue a warning, 346 * since we expect firmware to configure it properly. 347 */ 348 value = ioread32(reg); 349 if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { 350 iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); 351 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin); 352 } 353 354 /* Enable input sensing */ 355 lp_gpio_enable_input(conf2); 356 357 raw_spin_unlock_irqrestore(&lg->lock, flags); 358 359 return 0; 360} 361 362static void lp_gpio_disable_free(struct pinctrl_dev *pctldev, 363 struct pinctrl_gpio_range *range, 364 unsigned int pin) 365{ 366 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 367 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 368 unsigned long flags; 369 370 raw_spin_lock_irqsave(&lg->lock, flags); 371 372 /* Disable input sensing */ 373 lp_gpio_disable_input(conf2); 374 375 raw_spin_unlock_irqrestore(&lg->lock, flags); 376 377 pm_runtime_put(lg->dev); 378} 379 380static int lp_gpio_set_direction(struct pinctrl_dev *pctldev, 381 struct pinctrl_gpio_range *range, 382 unsigned int pin, bool input) 383{ 384 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 385 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 386 unsigned long flags; 387 u32 value; 388 389 raw_spin_lock_irqsave(&lg->lock, flags); 390 391 value = ioread32(reg); 392 value &= ~DIR_BIT; 393 if (input) { 394 value |= DIR_BIT; 395 } else { 396 /* 397 * Before making any direction modifications, do a check if GPIO 398 * is set for direct IRQ. On Lynxpoint, setting GPIO to output 399 * does not make sense, so let's at least warn the caller before 400 * they shoot themselves in the foot. 401 */ 402 WARN(lp_gpio_ioxapic_use(&lg->chip, pin), 403 "Potential Error: Setting GPIO to output with IOxAPIC redirection"); 404 } 405 iowrite32(value, reg); 406 407 raw_spin_unlock_irqrestore(&lg->lock, flags); 408 409 return 0; 410} 411 412static const struct pinmux_ops lptlp_pinmux_ops = { 413 .get_functions_count = intel_get_functions_count, 414 .get_function_name = intel_get_function_name, 415 .get_function_groups = intel_get_function_groups, 416 .set_mux = lp_pinmux_set_mux, 417 .gpio_request_enable = lp_gpio_request_enable, 418 .gpio_disable_free = lp_gpio_disable_free, 419 .gpio_set_direction = lp_gpio_set_direction, 420}; 421 422static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 423 unsigned long *config) 424{ 425 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 426 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 427 enum pin_config_param param = pinconf_to_config_param(*config); 428 unsigned long flags; 429 u32 value, pull; 430 u16 arg; 431 432 raw_spin_lock_irqsave(&lg->lock, flags); 433 value = ioread32(conf2); 434 raw_spin_unlock_irqrestore(&lg->lock, flags); 435 436 pull = value & GPIWP_MASK; 437 438 switch (param) { 439 case PIN_CONFIG_BIAS_DISABLE: 440 if (pull != GPIWP_NONE) 441 return -EINVAL; 442 arg = 0; 443 break; 444 case PIN_CONFIG_BIAS_PULL_DOWN: 445 if (pull != GPIWP_DOWN) 446 return -EINVAL; 447 448 arg = 1; 449 break; 450 case PIN_CONFIG_BIAS_PULL_UP: 451 if (pull != GPIWP_UP) 452 return -EINVAL; 453 454 arg = 1; 455 break; 456 default: 457 return -ENOTSUPP; 458 } 459 460 *config = pinconf_to_config_packed(param, arg); 461 462 return 0; 463} 464 465static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 466 unsigned long *configs, unsigned int num_configs) 467{ 468 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 469 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 470 enum pin_config_param param; 471 unsigned long flags; 472 int i, ret = 0; 473 u32 value; 474 475 raw_spin_lock_irqsave(&lg->lock, flags); 476 477 value = ioread32(conf2); 478 479 for (i = 0; i < num_configs; i++) { 480 param = pinconf_to_config_param(configs[i]); 481 482 switch (param) { 483 case PIN_CONFIG_BIAS_DISABLE: 484 value &= ~GPIWP_MASK; 485 value |= GPIWP_NONE; 486 break; 487 case PIN_CONFIG_BIAS_PULL_DOWN: 488 value &= ~GPIWP_MASK; 489 value |= GPIWP_DOWN; 490 break; 491 case PIN_CONFIG_BIAS_PULL_UP: 492 value &= ~GPIWP_MASK; 493 value |= GPIWP_UP; 494 break; 495 default: 496 ret = -ENOTSUPP; 497 } 498 499 if (ret) 500 break; 501 } 502 503 if (!ret) 504 iowrite32(value, conf2); 505 506 raw_spin_unlock_irqrestore(&lg->lock, flags); 507 508 return ret; 509} 510 511static const struct pinconf_ops lptlp_pinconf_ops = { 512 .is_generic = true, 513 .pin_config_get = lp_pin_config_get, 514 .pin_config_set = lp_pin_config_set, 515}; 516 517static const struct pinctrl_desc lptlp_pinctrl_desc = { 518 .pctlops = &lptlp_pinctrl_ops, 519 .pmxops = &lptlp_pinmux_ops, 520 .confops = &lptlp_pinconf_ops, 521 .owner = THIS_MODULE, 522}; 523 524static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset) 525{ 526 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 527 return !!(ioread32(reg) & IN_LVL_BIT); 528} 529 530static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 531{ 532 struct intel_pinctrl *lg = gpiochip_get_data(chip); 533 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 534 unsigned long flags; 535 536 raw_spin_lock_irqsave(&lg->lock, flags); 537 538 if (value) 539 iowrite32(ioread32(reg) | OUT_LVL_BIT, reg); 540 else 541 iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg); 542 543 raw_spin_unlock_irqrestore(&lg->lock, flags); 544} 545 546static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 547{ 548 return pinctrl_gpio_direction_input(chip->base + offset); 549} 550 551static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 552 int value) 553{ 554 lp_gpio_set(chip, offset, value); 555 556 return pinctrl_gpio_direction_output(chip->base + offset); 557} 558 559static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 560{ 561 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 562 563 if (ioread32(reg) & DIR_BIT) 564 return GPIO_LINE_DIRECTION_IN; 565 566 return GPIO_LINE_DIRECTION_OUT; 567} 568 569static void lp_gpio_irq_handler(struct irq_desc *desc) 570{ 571 struct irq_data *data = irq_desc_get_irq_data(desc); 572 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 573 struct intel_pinctrl *lg = gpiochip_get_data(gc); 574 struct irq_chip *chip = irq_data_get_irq_chip(data); 575 void __iomem *reg, *ena; 576 unsigned long pending; 577 u32 base, pin; 578 579 /* check from GPIO controller which pin triggered the interrupt */ 580 for (base = 0; base < lg->chip.ngpio; base += 32) { 581 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 582 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 583 584 /* Only interrupts that are enabled */ 585 pending = ioread32(reg) & ioread32(ena); 586 587 for_each_set_bit(pin, &pending, 32) 588 generic_handle_domain_irq(lg->chip.irq.domain, base + pin); 589 } 590 chip->irq_eoi(data); 591} 592 593static void lp_irq_ack(struct irq_data *d) 594{ 595 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 596 struct intel_pinctrl *lg = gpiochip_get_data(gc); 597 irq_hw_number_t hwirq = irqd_to_hwirq(d); 598 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT); 599 unsigned long flags; 600 601 raw_spin_lock_irqsave(&lg->lock, flags); 602 iowrite32(BIT(hwirq % 32), reg); 603 raw_spin_unlock_irqrestore(&lg->lock, flags); 604} 605 606static void lp_irq_unmask(struct irq_data *d) 607{ 608} 609 610static void lp_irq_mask(struct irq_data *d) 611{ 612} 613 614static void lp_irq_enable(struct irq_data *d) 615{ 616 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 617 struct intel_pinctrl *lg = gpiochip_get_data(gc); 618 irq_hw_number_t hwirq = irqd_to_hwirq(d); 619 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 620 unsigned long flags; 621 622 gpiochip_enable_irq(gc, hwirq); 623 624 raw_spin_lock_irqsave(&lg->lock, flags); 625 iowrite32(ioread32(reg) | BIT(hwirq % 32), reg); 626 raw_spin_unlock_irqrestore(&lg->lock, flags); 627} 628 629static void lp_irq_disable(struct irq_data *d) 630{ 631 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 632 struct intel_pinctrl *lg = gpiochip_get_data(gc); 633 irq_hw_number_t hwirq = irqd_to_hwirq(d); 634 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 635 unsigned long flags; 636 637 raw_spin_lock_irqsave(&lg->lock, flags); 638 iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg); 639 raw_spin_unlock_irqrestore(&lg->lock, flags); 640 641 gpiochip_disable_irq(gc, hwirq); 642} 643 644static int lp_irq_set_type(struct irq_data *d, unsigned int type) 645{ 646 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 647 struct intel_pinctrl *lg = gpiochip_get_data(gc); 648 irq_hw_number_t hwirq = irqd_to_hwirq(d); 649 unsigned long flags; 650 void __iomem *reg; 651 u32 value; 652 653 reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); 654 if (!reg) 655 return -EINVAL; 656 657 /* Fail if BIOS reserved pin for ACPI use */ 658 if (lp_gpio_acpi_use(lg, hwirq)) { 659 dev_err(lg->dev, "pin %lu can't be used as IRQ\n", hwirq); 660 return -EBUSY; 661 } 662 663 raw_spin_lock_irqsave(&lg->lock, flags); 664 value = ioread32(reg); 665 666 /* set both TRIG_SEL and INV bits to 0 for rising edge */ 667 if (type & IRQ_TYPE_EDGE_RISING) 668 value &= ~(TRIG_SEL_BIT | INT_INV_BIT); 669 670 /* TRIG_SEL bit 0, INV bit 1 for falling edge */ 671 if (type & IRQ_TYPE_EDGE_FALLING) 672 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT; 673 674 /* TRIG_SEL bit 1, INV bit 0 for level low */ 675 if (type & IRQ_TYPE_LEVEL_LOW) 676 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT; 677 678 /* TRIG_SEL bit 1, INV bit 1 for level high */ 679 if (type & IRQ_TYPE_LEVEL_HIGH) 680 value |= TRIG_SEL_BIT | INT_INV_BIT; 681 682 iowrite32(value, reg); 683 684 if (type & IRQ_TYPE_EDGE_BOTH) 685 irq_set_handler_locked(d, handle_edge_irq); 686 else if (type & IRQ_TYPE_LEVEL_MASK) 687 irq_set_handler_locked(d, handle_level_irq); 688 689 raw_spin_unlock_irqrestore(&lg->lock, flags); 690 691 return 0; 692} 693 694static const struct irq_chip lp_irqchip = { 695 .name = "LP-GPIO", 696 .irq_ack = lp_irq_ack, 697 .irq_mask = lp_irq_mask, 698 .irq_unmask = lp_irq_unmask, 699 .irq_enable = lp_irq_enable, 700 .irq_disable = lp_irq_disable, 701 .irq_set_type = lp_irq_set_type, 702 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 703 GPIOCHIP_IRQ_RESOURCE_HELPERS, 704}; 705 706static int lp_gpio_irq_init_hw(struct gpio_chip *chip) 707{ 708 struct intel_pinctrl *lg = gpiochip_get_data(chip); 709 void __iomem *reg; 710 unsigned int base; 711 712 for (base = 0; base < lg->chip.ngpio; base += 32) { 713 /* disable gpio pin interrupts */ 714 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 715 iowrite32(0, reg); 716 /* Clear interrupt status register */ 717 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 718 iowrite32(0xffffffff, reg); 719 } 720 721 return 0; 722} 723 724static int lp_gpio_add_pin_ranges(struct gpio_chip *chip) 725{ 726 struct intel_pinctrl *lg = gpiochip_get_data(chip); 727 struct device *dev = lg->dev; 728 int ret; 729 730 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins); 731 if (ret) 732 dev_err(dev, "failed to add GPIO pin range\n"); 733 734 return ret; 735} 736 737static int lp_gpio_probe(struct platform_device *pdev) 738{ 739 const struct intel_pinctrl_soc_data *soc; 740 struct intel_pinctrl *lg; 741 struct gpio_chip *gc; 742 struct device *dev = &pdev->dev; 743 struct resource *io_rc; 744 void __iomem *regs; 745 unsigned int i; 746 int irq, ret; 747 748 soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev); 749 if (!soc) 750 return -ENODEV; 751 752 lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL); 753 if (!lg) 754 return -ENOMEM; 755 756 lg->dev = dev; 757 lg->soc = soc; 758 759 lg->ncommunities = lg->soc->ncommunities; 760 lg->communities = devm_kcalloc(dev, lg->ncommunities, 761 sizeof(*lg->communities), GFP_KERNEL); 762 if (!lg->communities) 763 return -ENOMEM; 764 765 lg->pctldesc = lptlp_pinctrl_desc; 766 lg->pctldesc.name = dev_name(dev); 767 lg->pctldesc.pins = lg->soc->pins; 768 lg->pctldesc.npins = lg->soc->npins; 769 770 lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg); 771 if (IS_ERR(lg->pctldev)) { 772 dev_err(dev, "failed to register pinctrl driver\n"); 773 return PTR_ERR(lg->pctldev); 774 } 775 776 platform_set_drvdata(pdev, lg); 777 778 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); 779 if (!io_rc) { 780 dev_err(dev, "missing IO resources\n"); 781 return -EINVAL; 782 } 783 784 regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc)); 785 if (!regs) { 786 dev_err(dev, "failed mapping IO region %pR\n", &io_rc); 787 return -EBUSY; 788 } 789 790 for (i = 0; i < lg->soc->ncommunities; i++) { 791 struct intel_community *comm = &lg->communities[i]; 792 793 *comm = lg->soc->communities[i]; 794 795 comm->regs = regs; 796 comm->pad_regs = regs + 0x100; 797 } 798 799 raw_spin_lock_init(&lg->lock); 800 801 gc = &lg->chip; 802 gc->label = dev_name(dev); 803 gc->owner = THIS_MODULE; 804 gc->request = gpiochip_generic_request; 805 gc->free = gpiochip_generic_free; 806 gc->direction_input = lp_gpio_direction_input; 807 gc->direction_output = lp_gpio_direction_output; 808 gc->get = lp_gpio_get; 809 gc->set = lp_gpio_set; 810 gc->set_config = gpiochip_generic_config; 811 gc->get_direction = lp_gpio_get_direction; 812 gc->base = -1; 813 gc->ngpio = LP_NUM_GPIO; 814 gc->can_sleep = false; 815 gc->add_pin_ranges = lp_gpio_add_pin_ranges; 816 gc->parent = dev; 817 818 /* set up interrupts */ 819 irq = platform_get_irq_optional(pdev, 0); 820 if (irq > 0) { 821 struct gpio_irq_chip *girq; 822 823 girq = &gc->irq; 824 gpio_irq_chip_set_chip(girq, &lp_irqchip); 825 girq->init_hw = lp_gpio_irq_init_hw; 826 girq->parent_handler = lp_gpio_irq_handler; 827 girq->num_parents = 1; 828 girq->parents = devm_kcalloc(dev, girq->num_parents, 829 sizeof(*girq->parents), 830 GFP_KERNEL); 831 if (!girq->parents) 832 return -ENOMEM; 833 girq->parents[0] = irq; 834 girq->default_type = IRQ_TYPE_NONE; 835 girq->handler = handle_bad_irq; 836 } 837 838 ret = devm_gpiochip_add_data(dev, gc, lg); 839 if (ret) { 840 dev_err(dev, "failed adding lp-gpio chip\n"); 841 return ret; 842 } 843 844 pm_runtime_enable(dev); 845 846 return 0; 847} 848 849static int lp_gpio_remove(struct platform_device *pdev) 850{ 851 pm_runtime_disable(&pdev->dev); 852 return 0; 853} 854 855static int lp_gpio_runtime_suspend(struct device *dev) 856{ 857 return 0; 858} 859 860static int lp_gpio_runtime_resume(struct device *dev) 861{ 862 return 0; 863} 864 865static int lp_gpio_resume(struct device *dev) 866{ 867 struct intel_pinctrl *lg = dev_get_drvdata(dev); 868 struct gpio_chip *chip = &lg->chip; 869 const char *dummy; 870 int i; 871 872 /* on some hardware suspend clears input sensing, re-enable it here */ 873 for_each_requested_gpio(chip, i, dummy) 874 lp_gpio_enable_input(lp_gpio_reg(chip, i, LP_CONFIG2)); 875 876 return 0; 877} 878 879static const struct dev_pm_ops lp_gpio_pm_ops = { 880 SYSTEM_SLEEP_PM_OPS(NULL, lp_gpio_resume) 881 RUNTIME_PM_OPS(lp_gpio_runtime_suspend, lp_gpio_runtime_resume, NULL) 882}; 883 884static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = { 885 { "INT33C7", (kernel_ulong_t)&lptlp_soc_data }, 886 { "INT3437", (kernel_ulong_t)&lptlp_soc_data }, 887 { } 888}; 889MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match); 890 891static struct platform_driver lp_gpio_driver = { 892 .probe = lp_gpio_probe, 893 .remove = lp_gpio_remove, 894 .driver = { 895 .name = "lp_gpio", 896 .pm = pm_ptr(&lp_gpio_pm_ops), 897 .acpi_match_table = lynxpoint_gpio_acpi_match, 898 }, 899}; 900 901static int __init lp_gpio_init(void) 902{ 903 return platform_driver_register(&lp_gpio_driver); 904} 905subsys_initcall(lp_gpio_init); 906 907static void __exit lp_gpio_exit(void) 908{ 909 platform_driver_unregister(&lp_gpio_driver); 910} 911module_exit(lp_gpio_exit); 912 913MODULE_AUTHOR("Mathias Nyman (Intel)"); 914MODULE_AUTHOR("Andy Shevchenko (Intel)"); 915MODULE_DESCRIPTION("Intel Lynxpoint pinctrl driver"); 916MODULE_LICENSE("GPL v2"); 917MODULE_ALIAS("platform:lp_gpio"); 918MODULE_IMPORT_NS(PINCTRL_INTEL); 919