1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Intel Gemini Lake SoC pinctrl/GPIO driver 4 * 5 * Copyright (C) 2017 Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 */ 8 9#include <linux/mod_devicetable.h> 10#include <linux/module.h> 11#include <linux/platform_device.h> 12 13#include <linux/pinctrl/pinctrl.h> 14 15#include "pinctrl-intel.h" 16 17#define GLK_PAD_OWN 0x020 18#define GLK_PADCFGLOCK 0x080 19#define GLK_HOSTSW_OWN 0x0b0 20#define GLK_GPI_IS 0x100 21#define GLK_GPI_IE 0x110 22 23#define GLK_COMMUNITY(b, s, e) \ 24 INTEL_COMMUNITY_SIZE(b, s, e, 32, 4, GLK) 25 26/* GLK */ 27static const struct pinctrl_pin_desc glk_northwest_pins[] = { 28 PINCTRL_PIN(0, "TCK"), 29 PINCTRL_PIN(1, "TRST_B"), 30 PINCTRL_PIN(2, "TMS"), 31 PINCTRL_PIN(3, "TDI"), 32 PINCTRL_PIN(4, "TDO"), 33 PINCTRL_PIN(5, "JTAGX"), 34 PINCTRL_PIN(6, "CX_PREQ_B"), 35 PINCTRL_PIN(7, "CX_PRDY_B"), 36 PINCTRL_PIN(8, "GPIO_8"), 37 PINCTRL_PIN(9, "GPIO_9"), 38 PINCTRL_PIN(10, "GPIO_10"), 39 PINCTRL_PIN(11, "GPIO_11"), 40 PINCTRL_PIN(12, "GPIO_12"), 41 PINCTRL_PIN(13, "GPIO_13"), 42 PINCTRL_PIN(14, "GPIO_14"), 43 PINCTRL_PIN(15, "GPIO_15"), 44 PINCTRL_PIN(16, "GPIO_16"), 45 PINCTRL_PIN(17, "GPIO_17"), 46 PINCTRL_PIN(18, "GPIO_18"), 47 PINCTRL_PIN(19, "GPIO_19"), 48 PINCTRL_PIN(20, "GPIO_20"), 49 PINCTRL_PIN(21, "GPIO_21"), 50 PINCTRL_PIN(22, "GPIO_22"), 51 PINCTRL_PIN(23, "GPIO_23"), 52 PINCTRL_PIN(24, "GPIO_24"), 53 PINCTRL_PIN(25, "GPIO_25"), 54 PINCTRL_PIN(26, "ISH_GPIO_0"), 55 PINCTRL_PIN(27, "ISH_GPIO_1"), 56 PINCTRL_PIN(28, "ISH_GPIO_2"), 57 PINCTRL_PIN(29, "ISH_GPIO_3"), 58 PINCTRL_PIN(30, "ISH_GPIO_4"), 59 PINCTRL_PIN(31, "ISH_GPIO_5"), 60 PINCTRL_PIN(32, "ISH_GPIO_6"), 61 PINCTRL_PIN(33, "ISH_GPIO_7"), 62 PINCTRL_PIN(34, "ISH_GPIO_8"), 63 PINCTRL_PIN(35, "ISH_GPIO_9"), 64 PINCTRL_PIN(36, "GPIO_36"), 65 PINCTRL_PIN(37, "GPIO_37"), 66 PINCTRL_PIN(38, "GPIO_38"), 67 PINCTRL_PIN(39, "GPIO_39"), 68 PINCTRL_PIN(40, "GPIO_40"), 69 PINCTRL_PIN(41, "GPIO_41"), 70 PINCTRL_PIN(42, "GP_INTD_DSI_TE1"), 71 PINCTRL_PIN(43, "GP_INTD_DSI_TE2"), 72 PINCTRL_PIN(44, "USB_OC0_B"), 73 PINCTRL_PIN(45, "USB_OC1_B"), 74 PINCTRL_PIN(46, "DSI_I2C_SDA"), 75 PINCTRL_PIN(47, "DSI_I2C_SCL"), 76 PINCTRL_PIN(48, "PMC_I2C_SDA"), 77 PINCTRL_PIN(49, "PMC_I2C_SCL"), 78 PINCTRL_PIN(50, "LPSS_I2C0_SDA"), 79 PINCTRL_PIN(51, "LPSS_I2C0_SCL"), 80 PINCTRL_PIN(52, "LPSS_I2C1_SDA"), 81 PINCTRL_PIN(53, "LPSS_I2C1_SCL"), 82 PINCTRL_PIN(54, "LPSS_I2C2_SDA"), 83 PINCTRL_PIN(55, "LPSS_I2C2_SCL"), 84 PINCTRL_PIN(56, "LPSS_I2C3_SDA"), 85 PINCTRL_PIN(57, "LPSS_I2C3_SCL"), 86 PINCTRL_PIN(58, "LPSS_I2C4_SDA"), 87 PINCTRL_PIN(59, "LPSS_I2C4_SCL"), 88 PINCTRL_PIN(60, "LPSS_UART0_RXD"), 89 PINCTRL_PIN(61, "LPSS_UART0_TXD"), 90 PINCTRL_PIN(62, "LPSS_UART0_RTS_B"), 91 PINCTRL_PIN(63, "LPSS_UART0_CTS_B"), 92 PINCTRL_PIN(64, "LPSS_UART2_RXD"), 93 PINCTRL_PIN(65, "LPSS_UART2_TXD"), 94 PINCTRL_PIN(66, "LPSS_UART2_RTS_B"), 95 PINCTRL_PIN(67, "LPSS_UART2_CTS_B"), 96 PINCTRL_PIN(68, "PMC_SPI_FS0"), 97 PINCTRL_PIN(69, "PMC_SPI_FS1"), 98 PINCTRL_PIN(70, "PMC_SPI_FS2"), 99 PINCTRL_PIN(71, "PMC_SPI_RXD"), 100 PINCTRL_PIN(72, "PMC_SPI_TXD"), 101 PINCTRL_PIN(73, "PMC_SPI_CLK"), 102 PINCTRL_PIN(74, "THERMTRIP_B"), 103 PINCTRL_PIN(75, "PROCHOT_B"), 104 PINCTRL_PIN(76, "EMMC_RST_B"), 105 PINCTRL_PIN(77, "GPIO_212"), 106 PINCTRL_PIN(78, "GPIO_213"), 107 PINCTRL_PIN(79, "GPIO_214"), 108}; 109 110static const unsigned int glk_northwest_uart1_pins[] = { 26, 27, 28, 29 }; 111static const unsigned int glk_northwest_pwm0_pins[] = { 42 }; 112static const unsigned int glk_northwest_pwm1_pins[] = { 43 }; 113static const unsigned int glk_northwest_pwm2_pins[] = { 44 }; 114static const unsigned int glk_northwest_pwm3_pins[] = { 45 }; 115static const unsigned int glk_northwest_i2c0_pins[] = { 50, 51 }; 116static const unsigned int glk_northwest_i2c1_pins[] = { 52, 53 }; 117static const unsigned int glk_northwest_i2c2_pins[] = { 54, 55 }; 118static const unsigned int glk_northwest_i2c3_pins[] = { 56, 57 }; 119static const unsigned int glk_northwest_i2c4_pins[] = { 58, 59 }; 120static const unsigned int glk_northwest_uart0_pins[] = { 60, 61, 62, 63 }; 121static const unsigned int glk_northwest_uart2_pins[] = { 64, 65, 66, 67 }; 122 123static const struct intel_pingroup glk_northwest_groups[] = { 124 PIN_GROUP("uart1_grp", glk_northwest_uart1_pins, 2), 125 PIN_GROUP("pwm0_grp", glk_northwest_pwm0_pins, 2), 126 PIN_GROUP("pwm1_grp", glk_northwest_pwm1_pins, 2), 127 PIN_GROUP("pwm2_grp", glk_northwest_pwm2_pins, 2), 128 PIN_GROUP("pwm3_grp", glk_northwest_pwm3_pins, 2), 129 PIN_GROUP("i2c0_grp", glk_northwest_i2c0_pins, 1), 130 PIN_GROUP("i2c1_grp", glk_northwest_i2c1_pins, 1), 131 PIN_GROUP("i2c2_grp", glk_northwest_i2c2_pins, 1), 132 PIN_GROUP("i2c3_grp", glk_northwest_i2c3_pins, 1), 133 PIN_GROUP("i2c4_grp", glk_northwest_i2c4_pins, 1), 134 PIN_GROUP("uart0_grp", glk_northwest_uart0_pins, 1), 135 PIN_GROUP("uart2_grp", glk_northwest_uart2_pins, 1), 136}; 137 138static const char * const glk_northwest_uart1_groups[] = { "uart1_grp" }; 139static const char * const glk_northwest_pwm0_groups[] = { "pwm0_grp" }; 140static const char * const glk_northwest_pwm1_groups[] = { "pwm1_grp" }; 141static const char * const glk_northwest_pwm2_groups[] = { "pwm2_grp" }; 142static const char * const glk_northwest_pwm3_groups[] = { "pwm3_grp" }; 143static const char * const glk_northwest_i2c0_groups[] = { "i2c0_grp" }; 144static const char * const glk_northwest_i2c1_groups[] = { "i2c1_grp" }; 145static const char * const glk_northwest_i2c2_groups[] = { "i2c2_grp" }; 146static const char * const glk_northwest_i2c3_groups[] = { "i2c3_grp" }; 147static const char * const glk_northwest_i2c4_groups[] = { "i2c4_grp" }; 148static const char * const glk_northwest_uart0_groups[] = { "uart0_grp" }; 149static const char * const glk_northwest_uart2_groups[] = { "uart2_grp" }; 150 151static const struct intel_function glk_northwest_functions[] = { 152 FUNCTION("uart1", glk_northwest_uart1_groups), 153 FUNCTION("pmw0", glk_northwest_pwm0_groups), 154 FUNCTION("pmw1", glk_northwest_pwm1_groups), 155 FUNCTION("pmw2", glk_northwest_pwm2_groups), 156 FUNCTION("pmw3", glk_northwest_pwm3_groups), 157 FUNCTION("i2c0", glk_northwest_i2c0_groups), 158 FUNCTION("i2c1", glk_northwest_i2c1_groups), 159 FUNCTION("i2c2", glk_northwest_i2c2_groups), 160 FUNCTION("i2c3", glk_northwest_i2c3_groups), 161 FUNCTION("i2c4", glk_northwest_i2c4_groups), 162 FUNCTION("uart0", glk_northwest_uart0_groups), 163 FUNCTION("uart2", glk_northwest_uart2_groups), 164}; 165 166static const struct intel_community glk_northwest_communities[] = { 167 GLK_COMMUNITY(0, 0, 79), 168}; 169 170static const struct intel_pinctrl_soc_data glk_northwest_soc_data = { 171 .uid = "1", 172 .pins = glk_northwest_pins, 173 .npins = ARRAY_SIZE(glk_northwest_pins), 174 .groups = glk_northwest_groups, 175 .ngroups = ARRAY_SIZE(glk_northwest_groups), 176 .functions = glk_northwest_functions, 177 .nfunctions = ARRAY_SIZE(glk_northwest_functions), 178 .communities = glk_northwest_communities, 179 .ncommunities = ARRAY_SIZE(glk_northwest_communities), 180}; 181 182static const struct pinctrl_pin_desc glk_north_pins[] = { 183 PINCTRL_PIN(0, "SVID0_ALERT_B"), 184 PINCTRL_PIN(1, "SVID0_DATA"), 185 PINCTRL_PIN(2, "SVID0_CLK"), 186 PINCTRL_PIN(3, "LPSS_SPI_0_CLK"), 187 PINCTRL_PIN(4, "LPSS_SPI_0_FS0"), 188 PINCTRL_PIN(5, "LPSS_SPI_0_FS1"), 189 PINCTRL_PIN(6, "LPSS_SPI_0_RXD"), 190 PINCTRL_PIN(7, "LPSS_SPI_0_TXD"), 191 PINCTRL_PIN(8, "LPSS_SPI_2_CLK"), 192 PINCTRL_PIN(9, "LPSS_SPI_2_FS0"), 193 PINCTRL_PIN(10, "LPSS_SPI_2_FS1"), 194 PINCTRL_PIN(11, "LPSS_SPI_2_FS2"), 195 PINCTRL_PIN(12, "LPSS_SPI_2_RXD"), 196 PINCTRL_PIN(13, "LPSS_SPI_2_TXD"), 197 PINCTRL_PIN(14, "FST_SPI_CS0_B"), 198 PINCTRL_PIN(15, "FST_SPI_CS1_B"), 199 PINCTRL_PIN(16, "FST_SPI_MOSI_IO0"), 200 PINCTRL_PIN(17, "FST_SPI_MISO_IO1"), 201 PINCTRL_PIN(18, "FST_SPI_IO2"), 202 PINCTRL_PIN(19, "FST_SPI_IO3"), 203 PINCTRL_PIN(20, "FST_SPI_CLK"), 204 PINCTRL_PIN(21, "FST_SPI_CLK_FB"), 205 PINCTRL_PIN(22, "PMU_PLTRST_B"), 206 PINCTRL_PIN(23, "PMU_PWRBTN_B"), 207 PINCTRL_PIN(24, "PMU_SLP_S0_B"), 208 PINCTRL_PIN(25, "PMU_SLP_S3_B"), 209 PINCTRL_PIN(26, "PMU_SLP_S4_B"), 210 PINCTRL_PIN(27, "SUSPWRDNACK"), 211 PINCTRL_PIN(28, "EMMC_DNX_PWR_EN_B"), 212 PINCTRL_PIN(29, "GPIO_105"), 213 PINCTRL_PIN(30, "PMU_BATLOW_B"), 214 PINCTRL_PIN(31, "PMU_RESETBUTTON_B"), 215 PINCTRL_PIN(32, "PMU_SUSCLK"), 216 PINCTRL_PIN(33, "SUS_STAT_B"), 217 PINCTRL_PIN(34, "LPSS_I2C5_SDA"), 218 PINCTRL_PIN(35, "LPSS_I2C5_SCL"), 219 PINCTRL_PIN(36, "LPSS_I2C6_SDA"), 220 PINCTRL_PIN(37, "LPSS_I2C6_SCL"), 221 PINCTRL_PIN(38, "LPSS_I2C7_SDA"), 222 PINCTRL_PIN(39, "LPSS_I2C7_SCL"), 223 PINCTRL_PIN(40, "PCIE_WAKE0_B"), 224 PINCTRL_PIN(41, "PCIE_WAKE1_B"), 225 PINCTRL_PIN(42, "PCIE_WAKE2_B"), 226 PINCTRL_PIN(43, "PCIE_WAKE3_B"), 227 PINCTRL_PIN(44, "PCIE_CLKREQ0_B"), 228 PINCTRL_PIN(45, "PCIE_CLKREQ1_B"), 229 PINCTRL_PIN(46, "PCIE_CLKREQ2_B"), 230 PINCTRL_PIN(47, "PCIE_CLKREQ3_B"), 231 PINCTRL_PIN(48, "HV_DDI0_DDC_SDA"), 232 PINCTRL_PIN(49, "HV_DDI0_DDC_SCL"), 233 PINCTRL_PIN(50, "HV_DDI1_DDC_SDA"), 234 PINCTRL_PIN(51, "HV_DDI1_DDC_SCL"), 235 PINCTRL_PIN(52, "PANEL0_VDDEN"), 236 PINCTRL_PIN(53, "PANEL0_BKLTEN"), 237 PINCTRL_PIN(54, "PANEL0_BKLTCTL"), 238 PINCTRL_PIN(55, "HV_DDI0_HPD"), 239 PINCTRL_PIN(56, "HV_DDI1_HPD"), 240 PINCTRL_PIN(57, "HV_EDP_HPD"), 241 PINCTRL_PIN(58, "GPIO_134"), 242 PINCTRL_PIN(59, "GPIO_135"), 243 PINCTRL_PIN(60, "GPIO_136"), 244 PINCTRL_PIN(61, "GPIO_137"), 245 PINCTRL_PIN(62, "GPIO_138"), 246 PINCTRL_PIN(63, "GPIO_139"), 247 PINCTRL_PIN(64, "GPIO_140"), 248 PINCTRL_PIN(65, "GPIO_141"), 249 PINCTRL_PIN(66, "GPIO_142"), 250 PINCTRL_PIN(67, "GPIO_143"), 251 PINCTRL_PIN(68, "GPIO_144"), 252 PINCTRL_PIN(69, "GPIO_145"), 253 PINCTRL_PIN(70, "GPIO_146"), 254 PINCTRL_PIN(71, "LPC_ILB_SERIRQ"), 255 PINCTRL_PIN(72, "LPC_CLKOUT0"), 256 PINCTRL_PIN(73, "LPC_CLKOUT1"), 257 PINCTRL_PIN(74, "LPC_AD0"), 258 PINCTRL_PIN(75, "LPC_AD1"), 259 PINCTRL_PIN(76, "LPC_AD2"), 260 PINCTRL_PIN(77, "LPC_AD3"), 261 PINCTRL_PIN(78, "LPC_CLKRUNB"), 262 PINCTRL_PIN(79, "LPC_FRAMEB"), 263}; 264 265static const unsigned int glk_north_spi0_pins[] = { 3, 4, 5, 6, 7 }; 266static const unsigned int glk_north_spi1_pins[] = { 8, 9, 10, 11, 12, 13 }; 267static const unsigned int glk_north_i2c5_pins[] = { 34, 35 }; 268static const unsigned int glk_north_i2c6_pins[] = { 36, 37 }; 269static const unsigned int glk_north_i2c7_pins[] = { 38, 39 }; 270static const unsigned int glk_north_uart0_pins[] = { 62, 63, 64, 65 }; 271static const unsigned int glk_north_spi0b_pins[] = { 66, 67, 68, 69, 70 }; 272 273static const struct intel_pingroup glk_north_groups[] = { 274 PIN_GROUP("spi0_grp", glk_north_spi0_pins, 1), 275 PIN_GROUP("spi1_grp", glk_north_spi1_pins, 1), 276 PIN_GROUP("i2c5_grp", glk_north_i2c5_pins, 1), 277 PIN_GROUP("i2c6_grp", glk_north_i2c6_pins, 1), 278 PIN_GROUP("i2c7_grp", glk_north_i2c7_pins, 1), 279 PIN_GROUP("uart0_grp", glk_north_uart0_pins, 2), 280 PIN_GROUP("spi0b_grp", glk_north_spi0b_pins, 2), 281}; 282 283static const char * const glk_north_spi0_groups[] = { "spi0_grp", "spi0b_grp" }; 284static const char * const glk_north_spi1_groups[] = { "spi1_grp" }; 285static const char * const glk_north_i2c5_groups[] = { "i2c5_grp" }; 286static const char * const glk_north_i2c6_groups[] = { "i2c6_grp" }; 287static const char * const glk_north_i2c7_groups[] = { "i2c7_grp" }; 288static const char * const glk_north_uart0_groups[] = { "uart0_grp" }; 289 290static const struct intel_function glk_north_functions[] = { 291 FUNCTION("spi0", glk_north_spi0_groups), 292 FUNCTION("spi1", glk_north_spi1_groups), 293 FUNCTION("i2c5", glk_north_i2c5_groups), 294 FUNCTION("i2c6", glk_north_i2c6_groups), 295 FUNCTION("i2c7", glk_north_i2c7_groups), 296 FUNCTION("uart0", glk_north_uart0_groups), 297}; 298 299static const struct intel_community glk_north_communities[] = { 300 GLK_COMMUNITY(0, 0, 79), 301}; 302 303static const struct intel_pinctrl_soc_data glk_north_soc_data = { 304 .uid = "2", 305 .pins = glk_north_pins, 306 .npins = ARRAY_SIZE(glk_north_pins), 307 .groups = glk_north_groups, 308 .ngroups = ARRAY_SIZE(glk_north_groups), 309 .functions = glk_north_functions, 310 .nfunctions = ARRAY_SIZE(glk_north_functions), 311 .communities = glk_north_communities, 312 .ncommunities = ARRAY_SIZE(glk_north_communities), 313}; 314 315static const struct pinctrl_pin_desc glk_audio_pins[] = { 316 PINCTRL_PIN(0, "AVS_I2S0_MCLK"), 317 PINCTRL_PIN(1, "AVS_I2S0_BCLK"), 318 PINCTRL_PIN(2, "AVS_I2S0_WS_SYNC"), 319 PINCTRL_PIN(3, "AVS_I2S0_SDI"), 320 PINCTRL_PIN(4, "AVS_I2S0_SDO"), 321 PINCTRL_PIN(5, "AVS_I2S1_MCLK"), 322 PINCTRL_PIN(6, "AVS_I2S1_BCLK"), 323 PINCTRL_PIN(7, "AVS_I2S1_WS_SYNC"), 324 PINCTRL_PIN(8, "AVS_I2S1_SDI"), 325 PINCTRL_PIN(9, "AVS_I2S1_SDO"), 326 PINCTRL_PIN(10, "AVS_HDA_BCLK"), 327 PINCTRL_PIN(11, "AVS_HDA_WS_SYNC"), 328 PINCTRL_PIN(12, "AVS_HDA_SDI"), 329 PINCTRL_PIN(13, "AVS_HDA_SDO"), 330 PINCTRL_PIN(14, "AVS_HDA_RSTB"), 331 PINCTRL_PIN(15, "AVS_M_CLK_A1"), 332 PINCTRL_PIN(16, "AVS_M_CLK_B1"), 333 PINCTRL_PIN(17, "AVS_M_DATA_1"), 334 PINCTRL_PIN(18, "AVS_M_CLK_AB2"), 335 PINCTRL_PIN(19, "AVS_M_DATA_2"), 336}; 337 338static const struct intel_community glk_audio_communities[] = { 339 GLK_COMMUNITY(0, 0, 19), 340}; 341 342static const struct intel_pinctrl_soc_data glk_audio_soc_data = { 343 .uid = "3", 344 .pins = glk_audio_pins, 345 .npins = ARRAY_SIZE(glk_audio_pins), 346 .communities = glk_audio_communities, 347 .ncommunities = ARRAY_SIZE(glk_audio_communities), 348}; 349 350static const struct pinctrl_pin_desc glk_scc_pins[] = { 351 PINCTRL_PIN(0, "SMB_ALERTB"), 352 PINCTRL_PIN(1, "SMB_CLK"), 353 PINCTRL_PIN(2, "SMB_DATA"), 354 PINCTRL_PIN(3, "SDCARD_LVL_WP"), 355 PINCTRL_PIN(4, "SDCARD_CLK"), 356 PINCTRL_PIN(5, "SDCARD_CLK_FB"), 357 PINCTRL_PIN(6, "SDCARD_D0"), 358 PINCTRL_PIN(7, "SDCARD_D1"), 359 PINCTRL_PIN(8, "SDCARD_D2"), 360 PINCTRL_PIN(9, "SDCARD_D3"), 361 PINCTRL_PIN(10, "SDCARD_CMD"), 362 PINCTRL_PIN(11, "SDCARD_CD_B"), 363 PINCTRL_PIN(12, "SDCARD_PWR_DOWN_B"), 364 PINCTRL_PIN(13, "GPIO_210"), 365 PINCTRL_PIN(14, "OSC_CLK_OUT_0"), 366 PINCTRL_PIN(15, "OSC_CLK_OUT_1"), 367 PINCTRL_PIN(16, "CNV_BRI_DT"), 368 PINCTRL_PIN(17, "CNV_BRI_RSP"), 369 PINCTRL_PIN(18, "CNV_RGI_DT"), 370 PINCTRL_PIN(19, "CNV_RGI_RSP"), 371 PINCTRL_PIN(20, "CNV_RF_RESET_B"), 372 PINCTRL_PIN(21, "XTAL_CLKREQ"), 373 PINCTRL_PIN(22, "SDIO_CLK_FB"), 374 PINCTRL_PIN(23, "EMMC0_CLK"), 375 PINCTRL_PIN(24, "EMMC0_CLK_FB"), 376 PINCTRL_PIN(25, "EMMC0_D0"), 377 PINCTRL_PIN(26, "EMMC0_D1"), 378 PINCTRL_PIN(27, "EMMC0_D2"), 379 PINCTRL_PIN(28, "EMMC0_D3"), 380 PINCTRL_PIN(29, "EMMC0_D4"), 381 PINCTRL_PIN(30, "EMMC0_D5"), 382 PINCTRL_PIN(31, "EMMC0_D6"), 383 PINCTRL_PIN(32, "EMMC0_D7"), 384 PINCTRL_PIN(33, "EMMC0_CMD"), 385 PINCTRL_PIN(34, "EMMC0_STROBE"), 386}; 387 388static const unsigned int glk_scc_i2c7_pins[] = { 1, 2 }; 389static const unsigned int glk_scc_sdcard_pins[] = { 390 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 391}; 392static const unsigned int glk_scc_sdio_pins[] = { 16, 17, 18, 19, 20, 21, 22 }; 393static const unsigned int glk_scc_uart1_pins[] = { 16, 17, 18, 19 }; 394static const unsigned int glk_scc_emmc_pins[] = { 395 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 396}; 397 398static const struct intel_pingroup glk_scc_groups[] = { 399 PIN_GROUP("i2c7_grp", glk_scc_i2c7_pins, 2), 400 PIN_GROUP("sdcard_grp", glk_scc_sdcard_pins, 1), 401 PIN_GROUP("sdio_grp", glk_scc_sdio_pins, 2), 402 PIN_GROUP("uart1_grp", glk_scc_uart1_pins, 3), 403 PIN_GROUP("emmc_grp", glk_scc_emmc_pins, 1), 404}; 405 406static const char * const glk_scc_i2c7_groups[] = { "i2c7_grp" }; 407static const char * const glk_scc_sdcard_groups[] = { "sdcard_grp" }; 408static const char * const glk_scc_sdio_groups[] = { "sdio_grp" }; 409static const char * const glk_scc_uart1_groups[] = { "uart1_grp" }; 410static const char * const glk_scc_emmc_groups[] = { "emmc_grp" }; 411 412static const struct intel_function glk_scc_functions[] = { 413 FUNCTION("i2c7", glk_scc_i2c7_groups), 414 FUNCTION("sdcard", glk_scc_sdcard_groups), 415 FUNCTION("sdio", glk_scc_sdio_groups), 416 FUNCTION("uart1", glk_scc_uart1_groups), 417 FUNCTION("emmc", glk_scc_emmc_groups), 418}; 419 420static const struct intel_community glk_scc_communities[] = { 421 GLK_COMMUNITY(0, 0, 34), 422}; 423 424static const struct intel_pinctrl_soc_data glk_scc_soc_data = { 425 .uid = "4", 426 .pins = glk_scc_pins, 427 .npins = ARRAY_SIZE(glk_scc_pins), 428 .groups = glk_scc_groups, 429 .ngroups = ARRAY_SIZE(glk_scc_groups), 430 .functions = glk_scc_functions, 431 .nfunctions = ARRAY_SIZE(glk_scc_functions), 432 .communities = glk_scc_communities, 433 .ncommunities = ARRAY_SIZE(glk_scc_communities), 434}; 435 436static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = { 437 &glk_northwest_soc_data, 438 &glk_north_soc_data, 439 &glk_audio_soc_data, 440 &glk_scc_soc_data, 441 NULL 442}; 443 444static const struct acpi_device_id glk_pinctrl_acpi_match[] = { 445 { "INT3453", (kernel_ulong_t)glk_pinctrl_soc_data }, 446 { } 447}; 448MODULE_DEVICE_TABLE(acpi, glk_pinctrl_acpi_match); 449 450static INTEL_PINCTRL_PM_OPS(glk_pinctrl_pm_ops); 451 452static struct platform_driver glk_pinctrl_driver = { 453 .probe = intel_pinctrl_probe_by_uid, 454 .driver = { 455 .name = "geminilake-pinctrl", 456 .acpi_match_table = glk_pinctrl_acpi_match, 457 .pm = &glk_pinctrl_pm_ops, 458 }, 459}; 460 461static int __init glk_pinctrl_init(void) 462{ 463 return platform_driver_register(&glk_pinctrl_driver); 464} 465subsys_initcall(glk_pinctrl_init); 466 467static void __exit glk_pinctrl_exit(void) 468{ 469 platform_driver_unregister(&glk_pinctrl_driver); 470} 471module_exit(glk_pinctrl_exit); 472 473MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 474MODULE_DESCRIPTION("Intel Gemini Lake SoC pinctrl/GPIO driver"); 475MODULE_LICENSE("GPL v2"); 476MODULE_IMPORT_NS(PINCTRL_INTEL); 477