1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Intel Denverton SoC pinctrl/GPIO driver 4 * 5 * Copyright (C) 2017, Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 */ 8 9#include <linux/mod_devicetable.h> 10#include <linux/module.h> 11#include <linux/platform_device.h> 12 13#include <linux/pinctrl/pinctrl.h> 14 15#include "pinctrl-intel.h" 16 17#define DNV_PAD_OWN 0x020 18#define DNV_PADCFGLOCK 0x090 19#define DNV_HOSTSW_OWN 0x0C0 20#define DNV_GPI_IS 0x100 21#define DNV_GPI_IE 0x120 22 23#define DNV_GPP(n, s, e) \ 24 { \ 25 .reg_num = (n), \ 26 .base = (s), \ 27 .size = ((e) - (s) + 1), \ 28 } 29 30#define DNV_COMMUNITY(b, s, e, g) \ 31 INTEL_COMMUNITY_GPPS(b, s, e, g, DNV) 32 33/* Denverton */ 34static const struct pinctrl_pin_desc dnv_pins[] = { 35 /* North ALL */ 36 PINCTRL_PIN(0, "GBE0_SDP0"), 37 PINCTRL_PIN(1, "GBE1_SDP0"), 38 PINCTRL_PIN(2, "GBE0_SDP1"), 39 PINCTRL_PIN(3, "GBE1_SDP1"), 40 PINCTRL_PIN(4, "GBE0_SDP2"), 41 PINCTRL_PIN(5, "GBE1_SDP2"), 42 PINCTRL_PIN(6, "GBE0_SDP3"), 43 PINCTRL_PIN(7, "GBE1_SDP3"), 44 PINCTRL_PIN(8, "GBE2_LED0"), 45 PINCTRL_PIN(9, "GBE2_LED1"), 46 PINCTRL_PIN(10, "GBE0_I2C_CLK"), 47 PINCTRL_PIN(11, "GBE0_I2C_DATA"), 48 PINCTRL_PIN(12, "GBE1_I2C_CLK"), 49 PINCTRL_PIN(13, "GBE1_I2C_DATA"), 50 PINCTRL_PIN(14, "NCSI_RXD0"), 51 PINCTRL_PIN(15, "NCSI_CLK_IN"), 52 PINCTRL_PIN(16, "NCSI_RXD1"), 53 PINCTRL_PIN(17, "NCSI_CRS_DV"), 54 PINCTRL_PIN(18, "IDSLDO_VID_TICKLE"), 55 PINCTRL_PIN(19, "NCSI_TX_EN"), 56 PINCTRL_PIN(20, "NCSI_TXD0"), 57 PINCTRL_PIN(21, "NCSI_TXD1"), 58 PINCTRL_PIN(22, "NCSI_ARB_OUT"), 59 PINCTRL_PIN(23, "GBE0_LED0"), 60 PINCTRL_PIN(24, "GBE0_LED1"), 61 PINCTRL_PIN(25, "GBE1_LED0"), 62 PINCTRL_PIN(26, "GBE1_LED1"), 63 PINCTRL_PIN(27, "SPARE_0"), 64 PINCTRL_PIN(28, "PCIE_CLKREQ0_N"), 65 PINCTRL_PIN(29, "PCIE_CLKREQ1_N"), 66 PINCTRL_PIN(30, "PCIE_CLKREQ2_N"), 67 PINCTRL_PIN(31, "PCIE_CLKREQ3_N"), 68 PINCTRL_PIN(32, "PCIE_CLKREQ4_N"), 69 PINCTRL_PIN(33, "GBE_MDC"), 70 PINCTRL_PIN(34, "GBE_MDIO"), 71 PINCTRL_PIN(35, "SVID_ALERT_N"), 72 PINCTRL_PIN(36, "SVID_DATA"), 73 PINCTRL_PIN(37, "SVID_CLK"), 74 PINCTRL_PIN(38, "THERMTRIP_N"), 75 PINCTRL_PIN(39, "PROCHOT_N"), 76 PINCTRL_PIN(40, "MEMHOT_N"), 77 /* South DFX */ 78 PINCTRL_PIN(41, "DFX_PORT_CLK0"), 79 PINCTRL_PIN(42, "DFX_PORT_CLK1"), 80 PINCTRL_PIN(43, "DFX_PORT0"), 81 PINCTRL_PIN(44, "DFX_PORT1"), 82 PINCTRL_PIN(45, "DFX_PORT2"), 83 PINCTRL_PIN(46, "DFX_PORT3"), 84 PINCTRL_PIN(47, "DFX_PORT4"), 85 PINCTRL_PIN(48, "DFX_PORT5"), 86 PINCTRL_PIN(49, "DFX_PORT6"), 87 PINCTRL_PIN(50, "DFX_PORT7"), 88 PINCTRL_PIN(51, "DFX_PORT8"), 89 PINCTRL_PIN(52, "DFX_PORT9"), 90 PINCTRL_PIN(53, "DFX_PORT10"), 91 PINCTRL_PIN(54, "DFX_PORT11"), 92 PINCTRL_PIN(55, "DFX_PORT12"), 93 PINCTRL_PIN(56, "DFX_PORT13"), 94 PINCTRL_PIN(57, "DFX_PORT14"), 95 PINCTRL_PIN(58, "DFX_PORT15"), 96 /* South GPP0 */ 97 PINCTRL_PIN(59, "SPI_TPM_CS_N"), 98 PINCTRL_PIN(60, "UART2_CTS"), 99 PINCTRL_PIN(61, "PCIE_CLKREQ5_N"), 100 PINCTRL_PIN(62, "PCIE_CLKREQ6_N"), 101 PINCTRL_PIN(63, "PCIE_CLKREQ7_N"), 102 PINCTRL_PIN(64, "UART0_RXD"), 103 PINCTRL_PIN(65, "UART0_TXD"), 104 PINCTRL_PIN(66, "CPU_RESET_N"), 105 PINCTRL_PIN(67, "NMI"), 106 PINCTRL_PIN(68, "ERROR2_N"), 107 PINCTRL_PIN(69, "ERROR1_N"), 108 PINCTRL_PIN(70, "ERROR0_N"), 109 PINCTRL_PIN(71, "IERR_N"), 110 PINCTRL_PIN(72, "MCERR_N"), 111 PINCTRL_PIN(73, "SMB0_LEG_CLK"), 112 PINCTRL_PIN(74, "SMB0_LEG_DATA"), 113 PINCTRL_PIN(75, "SMB0_LEG_ALRT_N"), 114 PINCTRL_PIN(76, "SMB1_HOST_DATA"), 115 PINCTRL_PIN(77, "SMB1_HOST_CLK"), 116 PINCTRL_PIN(78, "SMB2_PECI_DATA"), 117 PINCTRL_PIN(79, "SMB2_PECI_CLK"), 118 PINCTRL_PIN(80, "SMB4_CSME0_DATA"), 119 PINCTRL_PIN(81, "SMB4_CSME0_CLK"), 120 PINCTRL_PIN(82, "SMB4_CSME0_ALRT_N"), 121 PINCTRL_PIN(83, "USB_OC0_N"), 122 PINCTRL_PIN(84, "FLEX_CLK_SE0"), 123 PINCTRL_PIN(85, "FLEX_CLK_SE1"), 124 PINCTRL_PIN(86, "SPARE_4"), 125 PINCTRL_PIN(87, "SMB3_IE0_CLK"), 126 PINCTRL_PIN(88, "SMB3_IE0_DATA"), 127 PINCTRL_PIN(89, "SMB3_IE0_ALRT_N"), 128 PINCTRL_PIN(90, "SATA0_LED_N"), 129 PINCTRL_PIN(91, "SATA1_LED_N"), 130 PINCTRL_PIN(92, "SATA_PDETECT0"), 131 PINCTRL_PIN(93, "SATA_PDETECT1"), 132 PINCTRL_PIN(94, "UART1_RTS"), 133 PINCTRL_PIN(95, "UART1_CTS"), 134 PINCTRL_PIN(96, "UART1_RXD"), 135 PINCTRL_PIN(97, "UART1_TXD"), 136 PINCTRL_PIN(98, "SPARE_8"), 137 PINCTRL_PIN(99, "SPARE_9"), 138 PINCTRL_PIN(100, "TCK"), 139 PINCTRL_PIN(101, "TRST_N"), 140 PINCTRL_PIN(102, "TMS"), 141 PINCTRL_PIN(103, "TDI"), 142 PINCTRL_PIN(104, "TDO"), 143 PINCTRL_PIN(105, "CX_PRDY_N"), 144 PINCTRL_PIN(106, "CX_PREQ_N"), 145 PINCTRL_PIN(107, "TAP1_TCK"), 146 PINCTRL_PIN(108, "TAP1_TRST_N"), 147 PINCTRL_PIN(109, "TAP1_TMS"), 148 PINCTRL_PIN(110, "TAP1_TDI"), 149 PINCTRL_PIN(111, "TAP1_TDO"), 150 /* South GPP1 */ 151 PINCTRL_PIN(112, "SUSPWRDNACK"), 152 PINCTRL_PIN(113, "PMU_SUSCLK"), 153 PINCTRL_PIN(114, "ADR_TRIGGER"), 154 PINCTRL_PIN(115, "PMU_SLP_S45_N"), 155 PINCTRL_PIN(116, "PMU_SLP_S3_N"), 156 PINCTRL_PIN(117, "PMU_WAKE_N"), 157 PINCTRL_PIN(118, "PMU_PWRBTN_N"), 158 PINCTRL_PIN(119, "PMU_RESETBUTTON_N"), 159 PINCTRL_PIN(120, "PMU_PLTRST_N"), 160 PINCTRL_PIN(121, "SUS_STAT_N"), 161 PINCTRL_PIN(122, "SLP_S0IX_N"), 162 PINCTRL_PIN(123, "SPI_CS0_N"), 163 PINCTRL_PIN(124, "SPI_CS1_N"), 164 PINCTRL_PIN(125, "SPI_MOSI_IO0"), 165 PINCTRL_PIN(126, "SPI_MISO_IO1"), 166 PINCTRL_PIN(127, "SPI_IO2"), 167 PINCTRL_PIN(128, "SPI_IO3"), 168 PINCTRL_PIN(129, "SPI_CLK"), 169 PINCTRL_PIN(130, "SPI_CLK_LOOPBK"), 170 PINCTRL_PIN(131, "ESPI_IO0"), 171 PINCTRL_PIN(132, "ESPI_IO1"), 172 PINCTRL_PIN(133, "ESPI_IO2"), 173 PINCTRL_PIN(134, "ESPI_IO3"), 174 PINCTRL_PIN(135, "ESPI_CS0_N"), 175 PINCTRL_PIN(136, "ESPI_CLK"), 176 PINCTRL_PIN(137, "ESPI_RST_N"), 177 PINCTRL_PIN(138, "ESPI_ALRT0_N"), 178 PINCTRL_PIN(139, "ESPI_CS1_N"), 179 PINCTRL_PIN(140, "ESPI_ALRT1_N"), 180 PINCTRL_PIN(141, "ESPI_CLK_LOOPBK"), 181 PINCTRL_PIN(142, "EMMC_CMD"), 182 PINCTRL_PIN(143, "EMMC_STROBE"), 183 PINCTRL_PIN(144, "EMMC_CLK"), 184 PINCTRL_PIN(145, "EMMC_D0"), 185 PINCTRL_PIN(146, "EMMC_D1"), 186 PINCTRL_PIN(147, "EMMC_D2"), 187 PINCTRL_PIN(148, "EMMC_D3"), 188 PINCTRL_PIN(149, "EMMC_D4"), 189 PINCTRL_PIN(150, "EMMC_D5"), 190 PINCTRL_PIN(151, "EMMC_D6"), 191 PINCTRL_PIN(152, "EMMC_D7"), 192 PINCTRL_PIN(153, "SPARE_3"), 193}; 194 195static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 }; 196static const unsigned int dnv_uart0_modes[] = { 2, 3, 1, 1 }; 197static const unsigned int dnv_uart1_pins[] = { 94, 95, 96, 97 }; 198static const unsigned int dnv_uart2_pins[] = { 60, 61, 62, 63 }; 199static const unsigned int dnv_uart2_modes[] = { 1, 2, 2, 2 }; 200static const unsigned int dnv_emmc_pins[] = { 201 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 202}; 203 204static const struct intel_pingroup dnv_groups[] = { 205 PIN_GROUP("uart0_grp", dnv_uart0_pins, dnv_uart0_modes), 206 PIN_GROUP("uart1_grp", dnv_uart1_pins, 1), 207 PIN_GROUP("uart2_grp", dnv_uart2_pins, dnv_uart2_modes), 208 PIN_GROUP("emmc_grp", dnv_emmc_pins, 1), 209}; 210 211static const char * const dnv_uart0_groups[] = { "uart0_grp" }; 212static const char * const dnv_uart1_groups[] = { "uart1_grp" }; 213static const char * const dnv_uart2_groups[] = { "uart2_grp" }; 214static const char * const dnv_emmc_groups[] = { "emmc_grp" }; 215 216static const struct intel_function dnv_functions[] = { 217 FUNCTION("uart0", dnv_uart0_groups), 218 FUNCTION("uart1", dnv_uart1_groups), 219 FUNCTION("uart2", dnv_uart2_groups), 220 FUNCTION("emmc", dnv_emmc_groups), 221}; 222 223static const struct intel_padgroup dnv_north_gpps[] = { 224 DNV_GPP(0, 0, 31), /* North ALL_0 */ 225 DNV_GPP(1, 32, 40), /* North ALL_1 */ 226}; 227 228static const struct intel_padgroup dnv_south_gpps[] = { 229 DNV_GPP(0, 41, 58), /* South DFX */ 230 DNV_GPP(1, 59, 90), /* South GPP0_0 */ 231 DNV_GPP(2, 91, 111), /* South GPP0_1 */ 232 DNV_GPP(3, 112, 143), /* South GPP1_0 */ 233 DNV_GPP(4, 144, 153), /* South GPP1_1 */ 234}; 235 236static const struct intel_community dnv_communities[] = { 237 DNV_COMMUNITY(0, 0, 40, dnv_north_gpps), 238 DNV_COMMUNITY(1, 41, 153, dnv_south_gpps), 239}; 240 241static const struct intel_pinctrl_soc_data dnv_soc_data = { 242 .pins = dnv_pins, 243 .npins = ARRAY_SIZE(dnv_pins), 244 .groups = dnv_groups, 245 .ngroups = ARRAY_SIZE(dnv_groups), 246 .functions = dnv_functions, 247 .nfunctions = ARRAY_SIZE(dnv_functions), 248 .communities = dnv_communities, 249 .ncommunities = ARRAY_SIZE(dnv_communities), 250}; 251 252static INTEL_PINCTRL_PM_OPS(dnv_pinctrl_pm_ops); 253 254static const struct acpi_device_id dnv_pinctrl_acpi_match[] = { 255 { "INTC3000", (kernel_ulong_t)&dnv_soc_data }, 256 { } 257}; 258MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match); 259 260static struct platform_driver dnv_pinctrl_driver = { 261 .probe = intel_pinctrl_probe_by_hid, 262 .driver = { 263 .name = "denverton-pinctrl", 264 .acpi_match_table = dnv_pinctrl_acpi_match, 265 .pm = &dnv_pinctrl_pm_ops, 266 }, 267}; 268 269static int __init dnv_pinctrl_init(void) 270{ 271 return platform_driver_register(&dnv_pinctrl_driver); 272} 273subsys_initcall(dnv_pinctrl_init); 274 275static void __exit dnv_pinctrl_exit(void) 276{ 277 platform_driver_unregister(&dnv_pinctrl_driver); 278} 279module_exit(dnv_pinctrl_exit); 280 281MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 282MODULE_DESCRIPTION("Intel Denverton SoC pinctrl/GPIO driver"); 283MODULE_LICENSE("GPL v2"); 284MODULE_IMPORT_NS(PINCTRL_INTEL); 285