1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Intel Broxton SoC pinctrl/GPIO driver 4 * 5 * Copyright (C) 2015, 2016 Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 */ 8 9#include <linux/mod_devicetable.h> 10#include <linux/module.h> 11#include <linux/platform_device.h> 12 13#include <linux/pinctrl/pinctrl.h> 14 15#include "pinctrl-intel.h" 16 17#define BXT_PAD_OWN 0x020 18#define BXT_PADCFGLOCK 0x060 19#define BXT_HOSTSW_OWN 0x080 20#define BXT_GPI_IS 0x100 21#define BXT_GPI_IE 0x110 22 23#define BXT_COMMUNITY(b, s, e) \ 24 INTEL_COMMUNITY_SIZE(b, s, e, 32, 4, BXT) 25 26/* BXT */ 27static const struct pinctrl_pin_desc bxt_north_pins[] = { 28 PINCTRL_PIN(0, "GPIO_0"), 29 PINCTRL_PIN(1, "GPIO_1"), 30 PINCTRL_PIN(2, "GPIO_2"), 31 PINCTRL_PIN(3, "GPIO_3"), 32 PINCTRL_PIN(4, "GPIO_4"), 33 PINCTRL_PIN(5, "GPIO_5"), 34 PINCTRL_PIN(6, "GPIO_6"), 35 PINCTRL_PIN(7, "GPIO_7"), 36 PINCTRL_PIN(8, "GPIO_8"), 37 PINCTRL_PIN(9, "GPIO_9"), 38 PINCTRL_PIN(10, "GPIO_10"), 39 PINCTRL_PIN(11, "GPIO_11"), 40 PINCTRL_PIN(12, "GPIO_12"), 41 PINCTRL_PIN(13, "GPIO_13"), 42 PINCTRL_PIN(14, "GPIO_14"), 43 PINCTRL_PIN(15, "GPIO_15"), 44 PINCTRL_PIN(16, "GPIO_16"), 45 PINCTRL_PIN(17, "GPIO_17"), 46 PINCTRL_PIN(18, "GPIO_18"), 47 PINCTRL_PIN(19, "GPIO_19"), 48 PINCTRL_PIN(20, "GPIO_20"), 49 PINCTRL_PIN(21, "GPIO_21"), 50 PINCTRL_PIN(22, "GPIO_22"), 51 PINCTRL_PIN(23, "GPIO_23"), 52 PINCTRL_PIN(24, "GPIO_24"), 53 PINCTRL_PIN(25, "GPIO_25"), 54 PINCTRL_PIN(26, "GPIO_26"), 55 PINCTRL_PIN(27, "GPIO_27"), 56 PINCTRL_PIN(28, "GPIO_28"), 57 PINCTRL_PIN(29, "GPIO_29"), 58 PINCTRL_PIN(30, "GPIO_30"), 59 PINCTRL_PIN(31, "GPIO_31"), 60 PINCTRL_PIN(32, "GPIO_32"), 61 PINCTRL_PIN(33, "GPIO_33"), 62 PINCTRL_PIN(34, "PWM0"), 63 PINCTRL_PIN(35, "PWM1"), 64 PINCTRL_PIN(36, "PWM2"), 65 PINCTRL_PIN(37, "PWM3"), 66 PINCTRL_PIN(38, "LPSS_UART0_RXD"), 67 PINCTRL_PIN(39, "LPSS_UART0_TXD"), 68 PINCTRL_PIN(40, "LPSS_UART0_RTS_B"), 69 PINCTRL_PIN(41, "LPSS_UART0_CTS_B"), 70 PINCTRL_PIN(42, "LPSS_UART1_RXD"), 71 PINCTRL_PIN(43, "LPSS_UART1_TXD"), 72 PINCTRL_PIN(44, "LPSS_UART1_RTS_B"), 73 PINCTRL_PIN(45, "LPSS_UART1_CTS_B"), 74 PINCTRL_PIN(46, "LPSS_UART2_RXD"), 75 PINCTRL_PIN(47, "LPSS_UART2_TXD"), 76 PINCTRL_PIN(48, "LPSS_UART2_RTS_B"), 77 PINCTRL_PIN(49, "LPSS_UART2_CTS_B"), 78 PINCTRL_PIN(50, "ISH_UART0_RXD"), 79 PINCTRL_PIN(51, "ISH_UART0_TXT"), 80 PINCTRL_PIN(52, "ISH_UART0_RTS_B"), 81 PINCTRL_PIN(53, "ISH_UART0_CTS_B"), 82 PINCTRL_PIN(54, "ISH_UART1_RXD"), 83 PINCTRL_PIN(55, "ISH_UART1_TXT"), 84 PINCTRL_PIN(56, "ISH_UART1_RTS_B"), 85 PINCTRL_PIN(57, "ISH_UART1_CTS_B"), 86 PINCTRL_PIN(58, "ISH_UART2_RXD"), 87 PINCTRL_PIN(59, "ISH_UART2_TXD"), 88 PINCTRL_PIN(60, "ISH_UART2_RTS_B"), 89 PINCTRL_PIN(61, "ISH_UART2_CTS_B"), 90 PINCTRL_PIN(62, "GP_CAMERASB00"), 91 PINCTRL_PIN(63, "GP_CAMERASB01"), 92 PINCTRL_PIN(64, "GP_CAMERASB02"), 93 PINCTRL_PIN(65, "GP_CAMERASB03"), 94 PINCTRL_PIN(66, "GP_CAMERASB04"), 95 PINCTRL_PIN(67, "GP_CAMERASB05"), 96 PINCTRL_PIN(68, "GP_CAMERASB06"), 97 PINCTRL_PIN(69, "GP_CAMERASB07"), 98 PINCTRL_PIN(70, "GP_CAMERASB08"), 99 PINCTRL_PIN(71, "GP_CAMERASB09"), 100 PINCTRL_PIN(72, "GP_CAMERASB10"), 101 PINCTRL_PIN(73, "GP_CAMERASB11"), 102 PINCTRL_PIN(74, "TCK"), 103 PINCTRL_PIN(75, "TRST_B"), 104 PINCTRL_PIN(76, "TMS"), 105 PINCTRL_PIN(77, "TDI"), 106 PINCTRL_PIN(78, "CX_PMODE"), 107 PINCTRL_PIN(79, "CX_PREQ_B"), 108 PINCTRL_PIN(80, "JTAGX"), 109 PINCTRL_PIN(81, "CX_PRDY_B"), 110 PINCTRL_PIN(82, "TDO"), 111}; 112 113static const unsigned int bxt_north_pwm0_pins[] = { 34 }; 114static const unsigned int bxt_north_pwm1_pins[] = { 35 }; 115static const unsigned int bxt_north_pwm2_pins[] = { 36 }; 116static const unsigned int bxt_north_pwm3_pins[] = { 37 }; 117static const unsigned int bxt_north_uart0_pins[] = { 38, 39, 40, 41 }; 118static const unsigned int bxt_north_uart1_pins[] = { 42, 43, 44, 45 }; 119static const unsigned int bxt_north_uart2_pins[] = { 46, 47, 48, 49 }; 120static const unsigned int bxt_north_uart0b_pins[] = { 50, 51, 52, 53 }; 121static const unsigned int bxt_north_uart1b_pins[] = { 54, 55, 56, 57 }; 122static const unsigned int bxt_north_uart2b_pins[] = { 58, 59, 60, 61 }; 123static const unsigned int bxt_north_uart3_pins[] = { 58, 59, 60, 61 }; 124 125static const struct intel_pingroup bxt_north_groups[] = { 126 PIN_GROUP("pwm0_grp", bxt_north_pwm0_pins, 1), 127 PIN_GROUP("pwm1_grp", bxt_north_pwm1_pins, 1), 128 PIN_GROUP("pwm2_grp", bxt_north_pwm2_pins, 1), 129 PIN_GROUP("pwm3_grp", bxt_north_pwm3_pins, 1), 130 PIN_GROUP("uart0_grp", bxt_north_uart0_pins, 1), 131 PIN_GROUP("uart1_grp", bxt_north_uart1_pins, 1), 132 PIN_GROUP("uart2_grp", bxt_north_uart2_pins, 1), 133 PIN_GROUP("uart0b_grp", bxt_north_uart0b_pins, 2), 134 PIN_GROUP("uart1b_grp", bxt_north_uart1b_pins, 2), 135 PIN_GROUP("uart2b_grp", bxt_north_uart2b_pins, 2), 136 PIN_GROUP("uart3_grp", bxt_north_uart3_pins, 3), 137}; 138 139static const char * const bxt_north_pwm0_groups[] = { "pwm0_grp" }; 140static const char * const bxt_north_pwm1_groups[] = { "pwm1_grp" }; 141static const char * const bxt_north_pwm2_groups[] = { "pwm2_grp" }; 142static const char * const bxt_north_pwm3_groups[] = { "pwm3_grp" }; 143static const char * const bxt_north_uart0_groups[] = { 144 "uart0_grp", "uart0b_grp", 145}; 146static const char * const bxt_north_uart1_groups[] = { 147 "uart1_grp", "uart1b_grp", 148}; 149static const char * const bxt_north_uart2_groups[] = { 150 "uart2_grp", "uart2b_grp", 151}; 152static const char * const bxt_north_uart3_groups[] = { "uart3_grp" }; 153 154static const struct intel_function bxt_north_functions[] = { 155 FUNCTION("pwm0", bxt_north_pwm0_groups), 156 FUNCTION("pwm1", bxt_north_pwm1_groups), 157 FUNCTION("pwm2", bxt_north_pwm2_groups), 158 FUNCTION("pwm3", bxt_north_pwm3_groups), 159 FUNCTION("uart0", bxt_north_uart0_groups), 160 FUNCTION("uart1", bxt_north_uart1_groups), 161 FUNCTION("uart2", bxt_north_uart2_groups), 162 FUNCTION("uart3", bxt_north_uart3_groups), 163}; 164 165static const struct intel_community bxt_north_communities[] = { 166 BXT_COMMUNITY(0, 0, 82), 167}; 168 169static const struct intel_pinctrl_soc_data bxt_north_soc_data = { 170 .uid = "1", 171 .pins = bxt_north_pins, 172 .npins = ARRAY_SIZE(bxt_north_pins), 173 .groups = bxt_north_groups, 174 .ngroups = ARRAY_SIZE(bxt_north_groups), 175 .functions = bxt_north_functions, 176 .nfunctions = ARRAY_SIZE(bxt_north_functions), 177 .communities = bxt_north_communities, 178 .ncommunities = ARRAY_SIZE(bxt_north_communities), 179}; 180 181static const struct pinctrl_pin_desc bxt_northwest_pins[] = { 182 PINCTRL_PIN(0, "PMC_SPI_FS0"), 183 PINCTRL_PIN(1, "PMC_SPI_FS1"), 184 PINCTRL_PIN(2, "PMC_SPI_FS2"), 185 PINCTRL_PIN(3, "PMC_SPI_RXD"), 186 PINCTRL_PIN(4, "PMC_SPI_TXD"), 187 PINCTRL_PIN(5, "PMC_SPI_CLK"), 188 PINCTRL_PIN(6, "PMC_UART_RXD"), 189 PINCTRL_PIN(7, "PMC_UART_TXD"), 190 PINCTRL_PIN(8, "PMIC_PWRGOOD"), 191 PINCTRL_PIN(9, "PMIC_RESET_B"), 192 PINCTRL_PIN(10, "RTC_CLK"), 193 PINCTRL_PIN(11, "PMIC_SDWN_B"), 194 PINCTRL_PIN(12, "PMIC_BCUDISW2"), 195 PINCTRL_PIN(13, "PMIC_BCUDISCRIT"), 196 PINCTRL_PIN(14, "PMIC_THERMTRIP_B"), 197 PINCTRL_PIN(15, "PMIC_STDBY"), 198 PINCTRL_PIN(16, "SVID0_ALERT_B"), 199 PINCTRL_PIN(17, "SVID0_DATA"), 200 PINCTRL_PIN(18, "SVID0_CLK"), 201 PINCTRL_PIN(19, "PMIC_I2C_SCL"), 202 PINCTRL_PIN(20, "PMIC_I2C_SDA"), 203 PINCTRL_PIN(21, "AVS_I2S1_MCLK"), 204 PINCTRL_PIN(22, "AVS_I2S1_BCLK"), 205 PINCTRL_PIN(23, "AVS_I2S1_WS_SYNC"), 206 PINCTRL_PIN(24, "AVS_I2S1_SDI"), 207 PINCTRL_PIN(25, "AVS_I2S1_SDO"), 208 PINCTRL_PIN(26, "AVS_M_CLK_A1"), 209 PINCTRL_PIN(27, "AVS_M_CLK_B1"), 210 PINCTRL_PIN(28, "AVS_M_DATA_1"), 211 PINCTRL_PIN(29, "AVS_M_CLK_AB2"), 212 PINCTRL_PIN(30, "AVS_M_DATA_2"), 213 PINCTRL_PIN(31, "AVS_I2S2_MCLK"), 214 PINCTRL_PIN(32, "AVS_I2S2_BCLK"), 215 PINCTRL_PIN(33, "AVS_I2S2_WS_SYNC"), 216 PINCTRL_PIN(34, "AVS_I2S2_SDI"), 217 PINCTRL_PIN(35, "AVS_I2S2_SDOK"), 218 PINCTRL_PIN(36, "AVS_I2S3_BCLK"), 219 PINCTRL_PIN(37, "AVS_I2S3_WS_SYNC"), 220 PINCTRL_PIN(38, "AVS_I2S3_SDI"), 221 PINCTRL_PIN(39, "AVS_I2S3_SDO"), 222 PINCTRL_PIN(40, "AVS_I2S4_BCLK"), 223 PINCTRL_PIN(41, "AVS_I2S4_WS_SYNC"), 224 PINCTRL_PIN(42, "AVS_I2S4_SDI"), 225 PINCTRL_PIN(43, "AVS_I2S4_SDO"), 226 PINCTRL_PIN(44, "PROCHOT_B"), 227 PINCTRL_PIN(45, "FST_SPI_CS0_B"), 228 PINCTRL_PIN(46, "FST_SPI_CS1_B"), 229 PINCTRL_PIN(47, "FST_SPI_MOSI_IO0"), 230 PINCTRL_PIN(48, "FST_SPI_MISO_IO1"), 231 PINCTRL_PIN(49, "FST_SPI_IO2"), 232 PINCTRL_PIN(50, "FST_SPI_IO3"), 233 PINCTRL_PIN(51, "FST_SPI_CLK"), 234 PINCTRL_PIN(52, "FST_SPI_CLK_FB"), 235 PINCTRL_PIN(53, "GP_SSP_0_CLK"), 236 PINCTRL_PIN(54, "GP_SSP_0_FS0"), 237 PINCTRL_PIN(55, "GP_SSP_0_FS1"), 238 PINCTRL_PIN(56, "GP_SSP_0_FS2"), 239 PINCTRL_PIN(57, "GP_SSP_0_RXD"), 240 PINCTRL_PIN(58, "GP_SSP_0_TXD"), 241 PINCTRL_PIN(59, "GP_SSP_1_CLK"), 242 PINCTRL_PIN(60, "GP_SSP_1_FS0"), 243 PINCTRL_PIN(61, "GP_SSP_1_FS1"), 244 PINCTRL_PIN(62, "GP_SSP_1_FS2"), 245 PINCTRL_PIN(63, "GP_SSP_1_FS3"), 246 PINCTRL_PIN(64, "GP_SSP_1_RXD"), 247 PINCTRL_PIN(65, "GP_SSP_1_TXD"), 248 PINCTRL_PIN(66, "GP_SSP_2_CLK"), 249 PINCTRL_PIN(67, "GP_SSP_2_FS0"), 250 PINCTRL_PIN(68, "GP_SSP_2_FS1"), 251 PINCTRL_PIN(69, "GP_SSP_2_FS2"), 252 PINCTRL_PIN(70, "GP_SSP_2_RXD"), 253 PINCTRL_PIN(71, "GP_SSP_2_TXD"), 254}; 255 256static const unsigned int bxt_northwest_ssp0_pins[] = { 53, 54, 55, 56, 57, 58 }; 257static const unsigned int bxt_northwest_ssp1_pins[] = { 258 59, 60, 61, 62, 63, 64, 65 259}; 260static const unsigned int bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 }; 261static const unsigned int bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 }; 262 263static const struct intel_pingroup bxt_northwest_groups[] = { 264 PIN_GROUP("ssp0_grp", bxt_northwest_ssp0_pins, 1), 265 PIN_GROUP("ssp1_grp", bxt_northwest_ssp1_pins, 1), 266 PIN_GROUP("ssp2_grp", bxt_northwest_ssp2_pins, 1), 267 PIN_GROUP("uart3_grp", bxt_northwest_uart3_pins, 2), 268}; 269 270static const char * const bxt_northwest_ssp0_groups[] = { "ssp0_grp" }; 271static const char * const bxt_northwest_ssp1_groups[] = { "ssp1_grp" }; 272static const char * const bxt_northwest_ssp2_groups[] = { "ssp2_grp" }; 273static const char * const bxt_northwest_uart3_groups[] = { "uart3_grp" }; 274 275static const struct intel_function bxt_northwest_functions[] = { 276 FUNCTION("ssp0", bxt_northwest_ssp0_groups), 277 FUNCTION("ssp1", bxt_northwest_ssp1_groups), 278 FUNCTION("ssp2", bxt_northwest_ssp2_groups), 279 FUNCTION("uart3", bxt_northwest_uart3_groups), 280}; 281 282static const struct intel_community bxt_northwest_communities[] = { 283 BXT_COMMUNITY(0, 0, 71), 284}; 285 286static const struct intel_pinctrl_soc_data bxt_northwest_soc_data = { 287 .uid = "2", 288 .pins = bxt_northwest_pins, 289 .npins = ARRAY_SIZE(bxt_northwest_pins), 290 .groups = bxt_northwest_groups, 291 .ngroups = ARRAY_SIZE(bxt_northwest_groups), 292 .functions = bxt_northwest_functions, 293 .nfunctions = ARRAY_SIZE(bxt_northwest_functions), 294 .communities = bxt_northwest_communities, 295 .ncommunities = ARRAY_SIZE(bxt_northwest_communities), 296}; 297 298static const struct pinctrl_pin_desc bxt_west_pins[] = { 299 PINCTRL_PIN(0, "LPSS_I2C0_SDA"), 300 PINCTRL_PIN(1, "LPSS_I2C0_SCL"), 301 PINCTRL_PIN(2, "LPSS_I2C1_SDA"), 302 PINCTRL_PIN(3, "LPSS_I2C1_SCL"), 303 PINCTRL_PIN(4, "LPSS_I2C2_SDA"), 304 PINCTRL_PIN(5, "LPSS_I2C2_SCL"), 305 PINCTRL_PIN(6, "LPSS_I2C3_SDA"), 306 PINCTRL_PIN(7, "LPSS_I2C3_SCL"), 307 PINCTRL_PIN(8, "LPSS_I2C4_SDA"), 308 PINCTRL_PIN(9, "LPSS_I2C4_SCL"), 309 PINCTRL_PIN(10, "LPSS_I2C5_SDA"), 310 PINCTRL_PIN(11, "LPSS_I2C5_SCL"), 311 PINCTRL_PIN(12, "LPSS_I2C6_SDA"), 312 PINCTRL_PIN(13, "LPSS_I2C6_SCL"), 313 PINCTRL_PIN(14, "LPSS_I2C7_SDA"), 314 PINCTRL_PIN(15, "LPSS_I2C7_SCL"), 315 PINCTRL_PIN(16, "ISH_I2C0_SDA"), 316 PINCTRL_PIN(17, "ISH_I2C0_SCL"), 317 PINCTRL_PIN(18, "ISH_I2C1_SDA"), 318 PINCTRL_PIN(19, "ISH_I2C1_SCL"), 319 PINCTRL_PIN(20, "ISH_I2C2_SDA"), 320 PINCTRL_PIN(21, "ISH_I2C2_SCL"), 321 PINCTRL_PIN(22, "ISH_GPIO_0"), 322 PINCTRL_PIN(23, "ISH_GPIO_1"), 323 PINCTRL_PIN(24, "ISH_GPIO_2"), 324 PINCTRL_PIN(25, "ISH_GPIO_3"), 325 PINCTRL_PIN(26, "ISH_GPIO_4"), 326 PINCTRL_PIN(27, "ISH_GPIO_5"), 327 PINCTRL_PIN(28, "ISH_GPIO_6"), 328 PINCTRL_PIN(29, "ISH_GPIO_7"), 329 PINCTRL_PIN(30, "ISH_GPIO_8"), 330 PINCTRL_PIN(31, "ISH_GPIO_9"), 331 PINCTRL_PIN(32, "MODEM_CLKREQ"), 332 PINCTRL_PIN(33, "DGCLKDBG_PMC_0"), 333 PINCTRL_PIN(34, "DGCLKDBG_PMC_1"), 334 PINCTRL_PIN(35, "DGCLKDBG_PMC_2"), 335 PINCTRL_PIN(36, "DGCLKDBG_ICLK_0"), 336 PINCTRL_PIN(37, "DGCLKDBG_ICLK_1"), 337 PINCTRL_PIN(38, "OSC_CLK_OUT_0"), 338 PINCTRL_PIN(39, "OSC_CLK_OUT_1"), 339 PINCTRL_PIN(40, "OSC_CLK_OUT_2"), 340 PINCTRL_PIN(41, "OSC_CLK_OUT_3"), 341}; 342 343static const unsigned int bxt_west_i2c0_pins[] = { 0, 1 }; 344static const unsigned int bxt_west_i2c1_pins[] = { 2, 3 }; 345static const unsigned int bxt_west_i2c2_pins[] = { 4, 5 }; 346static const unsigned int bxt_west_i2c3_pins[] = { 6, 7 }; 347static const unsigned int bxt_west_i2c4_pins[] = { 8, 9 }; 348static const unsigned int bxt_west_i2c5_pins[] = { 10, 11 }; 349static const unsigned int bxt_west_i2c6_pins[] = { 12, 13 }; 350static const unsigned int bxt_west_i2c7_pins[] = { 14, 15 }; 351static const unsigned int bxt_west_i2c5b_pins[] = { 16, 17 }; 352static const unsigned int bxt_west_i2c6b_pins[] = { 18, 19 }; 353static const unsigned int bxt_west_i2c7b_pins[] = { 20, 21 }; 354 355static const struct intel_pingroup bxt_west_groups[] = { 356 PIN_GROUP("i2c0_grp", bxt_west_i2c0_pins, 1), 357 PIN_GROUP("i2c1_grp", bxt_west_i2c1_pins, 1), 358 PIN_GROUP("i2c2_grp", bxt_west_i2c2_pins, 1), 359 PIN_GROUP("i2c3_grp", bxt_west_i2c3_pins, 1), 360 PIN_GROUP("i2c4_grp", bxt_west_i2c4_pins, 1), 361 PIN_GROUP("i2c5_grp", bxt_west_i2c5_pins, 1), 362 PIN_GROUP("i2c6_grp", bxt_west_i2c6_pins, 1), 363 PIN_GROUP("i2c7_grp", bxt_west_i2c7_pins, 1), 364 PIN_GROUP("i2c5b_grp", bxt_west_i2c5b_pins, 2), 365 PIN_GROUP("i2c6b_grp", bxt_west_i2c6b_pins, 2), 366 PIN_GROUP("i2c7b_grp", bxt_west_i2c7b_pins, 2), 367}; 368 369static const char * const bxt_west_i2c0_groups[] = { "i2c0_grp" }; 370static const char * const bxt_west_i2c1_groups[] = { "i2c1_grp" }; 371static const char * const bxt_west_i2c2_groups[] = { "i2c2_grp" }; 372static const char * const bxt_west_i2c3_groups[] = { "i2c3_grp" }; 373static const char * const bxt_west_i2c4_groups[] = { "i2c4_grp" }; 374static const char * const bxt_west_i2c5_groups[] = { "i2c5_grp", "i2c5b_grp" }; 375static const char * const bxt_west_i2c6_groups[] = { "i2c6_grp", "i2c6b_grp" }; 376static const char * const bxt_west_i2c7_groups[] = { "i2c7_grp", "i2c7b_grp" }; 377 378static const struct intel_function bxt_west_functions[] = { 379 FUNCTION("i2c0", bxt_west_i2c0_groups), 380 FUNCTION("i2c1", bxt_west_i2c1_groups), 381 FUNCTION("i2c2", bxt_west_i2c2_groups), 382 FUNCTION("i2c3", bxt_west_i2c3_groups), 383 FUNCTION("i2c4", bxt_west_i2c4_groups), 384 FUNCTION("i2c5", bxt_west_i2c5_groups), 385 FUNCTION("i2c6", bxt_west_i2c6_groups), 386 FUNCTION("i2c7", bxt_west_i2c7_groups), 387}; 388 389static const struct intel_community bxt_west_communities[] = { 390 BXT_COMMUNITY(0, 0, 41), 391}; 392 393static const struct intel_pinctrl_soc_data bxt_west_soc_data = { 394 .uid = "3", 395 .pins = bxt_west_pins, 396 .npins = ARRAY_SIZE(bxt_west_pins), 397 .groups = bxt_west_groups, 398 .ngroups = ARRAY_SIZE(bxt_west_groups), 399 .functions = bxt_west_functions, 400 .nfunctions = ARRAY_SIZE(bxt_west_functions), 401 .communities = bxt_west_communities, 402 .ncommunities = ARRAY_SIZE(bxt_west_communities), 403}; 404 405static const struct pinctrl_pin_desc bxt_southwest_pins[] = { 406 PINCTRL_PIN(0, "EMMC0_CLK"), 407 PINCTRL_PIN(1, "EMMC0_D0"), 408 PINCTRL_PIN(2, "EMMC0_D1"), 409 PINCTRL_PIN(3, "EMMC0_D2"), 410 PINCTRL_PIN(4, "EMMC0_D3"), 411 PINCTRL_PIN(5, "EMMC0_D4"), 412 PINCTRL_PIN(6, "EMMC0_D5"), 413 PINCTRL_PIN(7, "EMMC0_D6"), 414 PINCTRL_PIN(8, "EMMC0_D7"), 415 PINCTRL_PIN(9, "EMMC0_CMD"), 416 PINCTRL_PIN(10, "SDIO_CLK"), 417 PINCTRL_PIN(11, "SDIO_D0"), 418 PINCTRL_PIN(12, "SDIO_D1"), 419 PINCTRL_PIN(13, "SDIO_D2"), 420 PINCTRL_PIN(14, "SDIO_D3"), 421 PINCTRL_PIN(15, "SDIO_CMD"), 422 PINCTRL_PIN(16, "SDCARD_CLK"), 423 PINCTRL_PIN(17, "SDCARD_D0"), 424 PINCTRL_PIN(18, "SDCARD_D1"), 425 PINCTRL_PIN(19, "SDCARD_D2"), 426 PINCTRL_PIN(20, "SDCARD_D3"), 427 PINCTRL_PIN(21, "SDCARD_CD_B"), 428 PINCTRL_PIN(22, "SDCARD_CMD"), 429 PINCTRL_PIN(23, "SDCARD_LVL_CLK_FB"), 430 PINCTRL_PIN(24, "SDCARD_LVL_CMD_DIR"), 431 PINCTRL_PIN(25, "SDCARD_LVL_DAT_DIR"), 432 PINCTRL_PIN(26, "EMMC0_STROBE"), 433 PINCTRL_PIN(27, "SDIO_PWR_DOWN_B"), 434 PINCTRL_PIN(28, "SDCARD_PWR_DOWN_B"), 435 PINCTRL_PIN(29, "SDCARD_LVL_SEL"), 436 PINCTRL_PIN(30, "SDCARD_LVL_WP"), 437}; 438 439static const unsigned int bxt_southwest_emmc0_pins[] = { 440 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 26, 441}; 442static const unsigned int bxt_southwest_sdio_pins[] = { 443 10, 11, 12, 13, 14, 15, 27, 444}; 445static const unsigned int bxt_southwest_sdcard_pins[] = { 446 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30, 447}; 448 449static const struct intel_pingroup bxt_southwest_groups[] = { 450 PIN_GROUP("emmc0_grp", bxt_southwest_emmc0_pins, 1), 451 PIN_GROUP("sdio_grp", bxt_southwest_sdio_pins, 1), 452 PIN_GROUP("sdcard_grp", bxt_southwest_sdcard_pins, 1), 453}; 454 455static const char * const bxt_southwest_emmc0_groups[] = { "emmc0_grp" }; 456static const char * const bxt_southwest_sdio_groups[] = { "sdio_grp" }; 457static const char * const bxt_southwest_sdcard_groups[] = { "sdcard_grp" }; 458 459static const struct intel_function bxt_southwest_functions[] = { 460 FUNCTION("emmc0", bxt_southwest_emmc0_groups), 461 FUNCTION("sdio", bxt_southwest_sdio_groups), 462 FUNCTION("sdcard", bxt_southwest_sdcard_groups), 463}; 464 465static const struct intel_community bxt_southwest_communities[] = { 466 BXT_COMMUNITY(0, 0, 30), 467}; 468 469static const struct intel_pinctrl_soc_data bxt_southwest_soc_data = { 470 .uid = "4", 471 .pins = bxt_southwest_pins, 472 .npins = ARRAY_SIZE(bxt_southwest_pins), 473 .groups = bxt_southwest_groups, 474 .ngroups = ARRAY_SIZE(bxt_southwest_groups), 475 .functions = bxt_southwest_functions, 476 .nfunctions = ARRAY_SIZE(bxt_southwest_functions), 477 .communities = bxt_southwest_communities, 478 .ncommunities = ARRAY_SIZE(bxt_southwest_communities), 479}; 480 481static const struct pinctrl_pin_desc bxt_south_pins[] = { 482 PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"), 483 PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"), 484 PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"), 485 PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"), 486 PINCTRL_PIN(4, "DBI_SDA"), 487 PINCTRL_PIN(5, "DBI_SCL"), 488 PINCTRL_PIN(6, "PANEL0_VDDEN"), 489 PINCTRL_PIN(7, "PANEL0_BKLTEN"), 490 PINCTRL_PIN(8, "PANEL0_BKLTCTL"), 491 PINCTRL_PIN(9, "PANEL1_VDDEN"), 492 PINCTRL_PIN(10, "PANEL1_BKLTEN"), 493 PINCTRL_PIN(11, "PANEL1_BKLTCTL"), 494 PINCTRL_PIN(12, "DBI_CSX"), 495 PINCTRL_PIN(13, "DBI_RESX"), 496 PINCTRL_PIN(14, "GP_INTD_DSI_TE1"), 497 PINCTRL_PIN(15, "GP_INTD_DSI_TE2"), 498 PINCTRL_PIN(16, "USB_OC0_B"), 499 PINCTRL_PIN(17, "USB_OC1_B"), 500 PINCTRL_PIN(18, "MEX_WAKE0_B"), 501 PINCTRL_PIN(19, "MEX_WAKE1_B"), 502}; 503 504static const struct intel_community bxt_south_communities[] = { 505 BXT_COMMUNITY(0, 0, 19), 506}; 507 508static const struct intel_pinctrl_soc_data bxt_south_soc_data = { 509 .uid = "5", 510 .pins = bxt_south_pins, 511 .npins = ARRAY_SIZE(bxt_south_pins), 512 .communities = bxt_south_communities, 513 .ncommunities = ARRAY_SIZE(bxt_south_communities), 514}; 515 516static const struct intel_pinctrl_soc_data *bxt_pinctrl_soc_data[] = { 517 &bxt_north_soc_data, 518 &bxt_northwest_soc_data, 519 &bxt_west_soc_data, 520 &bxt_southwest_soc_data, 521 &bxt_south_soc_data, 522 NULL 523}; 524 525/* APL */ 526static const struct pinctrl_pin_desc apl_north_pins[] = { 527 PINCTRL_PIN(0, "GPIO_0"), 528 PINCTRL_PIN(1, "GPIO_1"), 529 PINCTRL_PIN(2, "GPIO_2"), 530 PINCTRL_PIN(3, "GPIO_3"), 531 PINCTRL_PIN(4, "GPIO_4"), 532 PINCTRL_PIN(5, "GPIO_5"), 533 PINCTRL_PIN(6, "GPIO_6"), 534 PINCTRL_PIN(7, "GPIO_7"), 535 PINCTRL_PIN(8, "GPIO_8"), 536 PINCTRL_PIN(9, "GPIO_9"), 537 PINCTRL_PIN(10, "GPIO_10"), 538 PINCTRL_PIN(11, "GPIO_11"), 539 PINCTRL_PIN(12, "GPIO_12"), 540 PINCTRL_PIN(13, "GPIO_13"), 541 PINCTRL_PIN(14, "GPIO_14"), 542 PINCTRL_PIN(15, "GPIO_15"), 543 PINCTRL_PIN(16, "GPIO_16"), 544 PINCTRL_PIN(17, "GPIO_17"), 545 PINCTRL_PIN(18, "GPIO_18"), 546 PINCTRL_PIN(19, "GPIO_19"), 547 PINCTRL_PIN(20, "GPIO_20"), 548 PINCTRL_PIN(21, "GPIO_21"), 549 PINCTRL_PIN(22, "GPIO_22"), 550 PINCTRL_PIN(23, "GPIO_23"), 551 PINCTRL_PIN(24, "GPIO_24"), 552 PINCTRL_PIN(25, "GPIO_25"), 553 PINCTRL_PIN(26, "GPIO_26"), 554 PINCTRL_PIN(27, "GPIO_27"), 555 PINCTRL_PIN(28, "GPIO_28"), 556 PINCTRL_PIN(29, "GPIO_29"), 557 PINCTRL_PIN(30, "GPIO_30"), 558 PINCTRL_PIN(31, "GPIO_31"), 559 PINCTRL_PIN(32, "GPIO_32"), 560 PINCTRL_PIN(33, "GPIO_33"), 561 PINCTRL_PIN(34, "PWM0"), 562 PINCTRL_PIN(35, "PWM1"), 563 PINCTRL_PIN(36, "PWM2"), 564 PINCTRL_PIN(37, "PWM3"), 565 PINCTRL_PIN(38, "LPSS_UART0_RXD"), 566 PINCTRL_PIN(39, "LPSS_UART0_TXD"), 567 PINCTRL_PIN(40, "LPSS_UART0_RTS_B"), 568 PINCTRL_PIN(41, "LPSS_UART0_CTS_B"), 569 PINCTRL_PIN(42, "LPSS_UART1_RXD"), 570 PINCTRL_PIN(43, "LPSS_UART1_TXD"), 571 PINCTRL_PIN(44, "LPSS_UART1_RTS_B"), 572 PINCTRL_PIN(45, "LPSS_UART1_CTS_B"), 573 PINCTRL_PIN(46, "LPSS_UART2_RXD"), 574 PINCTRL_PIN(47, "LPSS_UART2_TXD"), 575 PINCTRL_PIN(48, "LPSS_UART2_RTS_B"), 576 PINCTRL_PIN(49, "LPSS_UART2_CTS_B"), 577 PINCTRL_PIN(50, "GP_CAMERASB00"), 578 PINCTRL_PIN(51, "GP_CAMERASB01"), 579 PINCTRL_PIN(52, "GP_CAMERASB02"), 580 PINCTRL_PIN(53, "GP_CAMERASB03"), 581 PINCTRL_PIN(54, "GP_CAMERASB04"), 582 PINCTRL_PIN(55, "GP_CAMERASB05"), 583 PINCTRL_PIN(56, "GP_CAMERASB06"), 584 PINCTRL_PIN(57, "GP_CAMERASB07"), 585 PINCTRL_PIN(58, "GP_CAMERASB08"), 586 PINCTRL_PIN(59, "GP_CAMERASB09"), 587 PINCTRL_PIN(60, "GP_CAMERASB10"), 588 PINCTRL_PIN(61, "GP_CAMERASB11"), 589 PINCTRL_PIN(62, "TCK"), 590 PINCTRL_PIN(63, "TRST_B"), 591 PINCTRL_PIN(64, "TMS"), 592 PINCTRL_PIN(65, "TDI"), 593 PINCTRL_PIN(66, "CX_PMODE"), 594 PINCTRL_PIN(67, "CX_PREQ_B"), 595 PINCTRL_PIN(68, "JTAGX"), 596 PINCTRL_PIN(69, "CX_PRDY_B"), 597 PINCTRL_PIN(70, "TDO"), 598 PINCTRL_PIN(71, "CNV_BRI_DT"), 599 PINCTRL_PIN(72, "CNV_BRI_RSP"), 600 PINCTRL_PIN(73, "CNV_RGI_DT"), 601 PINCTRL_PIN(74, "CNV_RGI_RSP"), 602 PINCTRL_PIN(75, "SVID0_ALERT_B"), 603 PINCTRL_PIN(76, "SVID0_DATA"), 604 PINCTRL_PIN(77, "SVID0_CLK"), 605}; 606 607static const unsigned int apl_north_pwm0_pins[] = { 34 }; 608static const unsigned int apl_north_pwm1_pins[] = { 35 }; 609static const unsigned int apl_north_pwm2_pins[] = { 36 }; 610static const unsigned int apl_north_pwm3_pins[] = { 37 }; 611static const unsigned int apl_north_uart0_pins[] = { 38, 39, 40, 41 }; 612static const unsigned int apl_north_uart1_pins[] = { 42, 43, 44, 45 }; 613static const unsigned int apl_north_uart2_pins[] = { 46, 47, 48, 49 }; 614 615static const struct intel_pingroup apl_north_groups[] = { 616 PIN_GROUP("pwm0_grp", apl_north_pwm0_pins, 1), 617 PIN_GROUP("pwm1_grp", apl_north_pwm1_pins, 1), 618 PIN_GROUP("pwm2_grp", apl_north_pwm2_pins, 1), 619 PIN_GROUP("pwm3_grp", apl_north_pwm3_pins, 1), 620 PIN_GROUP("uart0_grp", apl_north_uart0_pins, 1), 621 PIN_GROUP("uart1_grp", apl_north_uart1_pins, 1), 622 PIN_GROUP("uart2_grp", apl_north_uart2_pins, 1), 623}; 624 625static const char * const apl_north_pwm0_groups[] = { "pwm0_grp" }; 626static const char * const apl_north_pwm1_groups[] = { "pwm1_grp" }; 627static const char * const apl_north_pwm2_groups[] = { "pwm2_grp" }; 628static const char * const apl_north_pwm3_groups[] = { "pwm3_grp" }; 629static const char * const apl_north_uart0_groups[] = { "uart0_grp" }; 630static const char * const apl_north_uart1_groups[] = { "uart1_grp" }; 631static const char * const apl_north_uart2_groups[] = { "uart2_grp" }; 632 633static const struct intel_function apl_north_functions[] = { 634 FUNCTION("pwm0", apl_north_pwm0_groups), 635 FUNCTION("pwm1", apl_north_pwm1_groups), 636 FUNCTION("pwm2", apl_north_pwm2_groups), 637 FUNCTION("pwm3", apl_north_pwm3_groups), 638 FUNCTION("uart0", apl_north_uart0_groups), 639 FUNCTION("uart1", apl_north_uart1_groups), 640 FUNCTION("uart2", apl_north_uart2_groups), 641}; 642 643static const struct intel_community apl_north_communities[] = { 644 BXT_COMMUNITY(0, 0, 77), 645}; 646 647static const struct intel_pinctrl_soc_data apl_north_soc_data = { 648 .uid = "1", 649 .pins = apl_north_pins, 650 .npins = ARRAY_SIZE(apl_north_pins), 651 .groups = apl_north_groups, 652 .ngroups = ARRAY_SIZE(apl_north_groups), 653 .functions = apl_north_functions, 654 .nfunctions = ARRAY_SIZE(apl_north_functions), 655 .communities = apl_north_communities, 656 .ncommunities = ARRAY_SIZE(apl_north_communities), 657}; 658 659static const struct pinctrl_pin_desc apl_northwest_pins[] = { 660 PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"), 661 PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"), 662 PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"), 663 PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"), 664 PINCTRL_PIN(4, "DBI_SDA"), 665 PINCTRL_PIN(5, "DBI_SCL"), 666 PINCTRL_PIN(6, "PANEL0_VDDEN"), 667 PINCTRL_PIN(7, "PANEL0_BKLTEN"), 668 PINCTRL_PIN(8, "PANEL0_BKLTCTL"), 669 PINCTRL_PIN(9, "PANEL1_VDDEN"), 670 PINCTRL_PIN(10, "PANEL1_BKLTEN"), 671 PINCTRL_PIN(11, "PANEL1_BKLTCTL"), 672 PINCTRL_PIN(12, "DBI_CSX"), 673 PINCTRL_PIN(13, "DBI_RESX"), 674 PINCTRL_PIN(14, "GP_INTD_DSI_TE1"), 675 PINCTRL_PIN(15, "GP_INTD_DSI_TE2"), 676 PINCTRL_PIN(16, "USB_OC0_B"), 677 PINCTRL_PIN(17, "USB_OC1_B"), 678 PINCTRL_PIN(18, "PMC_SPI_FS0"), 679 PINCTRL_PIN(19, "PMC_SPI_FS1"), 680 PINCTRL_PIN(20, "PMC_SPI_FS2"), 681 PINCTRL_PIN(21, "PMC_SPI_RXD"), 682 PINCTRL_PIN(22, "PMC_SPI_TXD"), 683 PINCTRL_PIN(23, "PMC_SPI_CLK"), 684 PINCTRL_PIN(24, "PMIC_PWRGOOD"), 685 PINCTRL_PIN(25, "PMIC_RESET_B"), 686 PINCTRL_PIN(26, "PMIC_SDWN_B"), 687 PINCTRL_PIN(27, "PMIC_BCUDISW2"), 688 PINCTRL_PIN(28, "PMIC_BCUDISCRIT"), 689 PINCTRL_PIN(29, "PMIC_THERMTRIP_B"), 690 PINCTRL_PIN(30, "PMIC_STDBY"), 691 PINCTRL_PIN(31, "PROCHOT_B"), 692 PINCTRL_PIN(32, "PMIC_I2C_SCL"), 693 PINCTRL_PIN(33, "PMIC_I2C_SDA"), 694 PINCTRL_PIN(34, "AVS_I2S1_MCLK"), 695 PINCTRL_PIN(35, "AVS_I2S1_BCLK"), 696 PINCTRL_PIN(36, "AVS_I2S1_WS_SYNC"), 697 PINCTRL_PIN(37, "AVS_I2S1_SDI"), 698 PINCTRL_PIN(38, "AVS_I2S1_SDO"), 699 PINCTRL_PIN(39, "AVS_M_CLK_A1"), 700 PINCTRL_PIN(40, "AVS_M_CLK_B1"), 701 PINCTRL_PIN(41, "AVS_M_DATA_1"), 702 PINCTRL_PIN(42, "AVS_M_CLK_AB2"), 703 PINCTRL_PIN(43, "AVS_M_DATA_2"), 704 PINCTRL_PIN(44, "AVS_I2S2_MCLK"), 705 PINCTRL_PIN(45, "AVS_I2S2_BCLK"), 706 PINCTRL_PIN(46, "AVS_I2S2_WS_SYNC"), 707 PINCTRL_PIN(47, "AVS_I2S2_SDI"), 708 PINCTRL_PIN(48, "AVS_I2S2_SDO"), 709 PINCTRL_PIN(49, "AVS_I2S3_BCLK"), 710 PINCTRL_PIN(50, "AVS_I2S3_WS_SYNC"), 711 PINCTRL_PIN(51, "AVS_I2S3_SDI"), 712 PINCTRL_PIN(52, "AVS_I2S3_SDO"), 713 PINCTRL_PIN(53, "FST_SPI_CS0_B"), 714 PINCTRL_PIN(54, "FST_SPI_CS1_B"), 715 PINCTRL_PIN(55, "FST_SPI_MOSI_IO0"), 716 PINCTRL_PIN(56, "FST_SPI_MISO_IO1"), 717 PINCTRL_PIN(57, "FST_SPI_IO2"), 718 PINCTRL_PIN(58, "FST_SPI_IO3"), 719 PINCTRL_PIN(59, "FST_SPI_CLK"), 720 PINCTRL_PIN(60, "FST_SPI_CLK_FB"), 721 PINCTRL_PIN(61, "GP_SSP_0_CLK"), 722 PINCTRL_PIN(62, "GP_SSP_0_FS0"), 723 PINCTRL_PIN(63, "GP_SSP_0_FS1"), 724 PINCTRL_PIN(64, "GP_SSP_0_RXD"), 725 PINCTRL_PIN(65, "GP_SSP_0_TXD"), 726 PINCTRL_PIN(66, "GP_SSP_1_CLK"), 727 PINCTRL_PIN(67, "GP_SSP_1_FS0"), 728 PINCTRL_PIN(68, "GP_SSP_1_FS1"), 729 PINCTRL_PIN(69, "GP_SSP_1_RXD"), 730 PINCTRL_PIN(70, "GP_SSP_1_TXD"), 731 PINCTRL_PIN(71, "GP_SSP_2_CLK"), 732 PINCTRL_PIN(72, "GP_SSP_2_FS0"), 733 PINCTRL_PIN(73, "GP_SSP_2_FS1"), 734 PINCTRL_PIN(74, "GP_SSP_2_FS2"), 735 PINCTRL_PIN(75, "GP_SSP_2_RXD"), 736 PINCTRL_PIN(76, "GP_SSP_2_TXD"), 737}; 738 739static const unsigned int apl_northwest_ssp0_pins[] = { 61, 62, 63, 64, 65 }; 740static const unsigned int apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 }; 741static const unsigned int apl_northwest_ssp2_pins[] = { 71, 72, 73, 74, 75, 76 }; 742static const unsigned int apl_northwest_uart3_pins[] = { 67, 68, 69, 70 }; 743 744static const struct intel_pingroup apl_northwest_groups[] = { 745 PIN_GROUP("ssp0_grp", apl_northwest_ssp0_pins, 1), 746 PIN_GROUP("ssp1_grp", apl_northwest_ssp1_pins, 1), 747 PIN_GROUP("ssp2_grp", apl_northwest_ssp2_pins, 1), 748 PIN_GROUP("uart3_grp", apl_northwest_uart3_pins, 2), 749}; 750 751static const char * const apl_northwest_ssp0_groups[] = { "ssp0_grp" }; 752static const char * const apl_northwest_ssp1_groups[] = { "ssp1_grp" }; 753static const char * const apl_northwest_ssp2_groups[] = { "ssp2_grp" }; 754static const char * const apl_northwest_uart3_groups[] = { "uart3_grp" }; 755 756static const struct intel_function apl_northwest_functions[] = { 757 FUNCTION("ssp0", apl_northwest_ssp0_groups), 758 FUNCTION("ssp1", apl_northwest_ssp1_groups), 759 FUNCTION("ssp2", apl_northwest_ssp2_groups), 760 FUNCTION("uart3", apl_northwest_uart3_groups), 761}; 762 763static const struct intel_community apl_northwest_communities[] = { 764 BXT_COMMUNITY(0, 0, 76), 765}; 766 767static const struct intel_pinctrl_soc_data apl_northwest_soc_data = { 768 .uid = "2", 769 .pins = apl_northwest_pins, 770 .npins = ARRAY_SIZE(apl_northwest_pins), 771 .groups = apl_northwest_groups, 772 .ngroups = ARRAY_SIZE(apl_northwest_groups), 773 .functions = apl_northwest_functions, 774 .nfunctions = ARRAY_SIZE(apl_northwest_functions), 775 .communities = apl_northwest_communities, 776 .ncommunities = ARRAY_SIZE(apl_northwest_communities), 777}; 778 779static const struct pinctrl_pin_desc apl_west_pins[] = { 780 PINCTRL_PIN(0, "LPSS_I2C0_SDA"), 781 PINCTRL_PIN(1, "LPSS_I2C0_SCL"), 782 PINCTRL_PIN(2, "LPSS_I2C1_SDA"), 783 PINCTRL_PIN(3, "LPSS_I2C1_SCL"), 784 PINCTRL_PIN(4, "LPSS_I2C2_SDA"), 785 PINCTRL_PIN(5, "LPSS_I2C2_SCL"), 786 PINCTRL_PIN(6, "LPSS_I2C3_SDA"), 787 PINCTRL_PIN(7, "LPSS_I2C3_SCL"), 788 PINCTRL_PIN(8, "LPSS_I2C4_SDA"), 789 PINCTRL_PIN(9, "LPSS_I2C4_SCL"), 790 PINCTRL_PIN(10, "LPSS_I2C5_SDA"), 791 PINCTRL_PIN(11, "LPSS_I2C5_SCL"), 792 PINCTRL_PIN(12, "LPSS_I2C6_SDA"), 793 PINCTRL_PIN(13, "LPSS_I2C6_SCL"), 794 PINCTRL_PIN(14, "LPSS_I2C7_SDA"), 795 PINCTRL_PIN(15, "LPSS_I2C7_SCL"), 796 PINCTRL_PIN(16, "ISH_GPIO_0"), 797 PINCTRL_PIN(17, "ISH_GPIO_1"), 798 PINCTRL_PIN(18, "ISH_GPIO_2"), 799 PINCTRL_PIN(19, "ISH_GPIO_3"), 800 PINCTRL_PIN(20, "ISH_GPIO_4"), 801 PINCTRL_PIN(21, "ISH_GPIO_5"), 802 PINCTRL_PIN(22, "ISH_GPIO_6"), 803 PINCTRL_PIN(23, "ISH_GPIO_7"), 804 PINCTRL_PIN(24, "ISH_GPIO_8"), 805 PINCTRL_PIN(25, "ISH_GPIO_9"), 806 PINCTRL_PIN(26, "PCIE_CLKREQ0_B"), 807 PINCTRL_PIN(27, "PCIE_CLKREQ1_B"), 808 PINCTRL_PIN(28, "PCIE_CLKREQ2_B"), 809 PINCTRL_PIN(29, "PCIE_CLKREQ3_B"), 810 PINCTRL_PIN(30, "OSC_CLK_OUT_0"), 811 PINCTRL_PIN(31, "OSC_CLK_OUT_1"), 812 PINCTRL_PIN(32, "OSC_CLK_OUT_2"), 813 PINCTRL_PIN(33, "OSC_CLK_OUT_3"), 814 PINCTRL_PIN(34, "OSC_CLK_OUT_4"), 815 PINCTRL_PIN(35, "PMU_AC_PRESENT"), 816 PINCTRL_PIN(36, "PMU_BATLOW_B"), 817 PINCTRL_PIN(37, "PMU_PLTRST_B"), 818 PINCTRL_PIN(38, "PMU_PWRBTN_B"), 819 PINCTRL_PIN(39, "PMU_RESETBUTTON_B"), 820 PINCTRL_PIN(40, "PMU_SLP_S0_B"), 821 PINCTRL_PIN(41, "PMU_SLP_S3_B"), 822 PINCTRL_PIN(42, "PMU_SLP_S4_B"), 823 PINCTRL_PIN(43, "PMU_SUSCLK"), 824 PINCTRL_PIN(44, "PMU_WAKE_B"), 825 PINCTRL_PIN(45, "SUS_STAT_B"), 826 PINCTRL_PIN(46, "SUSPWRDNACK"), 827}; 828 829static const unsigned int apl_west_i2c0_pins[] = { 0, 1 }; 830static const unsigned int apl_west_i2c1_pins[] = { 2, 3 }; 831static const unsigned int apl_west_i2c2_pins[] = { 4, 5 }; 832static const unsigned int apl_west_i2c3_pins[] = { 6, 7 }; 833static const unsigned int apl_west_i2c4_pins[] = { 8, 9 }; 834static const unsigned int apl_west_i2c5_pins[] = { 10, 11 }; 835static const unsigned int apl_west_i2c6_pins[] = { 12, 13 }; 836static const unsigned int apl_west_i2c7_pins[] = { 14, 15 }; 837static const unsigned int apl_west_uart2_pins[] = { 20, 21, 22, 34 }; 838 839static const struct intel_pingroup apl_west_groups[] = { 840 PIN_GROUP("i2c0_grp", apl_west_i2c0_pins, 1), 841 PIN_GROUP("i2c1_grp", apl_west_i2c1_pins, 1), 842 PIN_GROUP("i2c2_grp", apl_west_i2c2_pins, 1), 843 PIN_GROUP("i2c3_grp", apl_west_i2c3_pins, 1), 844 PIN_GROUP("i2c4_grp", apl_west_i2c4_pins, 1), 845 PIN_GROUP("i2c5_grp", apl_west_i2c5_pins, 1), 846 PIN_GROUP("i2c6_grp", apl_west_i2c6_pins, 1), 847 PIN_GROUP("i2c7_grp", apl_west_i2c7_pins, 1), 848 PIN_GROUP("uart2_grp", apl_west_uart2_pins, 3), 849}; 850 851static const char * const apl_west_i2c0_groups[] = { "i2c0_grp" }; 852static const char * const apl_west_i2c1_groups[] = { "i2c1_grp" }; 853static const char * const apl_west_i2c2_groups[] = { "i2c2_grp" }; 854static const char * const apl_west_i2c3_groups[] = { "i2c3_grp" }; 855static const char * const apl_west_i2c4_groups[] = { "i2c4_grp" }; 856static const char * const apl_west_i2c5_groups[] = { "i2c5_grp" }; 857static const char * const apl_west_i2c6_groups[] = { "i2c6_grp" }; 858static const char * const apl_west_i2c7_groups[] = { "i2c7_grp" }; 859static const char * const apl_west_uart2_groups[] = { "uart2_grp" }; 860 861static const struct intel_function apl_west_functions[] = { 862 FUNCTION("i2c0", apl_west_i2c0_groups), 863 FUNCTION("i2c1", apl_west_i2c1_groups), 864 FUNCTION("i2c2", apl_west_i2c2_groups), 865 FUNCTION("i2c3", apl_west_i2c3_groups), 866 FUNCTION("i2c4", apl_west_i2c4_groups), 867 FUNCTION("i2c5", apl_west_i2c5_groups), 868 FUNCTION("i2c6", apl_west_i2c6_groups), 869 FUNCTION("i2c7", apl_west_i2c7_groups), 870 FUNCTION("uart2", apl_west_uart2_groups), 871}; 872 873static const struct intel_community apl_west_communities[] = { 874 BXT_COMMUNITY(0, 0, 46), 875}; 876 877static const struct intel_pinctrl_soc_data apl_west_soc_data = { 878 .uid = "3", 879 .pins = apl_west_pins, 880 .npins = ARRAY_SIZE(apl_west_pins), 881 .groups = apl_west_groups, 882 .ngroups = ARRAY_SIZE(apl_west_groups), 883 .functions = apl_west_functions, 884 .nfunctions = ARRAY_SIZE(apl_west_functions), 885 .communities = apl_west_communities, 886 .ncommunities = ARRAY_SIZE(apl_west_communities), 887}; 888 889static const struct pinctrl_pin_desc apl_southwest_pins[] = { 890 PINCTRL_PIN(0, "PCIE_WAKE0_B"), 891 PINCTRL_PIN(1, "PCIE_WAKE1_B"), 892 PINCTRL_PIN(2, "PCIE_WAKE2_B"), 893 PINCTRL_PIN(3, "PCIE_WAKE3_B"), 894 PINCTRL_PIN(4, "EMMC0_CLK"), 895 PINCTRL_PIN(5, "EMMC0_D0"), 896 PINCTRL_PIN(6, "EMMC0_D1"), 897 PINCTRL_PIN(7, "EMMC0_D2"), 898 PINCTRL_PIN(8, "EMMC0_D3"), 899 PINCTRL_PIN(9, "EMMC0_D4"), 900 PINCTRL_PIN(10, "EMMC0_D5"), 901 PINCTRL_PIN(11, "EMMC0_D6"), 902 PINCTRL_PIN(12, "EMMC0_D7"), 903 PINCTRL_PIN(13, "EMMC0_CMD"), 904 PINCTRL_PIN(14, "SDIO_CLK"), 905 PINCTRL_PIN(15, "SDIO_D0"), 906 PINCTRL_PIN(16, "SDIO_D1"), 907 PINCTRL_PIN(17, "SDIO_D2"), 908 PINCTRL_PIN(18, "SDIO_D3"), 909 PINCTRL_PIN(19, "SDIO_CMD"), 910 PINCTRL_PIN(20, "SDCARD_CLK"), 911 PINCTRL_PIN(21, "SDCARD_CLK_FB"), 912 PINCTRL_PIN(22, "SDCARD_D0"), 913 PINCTRL_PIN(23, "SDCARD_D1"), 914 PINCTRL_PIN(24, "SDCARD_D2"), 915 PINCTRL_PIN(25, "SDCARD_D3"), 916 PINCTRL_PIN(26, "SDCARD_CD_B"), 917 PINCTRL_PIN(27, "SDCARD_CMD"), 918 PINCTRL_PIN(28, "SDCARD_LVL_WP"), 919 PINCTRL_PIN(29, "EMMC0_STROBE"), 920 PINCTRL_PIN(30, "SDIO_PWR_DOWN_B"), 921 PINCTRL_PIN(31, "SMB_ALERTB"), 922 PINCTRL_PIN(32, "SMB_CLK"), 923 PINCTRL_PIN(33, "SMB_DATA"), 924 PINCTRL_PIN(34, "LPC_ILB_SERIRQ"), 925 PINCTRL_PIN(35, "LPC_CLKOUT0"), 926 PINCTRL_PIN(36, "LPC_CLKOUT1"), 927 PINCTRL_PIN(37, "LPC_AD0"), 928 PINCTRL_PIN(38, "LPC_AD1"), 929 PINCTRL_PIN(39, "LPC_AD2"), 930 PINCTRL_PIN(40, "LPC_AD3"), 931 PINCTRL_PIN(41, "LPC_CLKRUNB"), 932 PINCTRL_PIN(42, "LPC_FRAMEB"), 933}; 934 935static const unsigned int apl_southwest_emmc0_pins[] = { 936 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 29, 937}; 938static const unsigned int apl_southwest_sdio_pins[] = { 939 14, 15, 16, 17, 18, 19, 30, 940}; 941static const unsigned int apl_southwest_sdcard_pins[] = { 942 20, 21, 22, 23, 24, 25, 26, 27, 28, 943}; 944static const unsigned int apl_southwest_i2c7_pins[] = { 32, 33 }; 945 946static const struct intel_pingroup apl_southwest_groups[] = { 947 PIN_GROUP("emmc0_grp", apl_southwest_emmc0_pins, 1), 948 PIN_GROUP("sdio_grp", apl_southwest_sdio_pins, 1), 949 PIN_GROUP("sdcard_grp", apl_southwest_sdcard_pins, 1), 950 PIN_GROUP("i2c7_grp", apl_southwest_i2c7_pins, 2), 951}; 952 953static const char * const apl_southwest_emmc0_groups[] = { "emmc0_grp" }; 954static const char * const apl_southwest_sdio_groups[] = { "sdio_grp" }; 955static const char * const apl_southwest_sdcard_groups[] = { "sdcard_grp" }; 956static const char * const apl_southwest_i2c7_groups[] = { "i2c7_grp" }; 957 958static const struct intel_function apl_southwest_functions[] = { 959 FUNCTION("emmc0", apl_southwest_emmc0_groups), 960 FUNCTION("sdio", apl_southwest_sdio_groups), 961 FUNCTION("sdcard", apl_southwest_sdcard_groups), 962 FUNCTION("i2c7", apl_southwest_i2c7_groups), 963}; 964 965static const struct intel_community apl_southwest_communities[] = { 966 BXT_COMMUNITY(0, 0, 42), 967}; 968 969static const struct intel_pinctrl_soc_data apl_southwest_soc_data = { 970 .uid = "4", 971 .pins = apl_southwest_pins, 972 .npins = ARRAY_SIZE(apl_southwest_pins), 973 .groups = apl_southwest_groups, 974 .ngroups = ARRAY_SIZE(apl_southwest_groups), 975 .functions = apl_southwest_functions, 976 .nfunctions = ARRAY_SIZE(apl_southwest_functions), 977 .communities = apl_southwest_communities, 978 .ncommunities = ARRAY_SIZE(apl_southwest_communities), 979}; 980 981static const struct intel_pinctrl_soc_data *apl_pinctrl_soc_data[] = { 982 &apl_north_soc_data, 983 &apl_northwest_soc_data, 984 &apl_west_soc_data, 985 &apl_southwest_soc_data, 986 NULL 987}; 988 989static const struct acpi_device_id bxt_pinctrl_acpi_match[] = { 990 { "INT3452", (kernel_ulong_t)apl_pinctrl_soc_data }, 991 { "INT34D1", (kernel_ulong_t)bxt_pinctrl_soc_data }, 992 { } 993}; 994MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match); 995 996static const struct platform_device_id bxt_pinctrl_platform_ids[] = { 997 { "apollolake-pinctrl", (kernel_ulong_t)apl_pinctrl_soc_data }, 998 { "broxton-pinctrl", (kernel_ulong_t)bxt_pinctrl_soc_data }, 999 { } 1000}; 1001 1002static INTEL_PINCTRL_PM_OPS(bxt_pinctrl_pm_ops); 1003 1004static struct platform_driver bxt_pinctrl_driver = { 1005 .probe = intel_pinctrl_probe_by_uid, 1006 .driver = { 1007 .name = "broxton-pinctrl", 1008 .acpi_match_table = bxt_pinctrl_acpi_match, 1009 .pm = &bxt_pinctrl_pm_ops, 1010 }, 1011 .id_table = bxt_pinctrl_platform_ids, 1012}; 1013 1014static int __init bxt_pinctrl_init(void) 1015{ 1016 return platform_driver_register(&bxt_pinctrl_driver); 1017} 1018subsys_initcall(bxt_pinctrl_init); 1019 1020static void __exit bxt_pinctrl_exit(void) 1021{ 1022 platform_driver_unregister(&bxt_pinctrl_driver); 1023} 1024module_exit(bxt_pinctrl_exit); 1025 1026MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1027MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver"); 1028MODULE_LICENSE("GPL v2"); 1029MODULE_ALIAS("platform:apollolake-pinctrl"); 1030MODULE_ALIAS("platform:broxton-pinctrl"); 1031MODULE_IMPORT_NS(PINCTRL_INTEL); 1032