162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * UFS PHY driver data for FSD SoC
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (C) 2022 Samsung Electronics Co., Ltd.
662306a36Sopenharmony_ci *
762306a36Sopenharmony_ci */
862306a36Sopenharmony_ci#include "phy-samsung-ufs.h"
962306a36Sopenharmony_ci
1062306a36Sopenharmony_ci#define FSD_EMBEDDED_COMBO_PHY_CTRL	0x724
1162306a36Sopenharmony_ci#define FSD_EMBEDDED_COMBO_PHY_CTRL_MASK	0x1
1262306a36Sopenharmony_ci#define FSD_EMBEDDED_COMBO_PHY_CTRL_EN	BIT(0)
1362306a36Sopenharmony_ci#define FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x6e
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_cistatic const struct samsung_ufs_phy_cfg fsd_pre_init_cfg[] = {
1662306a36Sopenharmony_ci	PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
1762306a36Sopenharmony_ci	PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
1862306a36Sopenharmony_ci	PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
1962306a36Sopenharmony_ci	PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_ANY),
2062306a36Sopenharmony_ci	PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
2162306a36Sopenharmony_ci	PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
2262306a36Sopenharmony_ci	PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
2362306a36Sopenharmony_ci	PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
2462306a36Sopenharmony_ci	PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
2562306a36Sopenharmony_ci	PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
2662306a36Sopenharmony_ci	PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
2762306a36Sopenharmony_ci	PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
2862306a36Sopenharmony_ci	PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
2962306a36Sopenharmony_ci	PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
3062306a36Sopenharmony_ci	END_UFS_PHY_CFG
3162306a36Sopenharmony_ci};
3262306a36Sopenharmony_ci
3362306a36Sopenharmony_ci/* Calibration for HS mode series A/B */
3462306a36Sopenharmony_cistatic const struct samsung_ufs_phy_cfg fsd_pre_pwr_hs_cfg[] = {
3562306a36Sopenharmony_ci	END_UFS_PHY_CFG
3662306a36Sopenharmony_ci};
3762306a36Sopenharmony_ci
3862306a36Sopenharmony_ci/* Calibration for HS mode series A/B atfer PMC */
3962306a36Sopenharmony_cistatic const struct samsung_ufs_phy_cfg fsd_post_pwr_hs_cfg[] = {
4062306a36Sopenharmony_ci	END_UFS_PHY_CFG
4162306a36Sopenharmony_ci};
4262306a36Sopenharmony_ci
4362306a36Sopenharmony_cistatic const struct samsung_ufs_phy_cfg *fsd_ufs_phy_cfgs[CFG_TAG_MAX] = {
4462306a36Sopenharmony_ci	[CFG_PRE_INIT]		= fsd_pre_init_cfg,
4562306a36Sopenharmony_ci	[CFG_PRE_PWR_HS]	= fsd_pre_pwr_hs_cfg,
4662306a36Sopenharmony_ci	[CFG_POST_PWR_HS]	= fsd_post_pwr_hs_cfg,
4762306a36Sopenharmony_ci};
4862306a36Sopenharmony_ci
4962306a36Sopenharmony_cistatic const char * const fsd_ufs_phy_clks[] = {
5062306a36Sopenharmony_ci	"ref_clk",
5162306a36Sopenharmony_ci};
5262306a36Sopenharmony_ci
5362306a36Sopenharmony_ciconst struct samsung_ufs_phy_drvdata fsd_ufs_phy = {
5462306a36Sopenharmony_ci	.cfgs = fsd_ufs_phy_cfgs,
5562306a36Sopenharmony_ci	.isol = {
5662306a36Sopenharmony_ci		.offset = FSD_EMBEDDED_COMBO_PHY_CTRL,
5762306a36Sopenharmony_ci		.mask = FSD_EMBEDDED_COMBO_PHY_CTRL_MASK,
5862306a36Sopenharmony_ci		.en = FSD_EMBEDDED_COMBO_PHY_CTRL_EN,
5962306a36Sopenharmony_ci	},
6062306a36Sopenharmony_ci	.clk_list = fsd_ufs_phy_clks,
6162306a36Sopenharmony_ci	.num_clks = ARRAY_SIZE(fsd_ufs_phy_clks),
6262306a36Sopenharmony_ci	.cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
6362306a36Sopenharmony_ci};
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