1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 5 * 6 */ 7 8#include <dt-bindings/phy/phy.h> 9#include <linux/clk.h> 10#include <linux/debugfs.h> 11#include <linux/delay.h> 12#include <linux/iopoll.h> 13#include <linux/mfd/syscon.h> 14#include <linux/module.h> 15#include <linux/nvmem-consumer.h> 16#include <linux/of.h> 17#include <linux/of_address.h> 18#include <linux/phy/phy.h> 19#include <linux/platform_device.h> 20#include <linux/regmap.h> 21 22#include "phy-mtk-io.h" 23 24/* version V1 sub-banks offset base address */ 25/* banks shared by multiple phys */ 26#define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ 27#define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */ 28#define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */ 29/* u2 phy bank */ 30#define SSUSB_SIFSLV_V1_U2PHY_COM 0x000 31/* u3/pcie/sata phy banks */ 32#define SSUSB_SIFSLV_V1_U3PHYD 0x000 33#define SSUSB_SIFSLV_V1_U3PHYA 0x200 34 35/* version V2/V3 sub-banks offset base address */ 36/* V3: U2FREQ is not used anymore, but reserved */ 37/* u2 phy banks */ 38#define SSUSB_SIFSLV_V2_MISC 0x000 39#define SSUSB_SIFSLV_V2_U2FREQ 0x100 40#define SSUSB_SIFSLV_V2_U2PHY_COM 0x300 41/* u3/pcie/sata phy banks */ 42#define SSUSB_SIFSLV_V2_SPLLC 0x000 43#define SSUSB_SIFSLV_V2_CHIP 0x100 44#define SSUSB_SIFSLV_V2_U3PHYD 0x200 45#define SSUSB_SIFSLV_V2_U3PHYA 0x400 46 47#define U3P_MISC_REG1 0x04 48#define MR1_EFUSE_AUTO_LOAD_DIS BIT(6) 49 50#define U3P_USBPHYACR0 0x000 51#define PA0_RG_U2PLL_FORCE_ON BIT(15) 52#define PA0_USB20_PLL_PREDIV GENMASK(7, 6) 53#define PA0_RG_USB20_INTR_EN BIT(5) 54 55#define U3P_USBPHYACR1 0x004 56#define PA1_RG_INTR_CAL GENMASK(23, 19) 57#define PA1_RG_VRT_SEL GENMASK(14, 12) 58#define PA1_RG_TERM_SEL GENMASK(10, 8) 59 60#define U3P_USBPHYACR2 0x008 61#define PA2_RG_U2PLL_BW GENMASK(21, 19) 62#define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18) 63 64#define U3P_USBPHYACR5 0x014 65#define PA5_RG_U2_HSTX_SRCAL_EN BIT(15) 66#define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) 67#define PA5_RG_U2_HS_100U_U3_EN BIT(11) 68 69#define U3P_USBPHYACR6 0x018 70#define PA6_RG_U2_PRE_EMP GENMASK(31, 30) 71#define PA6_RG_U2_BC11_SW_EN BIT(23) 72#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) 73#define PA6_RG_U2_DISCTH GENMASK(7, 4) 74#define PA6_RG_U2_SQTH GENMASK(3, 0) 75 76#define U3P_U2PHYACR4 0x020 77#define P2C_RG_USB20_GPIO_CTL BIT(9) 78#define P2C_USB20_GPIO_MODE BIT(8) 79#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) 80 81#define U3P_U2PHYA_RESV 0x030 82#define P2R_RG_U2PLL_FBDIV_26M 0x1bb13b 83#define P2R_RG_U2PLL_FBDIV_48M 0x3c0000 84 85#define U3P_U2PHYA_RESV1 0x044 86#define P2R_RG_U2PLL_REFCLK_SEL BIT(5) 87#define P2R_RG_U2PLL_FRA_EN BIT(3) 88 89#define U3D_U2PHYDCR0 0x060 90#define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24) 91 92#define U3P_U2PHYDTM0 0x068 93#define P2C_FORCE_UART_EN BIT(26) 94#define P2C_FORCE_DATAIN BIT(23) 95#define P2C_FORCE_DM_PULLDOWN BIT(21) 96#define P2C_FORCE_DP_PULLDOWN BIT(20) 97#define P2C_FORCE_XCVRSEL BIT(19) 98#define P2C_FORCE_SUSPENDM BIT(18) 99#define P2C_FORCE_TERMSEL BIT(17) 100#define P2C_RG_DATAIN GENMASK(13, 10) 101#define P2C_RG_DMPULLDOWN BIT(7) 102#define P2C_RG_DPPULLDOWN BIT(6) 103#define P2C_RG_XCVRSEL GENMASK(5, 4) 104#define P2C_RG_SUSPENDM BIT(3) 105#define P2C_RG_TERMSEL BIT(2) 106#define P2C_DTM0_PART_MASK \ 107 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \ 108 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \ 109 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \ 110 P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL) 111 112#define U3P_U2PHYDTM1 0x06C 113#define P2C_RG_UART_EN BIT(16) 114#define P2C_FORCE_IDDIG BIT(9) 115#define P2C_RG_VBUSVALID BIT(5) 116#define P2C_RG_SESSEND BIT(4) 117#define P2C_RG_AVALID BIT(2) 118#define P2C_RG_IDDIG BIT(1) 119 120#define U3P_U2PHYBC12C 0x080 121#define P2C_RG_CHGDT_EN BIT(0) 122 123#define U3P_U3_CHIP_GPIO_CTLD 0x0c 124#define P3C_REG_IP_SW_RST BIT(31) 125#define P3C_MCU_BUS_CK_GATE_EN BIT(30) 126#define P3C_FORCE_IP_SW_RST BIT(29) 127 128#define U3P_U3_CHIP_GPIO_CTLE 0x10 129#define P3C_RG_SWRST_U3_PHYD BIT(25) 130#define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24) 131 132#define U3P_U3_PHYA_REG0 0x000 133#define P3A_RG_IEXT_INTR GENMASK(15, 10) 134#define P3A_RG_CLKDRV_OFF GENMASK(3, 2) 135 136#define U3P_U3_PHYA_REG1 0x004 137#define P3A_RG_CLKDRV_AMP GENMASK(31, 29) 138 139#define U3P_U3_PHYA_REG6 0x018 140#define P3A_RG_TX_EIDLE_CM GENMASK(31, 28) 141 142#define U3P_U3_PHYA_REG9 0x024 143#define P3A_RG_RX_DAC_MUX GENMASK(5, 1) 144 145#define U3P_U3_PHYA_DA_REG0 0x100 146#define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) 147#define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) 148#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) 149 150#define U3P_U3_PHYA_DA_REG4 0x108 151#define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) 152#define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) 153 154#define U3P_U3_PHYA_DA_REG5 0x10c 155#define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) 156#define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) 157 158#define U3P_U3_PHYA_DA_REG6 0x110 159#define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) 160 161#define U3P_U3_PHYA_DA_REG7 0x114 162#define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) 163 164#define U3P_U3_PHYA_DA_REG20 0x13c 165#define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) 166 167#define U3P_U3_PHYA_DA_REG25 0x148 168#define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) 169 170#define U3P_U3_PHYD_LFPS1 0x00c 171#define P3D_RG_FWAKE_TH GENMASK(21, 16) 172 173#define U3P_U3_PHYD_IMPCAL0 0x010 174#define P3D_RG_FORCE_TX_IMPEL BIT(31) 175#define P3D_RG_TX_IMPEL GENMASK(28, 24) 176 177#define U3P_U3_PHYD_IMPCAL1 0x014 178#define P3D_RG_FORCE_RX_IMPEL BIT(31) 179#define P3D_RG_RX_IMPEL GENMASK(28, 24) 180 181#define U3P_U3_PHYD_RSV 0x054 182#define P3D_RG_EFUSE_AUTO_LOAD_DIS BIT(12) 183 184#define U3P_U3_PHYD_CDR1 0x05c 185#define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) 186#define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) 187 188#define U3P_U3_PHYD_RXDET1 0x128 189#define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) 190 191#define U3P_U3_PHYD_RXDET2 0x12c 192#define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) 193 194#define U3P_SPLLC_XTALCTL3 0x018 195#define XC3_RG_U3_XTAL_RX_PWD BIT(9) 196#define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8) 197 198#define U3P_U2FREQ_FMCR0 0x00 199#define P2F_RG_MONCLK_SEL GENMASK(27, 26) 200#define P2F_RG_FREQDET_EN BIT(24) 201#define P2F_RG_CYCLECNT GENMASK(23, 0) 202 203#define U3P_U2FREQ_VALUE 0x0c 204 205#define U3P_U2FREQ_FMMONR1 0x10 206#define P2F_USB_FM_VALID BIT(0) 207#define P2F_RG_FRCK_EN BIT(8) 208 209#define U3P_REF_CLK 26 /* MHZ */ 210#define U3P_SLEW_RATE_COEF 28 211#define U3P_SR_COEF_DIVISOR 1000 212#define U3P_FM_DET_CYCLE_CNT 1024 213 214/* SATA register setting */ 215#define PHYD_CTRL_SIGNAL_MODE4 0x1c 216/* CDR Charge Pump P-path current adjustment */ 217#define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20) 218#define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8) 219 220#define PHYD_DESIGN_OPTION2 0x24 221/* Symbol lock count selection */ 222#define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4) 223 224#define PHYD_DESIGN_OPTION9 0x40 225/* COMWAK GAP width window */ 226#define RG_TG_MAX_MSK GENMASK(20, 16) 227/* COMINIT GAP width window */ 228#define RG_T2_MAX_MSK GENMASK(13, 8) 229/* COMWAK GAP width window */ 230#define RG_TG_MIN_MSK GENMASK(7, 5) 231/* COMINIT GAP width window */ 232#define RG_T2_MIN_MSK GENMASK(4, 0) 233 234#define ANA_RG_CTRL_SIGNAL1 0x4c 235/* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */ 236#define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8) 237 238#define ANA_RG_CTRL_SIGNAL4 0x58 239#define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20) 240/* Loop filter R1 resistance adjustment for Gen1 speed */ 241#define RG_CDR_BR_GEN2_MSK GENMASK(10, 8) 242 243#define ANA_RG_CTRL_SIGNAL6 0x60 244/* I-path capacitance adjustment for Gen1 */ 245#define RG_CDR_BC_GEN1_MSK GENMASK(28, 24) 246#define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0) 247 248#define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c 249/* RX Gen1 LEQ tuning step */ 250#define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8) 251 252#define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8 253#define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16) 254 255#define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc 256#define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) 257 258/* PHY switch between pcie/usb3/sgmii/sata */ 259#define USB_PHY_SWITCH_CTRL 0x0 260#define RG_PHY_SW_TYPE GENMASK(3, 0) 261#define RG_PHY_SW_PCIE 0x0 262#define RG_PHY_SW_USB3 0x1 263#define RG_PHY_SW_SGMII 0x2 264#define RG_PHY_SW_SATA 0x3 265 266#define TPHY_CLKS_CNT 2 267 268#define USER_BUF_LEN(count) min_t(size_t, 8, (count)) 269 270enum mtk_phy_version { 271 MTK_PHY_V1 = 1, 272 MTK_PHY_V2, 273 MTK_PHY_V3, 274}; 275 276struct mtk_phy_pdata { 277 /* avoid RX sensitivity level degradation only for mt8173 */ 278 bool avoid_rx_sen_degradation; 279 /* 280 * workaround only for mt8195, HW fix it for others of V3, 281 * u2phy should use integer mode instead of fractional mode of 282 * 48M PLL, fix it by switching PLL to 26M from default 48M 283 */ 284 bool sw_pll_48m_to_26m; 285 /* 286 * Some SoCs (e.g. mt8195) drop a bit when use auto load efuse, 287 * support sw way, also support it for v2/v3 optionally. 288 */ 289 bool sw_efuse_supported; 290 enum mtk_phy_version version; 291}; 292 293struct u2phy_banks { 294 void __iomem *misc; 295 void __iomem *fmreg; 296 void __iomem *com; 297}; 298 299struct u3phy_banks { 300 void __iomem *spllc; 301 void __iomem *chip; 302 void __iomem *phyd; /* include u3phyd_bank2 */ 303 void __iomem *phya; /* include u3phya_da */ 304}; 305 306struct mtk_phy_instance { 307 struct phy *phy; 308 void __iomem *port_base; 309 union { 310 struct u2phy_banks u2_banks; 311 struct u3phy_banks u3_banks; 312 }; 313 struct clk_bulk_data clks[TPHY_CLKS_CNT]; 314 u32 index; 315 u32 type; 316 struct regmap *type_sw; 317 u32 type_sw_reg; 318 u32 type_sw_index; 319 u32 efuse_sw_en; 320 u32 efuse_intr; 321 u32 efuse_tx_imp; 322 u32 efuse_rx_imp; 323 int eye_src; 324 int eye_vrt; 325 int eye_term; 326 int intr; 327 int discth; 328 int pre_emphasis; 329 bool bc12_en; 330}; 331 332struct mtk_tphy { 333 struct device *dev; 334 void __iomem *sif_base; /* only shared sif */ 335 const struct mtk_phy_pdata *pdata; 336 struct mtk_phy_instance **phys; 337 int nphys; 338 int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ 339 int src_coef; /* coefficient for slew rate calibrate */ 340}; 341 342#if IS_ENABLED(CONFIG_DEBUG_FS) 343 344enum u2_phy_params { 345 U2P_EYE_VRT = 0, 346 U2P_EYE_TERM, 347 U2P_EFUSE_EN, 348 U2P_EFUSE_INTR, 349 U2P_DISCTH, 350 U2P_PRE_EMPHASIS, 351}; 352 353enum u3_phy_params { 354 U3P_EFUSE_EN = 0, 355 U3P_EFUSE_INTR, 356 U3P_EFUSE_TX_IMP, 357 U3P_EFUSE_RX_IMP, 358}; 359 360static const char *const u2_phy_files[] = { 361 [U2P_EYE_VRT] = "vrt", 362 [U2P_EYE_TERM] = "term", 363 [U2P_EFUSE_EN] = "efuse", 364 [U2P_EFUSE_INTR] = "intr", 365 [U2P_DISCTH] = "discth", 366 [U2P_PRE_EMPHASIS] = "preemph", 367}; 368 369static const char *const u3_phy_files[] = { 370 [U3P_EFUSE_EN] = "efuse", 371 [U3P_EFUSE_INTR] = "intr", 372 [U3P_EFUSE_TX_IMP] = "tx-imp", 373 [U3P_EFUSE_RX_IMP] = "rx-imp", 374}; 375 376static int u2_phy_params_show(struct seq_file *sf, void *unused) 377{ 378 struct mtk_phy_instance *inst = sf->private; 379 const char *fname = file_dentry(sf->file)->d_iname; 380 struct u2phy_banks *u2_banks = &inst->u2_banks; 381 void __iomem *com = u2_banks->com; 382 u32 max = 0; 383 u32 tmp = 0; 384 u32 val = 0; 385 int ret; 386 387 ret = match_string(u2_phy_files, ARRAY_SIZE(u2_phy_files), fname); 388 if (ret < 0) 389 return ret; 390 391 switch (ret) { 392 case U2P_EYE_VRT: 393 tmp = readl(com + U3P_USBPHYACR1); 394 val = FIELD_GET(PA1_RG_VRT_SEL, tmp); 395 max = FIELD_MAX(PA1_RG_VRT_SEL); 396 break; 397 398 case U2P_EYE_TERM: 399 tmp = readl(com + U3P_USBPHYACR1); 400 val = FIELD_GET(PA1_RG_TERM_SEL, tmp); 401 max = FIELD_MAX(PA1_RG_TERM_SEL); 402 break; 403 404 case U2P_EFUSE_EN: 405 if (u2_banks->misc) { 406 tmp = readl(u2_banks->misc + U3P_MISC_REG1); 407 max = 1; 408 } 409 410 val = !!(tmp & MR1_EFUSE_AUTO_LOAD_DIS); 411 break; 412 413 case U2P_EFUSE_INTR: 414 tmp = readl(com + U3P_USBPHYACR1); 415 val = FIELD_GET(PA1_RG_INTR_CAL, tmp); 416 max = FIELD_MAX(PA1_RG_INTR_CAL); 417 break; 418 419 case U2P_DISCTH: 420 tmp = readl(com + U3P_USBPHYACR6); 421 val = FIELD_GET(PA6_RG_U2_DISCTH, tmp); 422 max = FIELD_MAX(PA6_RG_U2_DISCTH); 423 break; 424 425 case U2P_PRE_EMPHASIS: 426 tmp = readl(com + U3P_USBPHYACR6); 427 val = FIELD_GET(PA6_RG_U2_PRE_EMP, tmp); 428 max = FIELD_MAX(PA6_RG_U2_PRE_EMP); 429 break; 430 431 default: 432 seq_printf(sf, "invalid, %d\n", ret); 433 break; 434 } 435 436 seq_printf(sf, "%s : %d [0, %d]\n", fname, val, max); 437 438 return 0; 439} 440 441static int u2_phy_params_open(struct inode *inode, struct file *file) 442{ 443 return single_open(file, u2_phy_params_show, inode->i_private); 444} 445 446static ssize_t u2_phy_params_write(struct file *file, const char __user *ubuf, 447 size_t count, loff_t *ppos) 448{ 449 const char *fname = file_dentry(file)->d_iname; 450 struct seq_file *sf = file->private_data; 451 struct mtk_phy_instance *inst = sf->private; 452 struct u2phy_banks *u2_banks = &inst->u2_banks; 453 void __iomem *com = u2_banks->com; 454 ssize_t rc; 455 u32 val; 456 int ret; 457 458 rc = kstrtouint_from_user(ubuf, USER_BUF_LEN(count), 0, &val); 459 if (rc) 460 return rc; 461 462 ret = match_string(u2_phy_files, ARRAY_SIZE(u2_phy_files), fname); 463 if (ret < 0) 464 return (ssize_t)ret; 465 466 switch (ret) { 467 case U2P_EYE_VRT: 468 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, val); 469 break; 470 471 case U2P_EYE_TERM: 472 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, val); 473 break; 474 475 case U2P_EFUSE_EN: 476 if (u2_banks->misc) 477 mtk_phy_update_field(u2_banks->misc + U3P_MISC_REG1, 478 MR1_EFUSE_AUTO_LOAD_DIS, !!val); 479 break; 480 481 case U2P_EFUSE_INTR: 482 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, val); 483 break; 484 485 case U2P_DISCTH: 486 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, val); 487 break; 488 489 case U2P_PRE_EMPHASIS: 490 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, val); 491 break; 492 493 default: 494 break; 495 } 496 497 return count; 498} 499 500static const struct file_operations u2_phy_fops = { 501 .open = u2_phy_params_open, 502 .write = u2_phy_params_write, 503 .read = seq_read, 504 .llseek = seq_lseek, 505 .release = single_release, 506}; 507 508static void u2_phy_dbgfs_files_create(struct mtk_phy_instance *inst) 509{ 510 u32 count = ARRAY_SIZE(u2_phy_files); 511 int i; 512 513 for (i = 0; i < count; i++) 514 debugfs_create_file(u2_phy_files[i], 0644, inst->phy->debugfs, 515 inst, &u2_phy_fops); 516} 517 518static int u3_phy_params_show(struct seq_file *sf, void *unused) 519{ 520 struct mtk_phy_instance *inst = sf->private; 521 const char *fname = file_dentry(sf->file)->d_iname; 522 struct u3phy_banks *u3_banks = &inst->u3_banks; 523 u32 val = 0; 524 u32 max = 0; 525 u32 tmp; 526 int ret; 527 528 ret = match_string(u3_phy_files, ARRAY_SIZE(u3_phy_files), fname); 529 if (ret < 0) 530 return ret; 531 532 switch (ret) { 533 case U3P_EFUSE_EN: 534 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); 535 val = !!(tmp & P3D_RG_EFUSE_AUTO_LOAD_DIS); 536 max = 1; 537 break; 538 539 case U3P_EFUSE_INTR: 540 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); 541 val = FIELD_GET(P3A_RG_IEXT_INTR, tmp); 542 max = FIELD_MAX(P3A_RG_IEXT_INTR); 543 break; 544 545 case U3P_EFUSE_TX_IMP: 546 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); 547 val = FIELD_GET(P3D_RG_TX_IMPEL, tmp); 548 max = FIELD_MAX(P3D_RG_TX_IMPEL); 549 break; 550 551 case U3P_EFUSE_RX_IMP: 552 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); 553 val = FIELD_GET(P3D_RG_RX_IMPEL, tmp); 554 max = FIELD_MAX(P3D_RG_RX_IMPEL); 555 break; 556 557 default: 558 seq_printf(sf, "invalid, %d\n", ret); 559 break; 560 } 561 562 seq_printf(sf, "%s : %d [0, %d]\n", fname, val, max); 563 564 return 0; 565} 566 567static int u3_phy_params_open(struct inode *inode, struct file *file) 568{ 569 return single_open(file, u3_phy_params_show, inode->i_private); 570} 571 572static ssize_t u3_phy_params_write(struct file *file, const char __user *ubuf, 573 size_t count, loff_t *ppos) 574{ 575 const char *fname = file_dentry(file)->d_iname; 576 struct seq_file *sf = file->private_data; 577 struct mtk_phy_instance *inst = sf->private; 578 struct u3phy_banks *u3_banks = &inst->u3_banks; 579 void __iomem *phyd = u3_banks->phyd; 580 ssize_t rc; 581 u32 val; 582 int ret; 583 584 rc = kstrtouint_from_user(ubuf, USER_BUF_LEN(count), 0, &val); 585 if (rc) 586 return rc; 587 588 ret = match_string(u3_phy_files, ARRAY_SIZE(u3_phy_files), fname); 589 if (ret < 0) 590 return (ssize_t)ret; 591 592 switch (ret) { 593 case U3P_EFUSE_EN: 594 mtk_phy_update_field(phyd + U3P_U3_PHYD_RSV, 595 P3D_RG_EFUSE_AUTO_LOAD_DIS, !!val); 596 break; 597 598 case U3P_EFUSE_INTR: 599 mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, 600 P3A_RG_IEXT_INTR, val); 601 break; 602 603 case U3P_EFUSE_TX_IMP: 604 mtk_phy_update_field(phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL, val); 605 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL); 606 break; 607 608 case U3P_EFUSE_RX_IMP: 609 mtk_phy_update_field(phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL, val); 610 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL); 611 break; 612 613 default: 614 break; 615 } 616 617 return count; 618} 619 620static const struct file_operations u3_phy_fops = { 621 .open = u3_phy_params_open, 622 .write = u3_phy_params_write, 623 .read = seq_read, 624 .llseek = seq_lseek, 625 .release = single_release, 626}; 627 628static void u3_phy_dbgfs_files_create(struct mtk_phy_instance *inst) 629{ 630 u32 count = ARRAY_SIZE(u3_phy_files); 631 int i; 632 633 for (i = 0; i < count; i++) 634 debugfs_create_file(u3_phy_files[i], 0644, inst->phy->debugfs, 635 inst, &u3_phy_fops); 636} 637 638static int phy_type_show(struct seq_file *sf, void *unused) 639{ 640 struct mtk_phy_instance *inst = sf->private; 641 const char *type; 642 643 switch (inst->type) { 644 case PHY_TYPE_USB2: 645 type = "USB2"; 646 break; 647 case PHY_TYPE_USB3: 648 type = "USB3"; 649 break; 650 case PHY_TYPE_PCIE: 651 type = "PCIe"; 652 break; 653 case PHY_TYPE_SGMII: 654 type = "SGMII"; 655 break; 656 case PHY_TYPE_SATA: 657 type = "SATA"; 658 break; 659 default: 660 type = ""; 661 } 662 663 seq_printf(sf, "%s\n", type); 664 665 return 0; 666} 667DEFINE_SHOW_ATTRIBUTE(phy_type); 668 669/* these files will be removed when phy is released by phy core */ 670static void phy_debugfs_init(struct mtk_phy_instance *inst) 671{ 672 debugfs_create_file("type", 0444, inst->phy->debugfs, inst, &phy_type_fops); 673 674 switch (inst->type) { 675 case PHY_TYPE_USB2: 676 u2_phy_dbgfs_files_create(inst); 677 break; 678 case PHY_TYPE_USB3: 679 case PHY_TYPE_PCIE: 680 u3_phy_dbgfs_files_create(inst); 681 break; 682 default: 683 break; 684 } 685} 686 687#else 688 689static void phy_debugfs_init(struct mtk_phy_instance *inst) 690{} 691 692#endif 693 694static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, 695 struct mtk_phy_instance *instance) 696{ 697 struct u2phy_banks *u2_banks = &instance->u2_banks; 698 void __iomem *fmreg = u2_banks->fmreg; 699 void __iomem *com = u2_banks->com; 700 int calibration_val; 701 int fm_out; 702 u32 tmp; 703 704 /* HW V3 doesn't support slew rate cal anymore */ 705 if (tphy->pdata->version == MTK_PHY_V3) 706 return; 707 708 /* use force value */ 709 if (instance->eye_src) 710 return; 711 712 /* enable USB ring oscillator */ 713 mtk_phy_set_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN); 714 udelay(1); 715 716 /*enable free run clock */ 717 mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); 718 719 /* set cycle count as 1024, and select u2 channel */ 720 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); 721 tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL); 722 tmp |= FIELD_PREP(P2F_RG_CYCLECNT, U3P_FM_DET_CYCLE_CNT); 723 if (tphy->pdata->version == MTK_PHY_V1) 724 tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1); 725 726 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); 727 728 /* enable frequency meter */ 729 mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); 730 731 /* ignore return value */ 732 readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp, 733 (tmp & P2F_USB_FM_VALID), 10, 200); 734 735 fm_out = readl(fmreg + U3P_U2FREQ_VALUE); 736 737 /* disable frequency meter */ 738 mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); 739 740 /*disable free run clock */ 741 mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); 742 743 if (fm_out) { 744 /* ( 1024 / FM_OUT ) x reference clock frequency x coef */ 745 tmp = tphy->src_ref_clk * tphy->src_coef; 746 tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out; 747 calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR); 748 } else { 749 /* if FM detection fail, set default value */ 750 calibration_val = 4; 751 } 752 dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n", 753 instance->index, fm_out, calibration_val, 754 tphy->src_ref_clk, tphy->src_coef); 755 756 /* set HS slew rate */ 757 mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, 758 calibration_val); 759 760 /* disable USB ring oscillator */ 761 mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN); 762} 763 764static void u3_phy_instance_init(struct mtk_tphy *tphy, 765 struct mtk_phy_instance *instance) 766{ 767 struct u3phy_banks *u3_banks = &instance->u3_banks; 768 void __iomem *phya = u3_banks->phya; 769 void __iomem *phyd = u3_banks->phyd; 770 771 /* gating PCIe Analog XTAL clock */ 772 mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3, 773 XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD); 774 775 /* gating XSQ */ 776 mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG0, P3A_RG_XTAL_EXT_EN_U3, 2); 777 778 mtk_phy_update_field(phya + U3P_U3_PHYA_REG9, P3A_RG_RX_DAC_MUX, 4); 779 780 mtk_phy_update_field(phya + U3P_U3_PHYA_REG6, P3A_RG_TX_EIDLE_CM, 0xe); 781 782 mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1, 783 P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1, 784 FIELD_PREP(P3D_RG_CDR_BIR_LTD0, 0xc) | 785 FIELD_PREP(P3D_RG_CDR_BIR_LTD1, 0x3)); 786 787 mtk_phy_update_field(phyd + U3P_U3_PHYD_LFPS1, P3D_RG_FWAKE_TH, 0x34); 788 789 mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET1, P3D_RG_RXDET_STB2_SET, 0x10); 790 791 mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET2, P3D_RG_RXDET_STB2_SET_P3, 0x10); 792 793 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 794} 795 796static void u2_phy_pll_26m_set(struct mtk_tphy *tphy, 797 struct mtk_phy_instance *instance) 798{ 799 struct u2phy_banks *u2_banks = &instance->u2_banks; 800 void __iomem *com = u2_banks->com; 801 802 if (!tphy->pdata->sw_pll_48m_to_26m) 803 return; 804 805 mtk_phy_update_field(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, 0); 806 807 mtk_phy_update_field(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, 3); 808 809 writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV); 810 811 mtk_phy_set_bits(com + U3P_U2PHYA_RESV1, 812 P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL); 813} 814 815static void u2_phy_instance_init(struct mtk_tphy *tphy, 816 struct mtk_phy_instance *instance) 817{ 818 struct u2phy_banks *u2_banks = &instance->u2_banks; 819 void __iomem *com = u2_banks->com; 820 u32 index = instance->index; 821 822 /* switch to USB function, and enable usb pll */ 823 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM); 824 825 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, 826 P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); 827 828 mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_UART_EN); 829 830 mtk_phy_set_bits(com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN); 831 832 /* disable switch 100uA current to SSUSB */ 833 mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN); 834 835 mtk_phy_clear_bits(com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK); 836 837 if (tphy->pdata->avoid_rx_sen_degradation) { 838 if (!index) { 839 mtk_phy_set_bits(com + U3P_USBPHYACR2, PA2_RG_SIF_U2PLL_FORCE_EN); 840 841 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); 842 } else { 843 mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); 844 845 mtk_phy_set_bits(com + U3P_U2PHYDTM0, 846 P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM); 847 } 848 } 849 850 /* DP/DM BC1.1 path Disable */ 851 mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN); 852 853 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, 2); 854 855 /* Workaround only for mt8195, HW fix it for others (V3) */ 856 u2_phy_pll_26m_set(tphy, instance); 857 858 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 859} 860 861static void u2_phy_instance_power_on(struct mtk_tphy *tphy, 862 struct mtk_phy_instance *instance) 863{ 864 struct u2phy_banks *u2_banks = &instance->u2_banks; 865 void __iomem *com = u2_banks->com; 866 u32 index = instance->index; 867 868 /* OTG Enable */ 869 mtk_phy_set_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN); 870 871 mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID); 872 873 mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND); 874 875 if (tphy->pdata->avoid_rx_sen_degradation && index) { 876 mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); 877 878 mtk_phy_set_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM); 879 } 880 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 881} 882 883static void u2_phy_instance_power_off(struct mtk_tphy *tphy, 884 struct mtk_phy_instance *instance) 885{ 886 struct u2phy_banks *u2_banks = &instance->u2_banks; 887 void __iomem *com = u2_banks->com; 888 u32 index = instance->index; 889 890 /* OTG Disable */ 891 mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN); 892 893 mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID); 894 895 mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND); 896 897 if (tphy->pdata->avoid_rx_sen_degradation && index) { 898 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM); 899 900 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); 901 } 902 903 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 904} 905 906static void u2_phy_instance_exit(struct mtk_tphy *tphy, 907 struct mtk_phy_instance *instance) 908{ 909 struct u2phy_banks *u2_banks = &instance->u2_banks; 910 void __iomem *com = u2_banks->com; 911 u32 index = instance->index; 912 913 if (tphy->pdata->avoid_rx_sen_degradation && index) { 914 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); 915 916 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM); 917 } 918} 919 920static void u2_phy_instance_set_mode(struct mtk_tphy *tphy, 921 struct mtk_phy_instance *instance, 922 enum phy_mode mode) 923{ 924 struct u2phy_banks *u2_banks = &instance->u2_banks; 925 u32 tmp; 926 927 tmp = readl(u2_banks->com + U3P_U2PHYDTM1); 928 switch (mode) { 929 case PHY_MODE_USB_DEVICE: 930 tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG; 931 break; 932 case PHY_MODE_USB_HOST: 933 tmp |= P2C_FORCE_IDDIG; 934 tmp &= ~P2C_RG_IDDIG; 935 break; 936 case PHY_MODE_USB_OTG: 937 tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG); 938 break; 939 default: 940 return; 941 } 942 writel(tmp, u2_banks->com + U3P_U2PHYDTM1); 943} 944 945static void pcie_phy_instance_init(struct mtk_tphy *tphy, 946 struct mtk_phy_instance *instance) 947{ 948 struct u3phy_banks *u3_banks = &instance->u3_banks; 949 void __iomem *phya = u3_banks->phya; 950 951 if (tphy->pdata->version != MTK_PHY_V1) 952 return; 953 954 mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0, 955 P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, 956 FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) | 957 FIELD_PREP(P3A_RG_XTAL_EXT_PE2H, 0x2)); 958 959 /* ref clk drive */ 960 mtk_phy_update_field(phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, 0x4); 961 962 mtk_phy_update_field(phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, 0x1); 963 964 /* SSC delta -5000ppm */ 965 mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG20, P3A_RG_PLL_DELTA1_PE2H, 0x3c); 966 967 mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG25, P3A_RG_PLL_DELTA_PE2H, 0x36); 968 969 /* change pll BW 0.6M */ 970 mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG5, 971 P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H, 972 FIELD_PREP(P3A_RG_PLL_BR_PE2H, 0x1) | 973 FIELD_PREP(P3A_RG_PLL_IC_PE2H, 0x1)); 974 975 mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG4, 976 P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H, 977 FIELD_PREP(P3A_RG_PLL_BC_PE2H, 0x3)); 978 979 mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG6, P3A_RG_PLL_IR_PE2H, 0x2); 980 981 mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG7, P3A_RG_PLL_BP_PE2H, 0xa); 982 983 /* Tx Detect Rx Timing: 10us -> 5us */ 984 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1, 985 P3D_RG_RXDET_STB2_SET, 0x10); 986 987 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2, 988 P3D_RG_RXDET_STB2_SET_P3, 0x10); 989 990 /* wait for PCIe subsys register to active */ 991 usleep_range(2500, 3000); 992 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 993} 994 995static void pcie_phy_instance_power_on(struct mtk_tphy *tphy, 996 struct mtk_phy_instance *instance) 997{ 998 struct u3phy_banks *bank = &instance->u3_banks; 999 1000 mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD, 1001 P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); 1002 1003 mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE, 1004 P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); 1005} 1006 1007static void pcie_phy_instance_power_off(struct mtk_tphy *tphy, 1008 struct mtk_phy_instance *instance) 1009 1010{ 1011 struct u3phy_banks *bank = &instance->u3_banks; 1012 1013 mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD, 1014 P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); 1015 1016 mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE, 1017 P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); 1018} 1019 1020static void sata_phy_instance_init(struct mtk_tphy *tphy, 1021 struct mtk_phy_instance *instance) 1022{ 1023 struct u3phy_banks *u3_banks = &instance->u3_banks; 1024 void __iomem *phyd = u3_banks->phyd; 1025 1026 /* charge current adjustment */ 1027 mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL6, 1028 RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK, 1029 FIELD_PREP(RG_CDR_BIRLTR_GEN1_MSK, 0x6) | 1030 FIELD_PREP(RG_CDR_BC_GEN1_MSK, 0x1a)); 1031 1032 mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL4, RG_CDR_BIRLTD0_GEN1_MSK, 0x18); 1033 1034 mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL5, RG_CDR_BIRLTD0_GEN3_MSK, 0x06); 1035 1036 mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL4, 1037 RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK, 1038 FIELD_PREP(RG_CDR_BICLTR_GEN1_MSK, 0x0c) | 1039 FIELD_PREP(RG_CDR_BR_GEN2_MSK, 0x07)); 1040 1041 mtk_phy_update_bits(phyd + PHYD_CTRL_SIGNAL_MODE4, 1042 RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK, 1043 FIELD_PREP(RG_CDR_BICLTD0_GEN1_MSK, 0x08) | 1044 FIELD_PREP(RG_CDR_BICLTD1_GEN1_MSK, 0x02)); 1045 1046 mtk_phy_update_field(phyd + PHYD_DESIGN_OPTION2, RG_LOCK_CNT_SEL_MSK, 0x02); 1047 1048 mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9, 1049 RG_T2_MIN_MSK | RG_TG_MIN_MSK, 1050 FIELD_PREP(RG_T2_MIN_MSK, 0x12) | 1051 FIELD_PREP(RG_TG_MIN_MSK, 0x04)); 1052 1053 mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9, 1054 RG_T2_MAX_MSK | RG_TG_MAX_MSK, 1055 FIELD_PREP(RG_T2_MAX_MSK, 0x31) | 1056 FIELD_PREP(RG_TG_MAX_MSK, 0x0e)); 1057 1058 mtk_phy_update_field(phyd + ANA_RG_CTRL_SIGNAL1, RG_IDRV_0DB_GEN1_MSK, 0x20); 1059 1060 mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL1, RG_EQ_DLEQ_LFI_GEN1_MSK, 0x03); 1061 1062 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 1063} 1064 1065static void phy_v1_banks_init(struct mtk_tphy *tphy, 1066 struct mtk_phy_instance *instance) 1067{ 1068 struct u2phy_banks *u2_banks = &instance->u2_banks; 1069 struct u3phy_banks *u3_banks = &instance->u3_banks; 1070 1071 switch (instance->type) { 1072 case PHY_TYPE_USB2: 1073 u2_banks->misc = NULL; 1074 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; 1075 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM; 1076 break; 1077 case PHY_TYPE_USB3: 1078 case PHY_TYPE_PCIE: 1079 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; 1080 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; 1081 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; 1082 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; 1083 break; 1084 case PHY_TYPE_SATA: 1085 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; 1086 break; 1087 default: 1088 dev_err(tphy->dev, "incompatible PHY type\n"); 1089 return; 1090 } 1091} 1092 1093static void phy_v2_banks_init(struct mtk_tphy *tphy, 1094 struct mtk_phy_instance *instance) 1095{ 1096 struct u2phy_banks *u2_banks = &instance->u2_banks; 1097 struct u3phy_banks *u3_banks = &instance->u3_banks; 1098 1099 switch (instance->type) { 1100 case PHY_TYPE_USB2: 1101 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; 1102 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; 1103 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; 1104 break; 1105 case PHY_TYPE_USB3: 1106 case PHY_TYPE_PCIE: 1107 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; 1108 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; 1109 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; 1110 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; 1111 break; 1112 default: 1113 dev_err(tphy->dev, "incompatible PHY type\n"); 1114 return; 1115 } 1116} 1117 1118static void phy_parse_property(struct mtk_tphy *tphy, 1119 struct mtk_phy_instance *instance) 1120{ 1121 struct device *dev = &instance->phy->dev; 1122 1123 if (instance->type != PHY_TYPE_USB2) 1124 return; 1125 1126 instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12"); 1127 device_property_read_u32(dev, "mediatek,eye-src", 1128 &instance->eye_src); 1129 device_property_read_u32(dev, "mediatek,eye-vrt", 1130 &instance->eye_vrt); 1131 device_property_read_u32(dev, "mediatek,eye-term", 1132 &instance->eye_term); 1133 device_property_read_u32(dev, "mediatek,intr", 1134 &instance->intr); 1135 device_property_read_u32(dev, "mediatek,discth", 1136 &instance->discth); 1137 device_property_read_u32(dev, "mediatek,pre-emphasis", 1138 &instance->pre_emphasis); 1139 dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n", 1140 instance->bc12_en, instance->eye_src, 1141 instance->eye_vrt, instance->eye_term, 1142 instance->intr, instance->discth); 1143 dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis); 1144} 1145 1146static void u2_phy_props_set(struct mtk_tphy *tphy, 1147 struct mtk_phy_instance *instance) 1148{ 1149 struct u2phy_banks *u2_banks = &instance->u2_banks; 1150 void __iomem *com = u2_banks->com; 1151 1152 if (instance->bc12_en) /* BC1.2 path Enable */ 1153 mtk_phy_set_bits(com + U3P_U2PHYBC12C, P2C_RG_CHGDT_EN); 1154 1155 if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src) 1156 mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, 1157 instance->eye_src); 1158 1159 if (instance->eye_vrt) 1160 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, 1161 instance->eye_vrt); 1162 1163 if (instance->eye_term) 1164 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, 1165 instance->eye_term); 1166 1167 if (instance->intr) { 1168 if (u2_banks->misc) 1169 mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, 1170 MR1_EFUSE_AUTO_LOAD_DIS); 1171 1172 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, 1173 instance->intr); 1174 } 1175 1176 if (instance->discth) 1177 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, 1178 instance->discth); 1179 1180 if (instance->pre_emphasis) 1181 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, 1182 instance->pre_emphasis); 1183} 1184 1185/* type switch for usb3/pcie/sgmii/sata */ 1186static int phy_type_syscon_get(struct mtk_phy_instance *instance, 1187 struct device_node *dn) 1188{ 1189 struct of_phandle_args args; 1190 int ret; 1191 1192 /* type switch function is optional */ 1193 if (!of_property_read_bool(dn, "mediatek,syscon-type")) 1194 return 0; 1195 1196 ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type", 1197 2, 0, &args); 1198 if (ret) 1199 return ret; 1200 1201 instance->type_sw_reg = args.args[0]; 1202 instance->type_sw_index = args.args[1] & 0x3; /* <=3 */ 1203 instance->type_sw = syscon_node_to_regmap(args.np); 1204 of_node_put(args.np); 1205 dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n", 1206 instance->type_sw_reg, instance->type_sw_index); 1207 1208 return PTR_ERR_OR_ZERO(instance->type_sw); 1209} 1210 1211static int phy_type_set(struct mtk_phy_instance *instance) 1212{ 1213 int type; 1214 u32 offset; 1215 1216 if (!instance->type_sw) 1217 return 0; 1218 1219 switch (instance->type) { 1220 case PHY_TYPE_USB3: 1221 type = RG_PHY_SW_USB3; 1222 break; 1223 case PHY_TYPE_PCIE: 1224 type = RG_PHY_SW_PCIE; 1225 break; 1226 case PHY_TYPE_SGMII: 1227 type = RG_PHY_SW_SGMII; 1228 break; 1229 case PHY_TYPE_SATA: 1230 type = RG_PHY_SW_SATA; 1231 break; 1232 case PHY_TYPE_USB2: 1233 default: 1234 return 0; 1235 } 1236 1237 offset = instance->type_sw_index * BITS_PER_BYTE; 1238 regmap_update_bits(instance->type_sw, instance->type_sw_reg, 1239 RG_PHY_SW_TYPE << offset, type << offset); 1240 1241 return 0; 1242} 1243 1244static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) 1245{ 1246 struct device *dev = &instance->phy->dev; 1247 int ret = 0; 1248 1249 /* tphy v1 doesn't support sw efuse, skip it */ 1250 if (!tphy->pdata->sw_efuse_supported) { 1251 instance->efuse_sw_en = 0; 1252 return 0; 1253 } 1254 1255 /* software efuse is optional */ 1256 instance->efuse_sw_en = device_property_read_bool(dev, "nvmem-cells"); 1257 if (!instance->efuse_sw_en) 1258 return 0; 1259 1260 switch (instance->type) { 1261 case PHY_TYPE_USB2: 1262 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); 1263 if (ret) { 1264 dev_err(dev, "fail to get u2 intr efuse, %d\n", ret); 1265 break; 1266 } 1267 1268 /* no efuse, ignore it */ 1269 if (!instance->efuse_intr) { 1270 dev_warn(dev, "no u2 intr efuse, but dts enable it\n"); 1271 instance->efuse_sw_en = 0; 1272 break; 1273 } 1274 1275 dev_dbg(dev, "u2 efuse - intr %x\n", instance->efuse_intr); 1276 break; 1277 1278 case PHY_TYPE_USB3: 1279 case PHY_TYPE_PCIE: 1280 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); 1281 if (ret) { 1282 dev_err(dev, "fail to get u3 intr efuse, %d\n", ret); 1283 break; 1284 } 1285 1286 ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp", &instance->efuse_rx_imp); 1287 if (ret) { 1288 dev_err(dev, "fail to get u3 rx_imp efuse, %d\n", ret); 1289 break; 1290 } 1291 1292 ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp", &instance->efuse_tx_imp); 1293 if (ret) { 1294 dev_err(dev, "fail to get u3 tx_imp efuse, %d\n", ret); 1295 break; 1296 } 1297 1298 /* no efuse, ignore it */ 1299 if (!instance->efuse_intr && 1300 !instance->efuse_rx_imp && 1301 !instance->efuse_tx_imp) { 1302 dev_warn(dev, "no u3 intr efuse, but dts enable it\n"); 1303 instance->efuse_sw_en = 0; 1304 break; 1305 } 1306 1307 dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n", 1308 instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp); 1309 break; 1310 default: 1311 dev_err(dev, "no sw efuse for type %d\n", instance->type); 1312 ret = -EINVAL; 1313 } 1314 1315 return ret; 1316} 1317 1318static void phy_efuse_set(struct mtk_phy_instance *instance) 1319{ 1320 struct device *dev = &instance->phy->dev; 1321 struct u2phy_banks *u2_banks = &instance->u2_banks; 1322 struct u3phy_banks *u3_banks = &instance->u3_banks; 1323 1324 if (!instance->efuse_sw_en) 1325 return; 1326 1327 switch (instance->type) { 1328 case PHY_TYPE_USB2: 1329 mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, MR1_EFUSE_AUTO_LOAD_DIS); 1330 1331 mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, 1332 instance->efuse_intr); 1333 break; 1334 case PHY_TYPE_USB3: 1335 case PHY_TYPE_PCIE: 1336 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_RSV, P3D_RG_EFUSE_AUTO_LOAD_DIS); 1337 1338 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL, 1339 instance->efuse_tx_imp); 1340 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL); 1341 1342 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL, 1343 instance->efuse_rx_imp); 1344 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL); 1345 1346 mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR, 1347 instance->efuse_intr); 1348 break; 1349 default: 1350 dev_warn(dev, "no sw efuse for type %d\n", instance->type); 1351 break; 1352 } 1353} 1354 1355static int mtk_phy_init(struct phy *phy) 1356{ 1357 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 1358 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 1359 int ret; 1360 1361 ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks); 1362 if (ret) 1363 return ret; 1364 1365 phy_efuse_set(instance); 1366 1367 switch (instance->type) { 1368 case PHY_TYPE_USB2: 1369 u2_phy_instance_init(tphy, instance); 1370 u2_phy_props_set(tphy, instance); 1371 break; 1372 case PHY_TYPE_USB3: 1373 u3_phy_instance_init(tphy, instance); 1374 break; 1375 case PHY_TYPE_PCIE: 1376 pcie_phy_instance_init(tphy, instance); 1377 break; 1378 case PHY_TYPE_SATA: 1379 sata_phy_instance_init(tphy, instance); 1380 break; 1381 case PHY_TYPE_SGMII: 1382 /* nothing to do, only used to set type */ 1383 break; 1384 default: 1385 dev_err(tphy->dev, "incompatible PHY type\n"); 1386 clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks); 1387 return -EINVAL; 1388 } 1389 1390 return 0; 1391} 1392 1393static int mtk_phy_power_on(struct phy *phy) 1394{ 1395 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 1396 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 1397 1398 if (instance->type == PHY_TYPE_USB2) { 1399 u2_phy_instance_power_on(tphy, instance); 1400 hs_slew_rate_calibrate(tphy, instance); 1401 } else if (instance->type == PHY_TYPE_PCIE) { 1402 pcie_phy_instance_power_on(tphy, instance); 1403 } 1404 1405 return 0; 1406} 1407 1408static int mtk_phy_power_off(struct phy *phy) 1409{ 1410 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 1411 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 1412 1413 if (instance->type == PHY_TYPE_USB2) 1414 u2_phy_instance_power_off(tphy, instance); 1415 else if (instance->type == PHY_TYPE_PCIE) 1416 pcie_phy_instance_power_off(tphy, instance); 1417 1418 return 0; 1419} 1420 1421static int mtk_phy_exit(struct phy *phy) 1422{ 1423 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 1424 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 1425 1426 if (instance->type == PHY_TYPE_USB2) 1427 u2_phy_instance_exit(tphy, instance); 1428 1429 clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks); 1430 return 0; 1431} 1432 1433static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) 1434{ 1435 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 1436 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 1437 1438 if (instance->type == PHY_TYPE_USB2) 1439 u2_phy_instance_set_mode(tphy, instance, mode); 1440 1441 return 0; 1442} 1443 1444static struct phy *mtk_phy_xlate(struct device *dev, 1445 struct of_phandle_args *args) 1446{ 1447 struct mtk_tphy *tphy = dev_get_drvdata(dev); 1448 struct mtk_phy_instance *instance = NULL; 1449 struct device_node *phy_np = args->np; 1450 int index; 1451 int ret; 1452 1453 if (args->args_count != 1) { 1454 dev_err(dev, "invalid number of cells in 'phy' property\n"); 1455 return ERR_PTR(-EINVAL); 1456 } 1457 1458 for (index = 0; index < tphy->nphys; index++) 1459 if (phy_np == tphy->phys[index]->phy->dev.of_node) { 1460 instance = tphy->phys[index]; 1461 break; 1462 } 1463 1464 if (!instance) { 1465 dev_err(dev, "failed to find appropriate phy\n"); 1466 return ERR_PTR(-EINVAL); 1467 } 1468 1469 instance->type = args->args[0]; 1470 if (!(instance->type == PHY_TYPE_USB2 || 1471 instance->type == PHY_TYPE_USB3 || 1472 instance->type == PHY_TYPE_PCIE || 1473 instance->type == PHY_TYPE_SATA || 1474 instance->type == PHY_TYPE_SGMII)) { 1475 dev_err(dev, "unsupported device type: %d\n", instance->type); 1476 return ERR_PTR(-EINVAL); 1477 } 1478 1479 switch (tphy->pdata->version) { 1480 case MTK_PHY_V1: 1481 phy_v1_banks_init(tphy, instance); 1482 break; 1483 case MTK_PHY_V2: 1484 case MTK_PHY_V3: 1485 phy_v2_banks_init(tphy, instance); 1486 break; 1487 default: 1488 dev_err(dev, "phy version is not supported\n"); 1489 return ERR_PTR(-EINVAL); 1490 } 1491 1492 ret = phy_efuse_get(tphy, instance); 1493 if (ret) 1494 return ERR_PTR(ret); 1495 1496 phy_parse_property(tphy, instance); 1497 phy_type_set(instance); 1498 phy_debugfs_init(instance); 1499 1500 return instance->phy; 1501} 1502 1503static const struct phy_ops mtk_tphy_ops = { 1504 .init = mtk_phy_init, 1505 .exit = mtk_phy_exit, 1506 .power_on = mtk_phy_power_on, 1507 .power_off = mtk_phy_power_off, 1508 .set_mode = mtk_phy_set_mode, 1509 .owner = THIS_MODULE, 1510}; 1511 1512static const struct mtk_phy_pdata tphy_v1_pdata = { 1513 .avoid_rx_sen_degradation = false, 1514 .version = MTK_PHY_V1, 1515}; 1516 1517static const struct mtk_phy_pdata tphy_v2_pdata = { 1518 .avoid_rx_sen_degradation = false, 1519 .sw_efuse_supported = true, 1520 .version = MTK_PHY_V2, 1521}; 1522 1523static const struct mtk_phy_pdata tphy_v3_pdata = { 1524 .sw_efuse_supported = true, 1525 .version = MTK_PHY_V3, 1526}; 1527 1528static const struct mtk_phy_pdata mt8173_pdata = { 1529 .avoid_rx_sen_degradation = true, 1530 .version = MTK_PHY_V1, 1531}; 1532 1533static const struct mtk_phy_pdata mt8195_pdata = { 1534 .sw_pll_48m_to_26m = true, 1535 .sw_efuse_supported = true, 1536 .version = MTK_PHY_V3, 1537}; 1538 1539static const struct of_device_id mtk_tphy_id_table[] = { 1540 { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata }, 1541 { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata }, 1542 { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata }, 1543 { .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata }, 1544 { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, 1545 { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, 1546 { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata }, 1547 { }, 1548}; 1549MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); 1550 1551static int mtk_tphy_probe(struct platform_device *pdev) 1552{ 1553 struct device *dev = &pdev->dev; 1554 struct device_node *np = dev->of_node; 1555 struct device_node *child_np; 1556 struct phy_provider *provider; 1557 struct resource *sif_res; 1558 struct mtk_tphy *tphy; 1559 struct resource res; 1560 int port, retval; 1561 1562 tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL); 1563 if (!tphy) 1564 return -ENOMEM; 1565 1566 tphy->pdata = of_device_get_match_data(dev); 1567 if (!tphy->pdata) 1568 return -EINVAL; 1569 1570 tphy->nphys = of_get_child_count(np); 1571 tphy->phys = devm_kcalloc(dev, tphy->nphys, 1572 sizeof(*tphy->phys), GFP_KERNEL); 1573 if (!tphy->phys) 1574 return -ENOMEM; 1575 1576 tphy->dev = dev; 1577 platform_set_drvdata(pdev, tphy); 1578 1579 sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1580 /* SATA phy of V1 needn't it if not shared with PCIe or USB */ 1581 if (sif_res && tphy->pdata->version == MTK_PHY_V1) { 1582 /* get banks shared by multiple phys */ 1583 tphy->sif_base = devm_ioremap_resource(dev, sif_res); 1584 if (IS_ERR(tphy->sif_base)) { 1585 dev_err(dev, "failed to remap sif regs\n"); 1586 return PTR_ERR(tphy->sif_base); 1587 } 1588 } 1589 1590 if (tphy->pdata->version < MTK_PHY_V3) { 1591 tphy->src_ref_clk = U3P_REF_CLK; 1592 tphy->src_coef = U3P_SLEW_RATE_COEF; 1593 /* update parameters of slew rate calibrate if exist */ 1594 device_property_read_u32(dev, "mediatek,src-ref-clk-mhz", 1595 &tphy->src_ref_clk); 1596 device_property_read_u32(dev, "mediatek,src-coef", 1597 &tphy->src_coef); 1598 } 1599 1600 port = 0; 1601 for_each_child_of_node(np, child_np) { 1602 struct mtk_phy_instance *instance; 1603 struct clk_bulk_data *clks; 1604 struct device *subdev; 1605 struct phy *phy; 1606 1607 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL); 1608 if (!instance) { 1609 retval = -ENOMEM; 1610 goto put_child; 1611 } 1612 1613 tphy->phys[port] = instance; 1614 1615 phy = devm_phy_create(dev, child_np, &mtk_tphy_ops); 1616 if (IS_ERR(phy)) { 1617 dev_err(dev, "failed to create phy\n"); 1618 retval = PTR_ERR(phy); 1619 goto put_child; 1620 } 1621 1622 subdev = &phy->dev; 1623 retval = of_address_to_resource(child_np, 0, &res); 1624 if (retval) { 1625 dev_err(subdev, "failed to get address resource(id-%d)\n", 1626 port); 1627 goto put_child; 1628 } 1629 1630 instance->port_base = devm_ioremap_resource(subdev, &res); 1631 if (IS_ERR(instance->port_base)) { 1632 retval = PTR_ERR(instance->port_base); 1633 goto put_child; 1634 } 1635 1636 instance->phy = phy; 1637 instance->index = port; 1638 phy_set_drvdata(phy, instance); 1639 port++; 1640 1641 clks = instance->clks; 1642 clks[0].id = "ref"; /* digital (& analog) clock */ 1643 clks[1].id = "da_ref"; /* analog clock */ 1644 retval = devm_clk_bulk_get_optional(subdev, TPHY_CLKS_CNT, clks); 1645 if (retval) 1646 goto put_child; 1647 1648 retval = phy_type_syscon_get(instance, child_np); 1649 if (retval) 1650 goto put_child; 1651 } 1652 1653 provider = devm_of_phy_provider_register(dev, mtk_phy_xlate); 1654 1655 return PTR_ERR_OR_ZERO(provider); 1656put_child: 1657 of_node_put(child_np); 1658 return retval; 1659} 1660 1661static struct platform_driver mtk_tphy_driver = { 1662 .probe = mtk_tphy_probe, 1663 .driver = { 1664 .name = "mtk-tphy", 1665 .of_match_table = mtk_tphy_id_table, 1666 }, 1667}; 1668 1669module_platform_driver(mtk_tphy_driver); 1670 1671MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 1672MODULE_DESCRIPTION("MediaTek T-PHY driver"); 1673MODULE_LICENSE("GPL v2"); 1674