1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * ARMv8 PMUv3 Performance Events handling code. 4 * 5 * Copyright (C) 2012 ARM Limited 6 * Author: Will Deacon <will.deacon@arm.com> 7 * 8 * This code is based heavily on the ARMv7 perf event code. 9 */ 10 11#include <asm/irq_regs.h> 12#include <asm/perf_event.h> 13#include <asm/virt.h> 14 15#include <clocksource/arm_arch_timer.h> 16 17#include <linux/acpi.h> 18#include <linux/clocksource.h> 19#include <linux/of.h> 20#include <linux/perf/arm_pmu.h> 21#include <linux/perf/arm_pmuv3.h> 22#include <linux/platform_device.h> 23#include <linux/sched_clock.h> 24#include <linux/smp.h> 25#include <linux/nmi.h> 26 27#include <asm/arm_pmuv3.h> 28 29/* ARMv8 Cortex-A53 specific event types. */ 30#define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2 31 32/* ARMv8 Cavium ThunderX specific event types. */ 33#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST 0xE9 34#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS 0xEA 35#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS 0xEB 36#define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS 0xEC 37#define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS 0xED 38 39/* 40 * ARMv8 Architectural defined events, not all of these may 41 * be supported on any given implementation. Unsupported events will 42 * be disabled at run-time based on the PMCEID registers. 43 */ 44static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = { 45 PERF_MAP_ALL_UNSUPPORTED, 46 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES, 47 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED, 48 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, 49 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, 50 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, 51 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES, 52 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND, 53 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND, 54}; 55 56static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 57 [PERF_COUNT_HW_CACHE_OP_MAX] 58 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 59 PERF_CACHE_MAP_ALL_UNSUPPORTED, 60 61 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, 62 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, 63 64 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE, 65 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL, 66 67 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL, 68 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB, 69 70 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL, 71 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB, 72 73 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD, 74 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD, 75 76 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED, 77 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, 78}; 79 80static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 81 [PERF_COUNT_HW_CACHE_OP_MAX] 82 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 83 PERF_CACHE_MAP_ALL_UNSUPPORTED, 84 85 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL, 86 87 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, 88 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, 89}; 90 91static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 92 [PERF_COUNT_HW_CACHE_OP_MAX] 93 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 94 PERF_CACHE_MAP_ALL_UNSUPPORTED, 95 96 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 97 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, 98 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 99 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR, 100 101 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, 102 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, 103 104 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, 105 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, 106}; 107 108static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 109 [PERF_COUNT_HW_CACHE_OP_MAX] 110 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 111 PERF_CACHE_MAP_ALL_UNSUPPORTED, 112 113 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 114 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 115}; 116 117static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 118 [PERF_COUNT_HW_CACHE_OP_MAX] 119 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 120 PERF_CACHE_MAP_ALL_UNSUPPORTED, 121 122 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 123 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, 124 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 125 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST, 126 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS, 127 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS, 128 129 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS, 130 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS, 131 132 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD, 133 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, 134 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR, 135 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, 136}; 137 138static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 139 [PERF_COUNT_HW_CACHE_OP_MAX] 140 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 141 PERF_CACHE_MAP_ALL_UNSUPPORTED, 142 143 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 144 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, 145 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 146 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR, 147 148 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD, 149 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR, 150 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, 151 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, 152 153 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, 154 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, 155}; 156 157static ssize_t 158armv8pmu_events_sysfs_show(struct device *dev, 159 struct device_attribute *attr, char *page) 160{ 161 struct perf_pmu_events_attr *pmu_attr; 162 163 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 164 165 return sprintf(page, "event=0x%04llx\n", pmu_attr->id); 166} 167 168#define ARMV8_EVENT_ATTR(name, config) \ 169 PMU_EVENT_ATTR_ID(name, armv8pmu_events_sysfs_show, config) 170 171static struct attribute *armv8_pmuv3_event_attrs[] = { 172 /* 173 * Don't expose the sw_incr event in /sys. It's not usable as writes to 174 * PMSWINC_EL0 will trap as PMUSERENR.{SW,EN}=={0,0} and event rotation 175 * means we don't have a fixed event<->counter relationship regardless. 176 */ 177 ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL), 178 ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL), 179 ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL), 180 ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE), 181 ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL), 182 ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED), 183 ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED), 184 ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED), 185 ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN), 186 ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN), 187 ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED), 188 ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED), 189 ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED), 190 ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED), 191 ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED), 192 ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED), 193 ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES), 194 ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED), 195 ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS), 196 ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE), 197 ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB), 198 ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE), 199 ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL), 200 ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB), 201 ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS), 202 ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR), 203 ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC), 204 ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED), 205 ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES), 206 /* Don't expose the chain event in /sys, since it's useless in isolation */ 207 ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE), 208 ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE), 209 ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED), 210 ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED), 211 ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND), 212 ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND), 213 ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB), 214 ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB), 215 ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE), 216 ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL), 217 ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE), 218 ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL), 219 ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE), 220 ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB), 221 ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL), 222 ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL), 223 ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB), 224 ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB), 225 ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS), 226 ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE), 227 ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS), 228 ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK), 229 ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK), 230 ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD), 231 ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD), 232 ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD), 233 ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD), 234 ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED), 235 ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC), 236 ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL), 237 ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND), 238 ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND), 239 ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT), 240 ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP), 241 ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED), 242 ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE), 243 ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION), 244 ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES), 245 ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM), 246 ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS), 247 ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD), 248 ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS), 249 ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD), 250 ARMV8_EVENT_ATTR(trb_wrap, ARMV8_PMUV3_PERFCTR_TRB_WRAP), 251 ARMV8_EVENT_ATTR(trb_trig, ARMV8_PMUV3_PERFCTR_TRB_TRIG), 252 ARMV8_EVENT_ATTR(trcextout0, ARMV8_PMUV3_PERFCTR_TRCEXTOUT0), 253 ARMV8_EVENT_ATTR(trcextout1, ARMV8_PMUV3_PERFCTR_TRCEXTOUT1), 254 ARMV8_EVENT_ATTR(trcextout2, ARMV8_PMUV3_PERFCTR_TRCEXTOUT2), 255 ARMV8_EVENT_ATTR(trcextout3, ARMV8_PMUV3_PERFCTR_TRCEXTOUT3), 256 ARMV8_EVENT_ATTR(cti_trigout4, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4), 257 ARMV8_EVENT_ATTR(cti_trigout5, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5), 258 ARMV8_EVENT_ATTR(cti_trigout6, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6), 259 ARMV8_EVENT_ATTR(cti_trigout7, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7), 260 ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT), 261 ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT), 262 ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT), 263 ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED), 264 ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD), 265 ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR), 266 NULL, 267}; 268 269static umode_t 270armv8pmu_event_attr_is_visible(struct kobject *kobj, 271 struct attribute *attr, int unused) 272{ 273 struct device *dev = kobj_to_dev(kobj); 274 struct pmu *pmu = dev_get_drvdata(dev); 275 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 276 struct perf_pmu_events_attr *pmu_attr; 277 278 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr); 279 280 if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS && 281 test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap)) 282 return attr->mode; 283 284 if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) { 285 u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE; 286 287 if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS && 288 test_bit(id, cpu_pmu->pmceid_ext_bitmap)) 289 return attr->mode; 290 } 291 292 return 0; 293} 294 295static const struct attribute_group armv8_pmuv3_events_attr_group = { 296 .name = "events", 297 .attrs = armv8_pmuv3_event_attrs, 298 .is_visible = armv8pmu_event_attr_is_visible, 299}; 300 301PMU_FORMAT_ATTR(event, "config:0-15"); 302PMU_FORMAT_ATTR(long, "config1:0"); 303PMU_FORMAT_ATTR(rdpmc, "config1:1"); 304 305static int sysctl_perf_user_access __read_mostly; 306 307static inline bool armv8pmu_event_is_64bit(struct perf_event *event) 308{ 309 return event->attr.config1 & 0x1; 310} 311 312static inline bool armv8pmu_event_want_user_access(struct perf_event *event) 313{ 314 return event->attr.config1 & 0x2; 315} 316 317static struct attribute *armv8_pmuv3_format_attrs[] = { 318 &format_attr_event.attr, 319 &format_attr_long.attr, 320 &format_attr_rdpmc.attr, 321 NULL, 322}; 323 324static const struct attribute_group armv8_pmuv3_format_attr_group = { 325 .name = "format", 326 .attrs = armv8_pmuv3_format_attrs, 327}; 328 329static ssize_t slots_show(struct device *dev, struct device_attribute *attr, 330 char *page) 331{ 332 struct pmu *pmu = dev_get_drvdata(dev); 333 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 334 u32 slots = cpu_pmu->reg_pmmir & ARMV8_PMU_SLOTS_MASK; 335 336 return sysfs_emit(page, "0x%08x\n", slots); 337} 338 339static DEVICE_ATTR_RO(slots); 340 341static ssize_t bus_slots_show(struct device *dev, struct device_attribute *attr, 342 char *page) 343{ 344 struct pmu *pmu = dev_get_drvdata(dev); 345 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 346 u32 bus_slots = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_SLOTS_SHIFT) 347 & ARMV8_PMU_BUS_SLOTS_MASK; 348 349 return sysfs_emit(page, "0x%08x\n", bus_slots); 350} 351 352static DEVICE_ATTR_RO(bus_slots); 353 354static ssize_t bus_width_show(struct device *dev, struct device_attribute *attr, 355 char *page) 356{ 357 struct pmu *pmu = dev_get_drvdata(dev); 358 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 359 u32 bus_width = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_WIDTH_SHIFT) 360 & ARMV8_PMU_BUS_WIDTH_MASK; 361 u32 val = 0; 362 363 /* Encoded as Log2(number of bytes), plus one */ 364 if (bus_width > 2 && bus_width < 13) 365 val = 1 << (bus_width - 1); 366 367 return sysfs_emit(page, "0x%08x\n", val); 368} 369 370static DEVICE_ATTR_RO(bus_width); 371 372static struct attribute *armv8_pmuv3_caps_attrs[] = { 373 &dev_attr_slots.attr, 374 &dev_attr_bus_slots.attr, 375 &dev_attr_bus_width.attr, 376 NULL, 377}; 378 379static const struct attribute_group armv8_pmuv3_caps_attr_group = { 380 .name = "caps", 381 .attrs = armv8_pmuv3_caps_attrs, 382}; 383 384/* 385 * Perf Events' indices 386 */ 387#define ARMV8_IDX_CYCLE_COUNTER 0 388#define ARMV8_IDX_COUNTER0 1 389#define ARMV8_IDX_CYCLE_COUNTER_USER 32 390 391/* 392 * We unconditionally enable ARMv8.5-PMU long event counter support 393 * (64-bit events) where supported. Indicate if this arm_pmu has long 394 * event counter support. 395 * 396 * On AArch32, long counters make no sense (you can't access the top 397 * bits), so we only enable this on AArch64. 398 */ 399static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu) 400{ 401 return (IS_ENABLED(CONFIG_ARM64) && is_pmuv3p5(cpu_pmu->pmuver)); 402} 403 404static inline bool armv8pmu_event_has_user_read(struct perf_event *event) 405{ 406 return event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT; 407} 408 409/* 410 * We must chain two programmable counters for 64 bit events, 411 * except when we have allocated the 64bit cycle counter (for CPU 412 * cycles event) or when user space counter access is enabled. 413 */ 414static inline bool armv8pmu_event_is_chained(struct perf_event *event) 415{ 416 int idx = event->hw.idx; 417 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 418 419 return !armv8pmu_event_has_user_read(event) && 420 armv8pmu_event_is_64bit(event) && 421 !armv8pmu_has_long_event(cpu_pmu) && 422 (idx != ARMV8_IDX_CYCLE_COUNTER); 423} 424 425/* 426 * ARMv8 low level PMU access 427 */ 428 429/* 430 * Perf Event to low level counters mapping 431 */ 432#define ARMV8_IDX_TO_COUNTER(x) \ 433 (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK) 434 435static inline u64 armv8pmu_pmcr_read(void) 436{ 437 return read_pmcr(); 438} 439 440static inline void armv8pmu_pmcr_write(u64 val) 441{ 442 val &= ARMV8_PMU_PMCR_MASK; 443 isb(); 444 write_pmcr(val); 445} 446 447static inline int armv8pmu_has_overflowed(u32 pmovsr) 448{ 449 return pmovsr & ARMV8_PMU_OVERFLOWED_MASK; 450} 451 452static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx) 453{ 454 return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx)); 455} 456 457static inline u64 armv8pmu_read_evcntr(int idx) 458{ 459 u32 counter = ARMV8_IDX_TO_COUNTER(idx); 460 461 return read_pmevcntrn(counter); 462} 463 464static inline u64 armv8pmu_read_hw_counter(struct perf_event *event) 465{ 466 int idx = event->hw.idx; 467 u64 val = armv8pmu_read_evcntr(idx); 468 469 if (armv8pmu_event_is_chained(event)) 470 val = (val << 32) | armv8pmu_read_evcntr(idx - 1); 471 return val; 472} 473 474/* 475 * The cycle counter is always a 64-bit counter. When ARMV8_PMU_PMCR_LP 476 * is set the event counters also become 64-bit counters. Unless the 477 * user has requested a long counter (attr.config1) then we want to 478 * interrupt upon 32-bit overflow - we achieve this by applying a bias. 479 */ 480static bool armv8pmu_event_needs_bias(struct perf_event *event) 481{ 482 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 483 struct hw_perf_event *hwc = &event->hw; 484 int idx = hwc->idx; 485 486 if (armv8pmu_event_is_64bit(event)) 487 return false; 488 489 if (armv8pmu_has_long_event(cpu_pmu) || 490 idx == ARMV8_IDX_CYCLE_COUNTER) 491 return true; 492 493 return false; 494} 495 496static u64 armv8pmu_bias_long_counter(struct perf_event *event, u64 value) 497{ 498 if (armv8pmu_event_needs_bias(event)) 499 value |= GENMASK_ULL(63, 32); 500 501 return value; 502} 503 504static u64 armv8pmu_unbias_long_counter(struct perf_event *event, u64 value) 505{ 506 if (armv8pmu_event_needs_bias(event)) 507 value &= ~GENMASK_ULL(63, 32); 508 509 return value; 510} 511 512static u64 armv8pmu_read_counter(struct perf_event *event) 513{ 514 struct hw_perf_event *hwc = &event->hw; 515 int idx = hwc->idx; 516 u64 value; 517 518 if (idx == ARMV8_IDX_CYCLE_COUNTER) 519 value = read_pmccntr(); 520 else 521 value = armv8pmu_read_hw_counter(event); 522 523 return armv8pmu_unbias_long_counter(event, value); 524} 525 526static inline void armv8pmu_write_evcntr(int idx, u64 value) 527{ 528 u32 counter = ARMV8_IDX_TO_COUNTER(idx); 529 530 write_pmevcntrn(counter, value); 531} 532 533static inline void armv8pmu_write_hw_counter(struct perf_event *event, 534 u64 value) 535{ 536 int idx = event->hw.idx; 537 538 if (armv8pmu_event_is_chained(event)) { 539 armv8pmu_write_evcntr(idx, upper_32_bits(value)); 540 armv8pmu_write_evcntr(idx - 1, lower_32_bits(value)); 541 } else { 542 armv8pmu_write_evcntr(idx, value); 543 } 544} 545 546static void armv8pmu_write_counter(struct perf_event *event, u64 value) 547{ 548 struct hw_perf_event *hwc = &event->hw; 549 int idx = hwc->idx; 550 551 value = armv8pmu_bias_long_counter(event, value); 552 553 if (idx == ARMV8_IDX_CYCLE_COUNTER) 554 write_pmccntr(value); 555 else 556 armv8pmu_write_hw_counter(event, value); 557} 558 559static inline void armv8pmu_write_evtype(int idx, u32 val) 560{ 561 u32 counter = ARMV8_IDX_TO_COUNTER(idx); 562 563 val &= ARMV8_PMU_EVTYPE_MASK; 564 write_pmevtypern(counter, val); 565} 566 567static inline void armv8pmu_write_event_type(struct perf_event *event) 568{ 569 struct hw_perf_event *hwc = &event->hw; 570 int idx = hwc->idx; 571 572 /* 573 * For chained events, the low counter is programmed to count 574 * the event of interest and the high counter is programmed 575 * with CHAIN event code with filters set to count at all ELs. 576 */ 577 if (armv8pmu_event_is_chained(event)) { 578 u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN | 579 ARMV8_PMU_INCLUDE_EL2; 580 581 armv8pmu_write_evtype(idx - 1, hwc->config_base); 582 armv8pmu_write_evtype(idx, chain_evt); 583 } else { 584 if (idx == ARMV8_IDX_CYCLE_COUNTER) 585 write_pmccfiltr(hwc->config_base); 586 else 587 armv8pmu_write_evtype(idx, hwc->config_base); 588 } 589} 590 591static u32 armv8pmu_event_cnten_mask(struct perf_event *event) 592{ 593 int counter = ARMV8_IDX_TO_COUNTER(event->hw.idx); 594 u32 mask = BIT(counter); 595 596 if (armv8pmu_event_is_chained(event)) 597 mask |= BIT(counter - 1); 598 return mask; 599} 600 601static inline void armv8pmu_enable_counter(u32 mask) 602{ 603 /* 604 * Make sure event configuration register writes are visible before we 605 * enable the counter. 606 * */ 607 isb(); 608 write_pmcntenset(mask); 609} 610 611static inline void armv8pmu_enable_event_counter(struct perf_event *event) 612{ 613 struct perf_event_attr *attr = &event->attr; 614 u32 mask = armv8pmu_event_cnten_mask(event); 615 616 kvm_set_pmu_events(mask, attr); 617 618 /* We rely on the hypervisor switch code to enable guest counters */ 619 if (!kvm_pmu_counter_deferred(attr)) 620 armv8pmu_enable_counter(mask); 621} 622 623static inline void armv8pmu_disable_counter(u32 mask) 624{ 625 write_pmcntenclr(mask); 626 /* 627 * Make sure the effects of disabling the counter are visible before we 628 * start configuring the event. 629 */ 630 isb(); 631} 632 633static inline void armv8pmu_disable_event_counter(struct perf_event *event) 634{ 635 struct perf_event_attr *attr = &event->attr; 636 u32 mask = armv8pmu_event_cnten_mask(event); 637 638 kvm_clr_pmu_events(mask); 639 640 /* We rely on the hypervisor switch code to disable guest counters */ 641 if (!kvm_pmu_counter_deferred(attr)) 642 armv8pmu_disable_counter(mask); 643} 644 645static inline void armv8pmu_enable_intens(u32 mask) 646{ 647 write_pmintenset(mask); 648} 649 650static inline void armv8pmu_enable_event_irq(struct perf_event *event) 651{ 652 u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx); 653 armv8pmu_enable_intens(BIT(counter)); 654} 655 656static inline void armv8pmu_disable_intens(u32 mask) 657{ 658 write_pmintenclr(mask); 659 isb(); 660 /* Clear the overflow flag in case an interrupt is pending. */ 661 write_pmovsclr(mask); 662 isb(); 663} 664 665static inline void armv8pmu_disable_event_irq(struct perf_event *event) 666{ 667 u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx); 668 armv8pmu_disable_intens(BIT(counter)); 669} 670 671static inline u32 armv8pmu_getreset_flags(void) 672{ 673 u32 value; 674 675 /* Read */ 676 value = read_pmovsclr(); 677 678 /* Write to clear flags */ 679 value &= ARMV8_PMU_OVSR_MASK; 680 write_pmovsclr(value); 681 682 return value; 683} 684 685static void update_pmuserenr(u64 val) 686{ 687 lockdep_assert_irqs_disabled(); 688 689 /* 690 * The current PMUSERENR_EL0 value might be the value for the guest. 691 * If that's the case, have KVM keep tracking of the register value 692 * for the host EL0 so that KVM can restore it before returning to 693 * the host EL0. Otherwise, update the register now. 694 */ 695 if (kvm_set_pmuserenr(val)) 696 return; 697 698 write_pmuserenr(val); 699} 700 701static void armv8pmu_disable_user_access(void) 702{ 703 update_pmuserenr(0); 704} 705 706static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu) 707{ 708 int i; 709 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); 710 711 /* Clear any unused counters to avoid leaking their contents */ 712 for_each_clear_bit(i, cpuc->used_mask, cpu_pmu->num_events) { 713 if (i == ARMV8_IDX_CYCLE_COUNTER) 714 write_pmccntr(0); 715 else 716 armv8pmu_write_evcntr(i, 0); 717 } 718 719 update_pmuserenr(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR); 720} 721 722static void armv8pmu_enable_event(struct perf_event *event) 723{ 724 /* 725 * Enable counter and interrupt, and set the counter to count 726 * the event that we're interested in. 727 */ 728 armv8pmu_disable_event_counter(event); 729 armv8pmu_write_event_type(event); 730 armv8pmu_enable_event_irq(event); 731 armv8pmu_enable_event_counter(event); 732} 733 734static void armv8pmu_disable_event(struct perf_event *event) 735{ 736 armv8pmu_disable_event_counter(event); 737 armv8pmu_disable_event_irq(event); 738} 739 740static void armv8pmu_start(struct arm_pmu *cpu_pmu) 741{ 742 struct perf_event_context *ctx; 743 int nr_user = 0; 744 745 ctx = perf_cpu_task_ctx(); 746 if (ctx) 747 nr_user = ctx->nr_user; 748 749 if (sysctl_perf_user_access && nr_user) 750 armv8pmu_enable_user_access(cpu_pmu); 751 else 752 armv8pmu_disable_user_access(); 753 754 /* Enable all counters */ 755 armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E); 756 757 kvm_vcpu_pmu_resync_el0(); 758} 759 760static void armv8pmu_stop(struct arm_pmu *cpu_pmu) 761{ 762 /* Disable all counters */ 763 armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E); 764} 765 766static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu) 767{ 768 u32 pmovsr; 769 struct perf_sample_data data; 770 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); 771 struct pt_regs *regs; 772 int idx; 773 774 /* 775 * Get and reset the IRQ flags 776 */ 777 pmovsr = armv8pmu_getreset_flags(); 778 779 /* 780 * Did an overflow occur? 781 */ 782 if (!armv8pmu_has_overflowed(pmovsr)) 783 return IRQ_NONE; 784 785 /* 786 * Handle the counter(s) overflow(s) 787 */ 788 regs = get_irq_regs(); 789 790 /* 791 * Stop the PMU while processing the counter overflows 792 * to prevent skews in group events. 793 */ 794 armv8pmu_stop(cpu_pmu); 795 for (idx = 0; idx < cpu_pmu->num_events; ++idx) { 796 struct perf_event *event = cpuc->events[idx]; 797 struct hw_perf_event *hwc; 798 799 /* Ignore if we don't have an event. */ 800 if (!event) 801 continue; 802 803 /* 804 * We have a single interrupt for all counters. Check that 805 * each counter has overflowed before we process it. 806 */ 807 if (!armv8pmu_counter_has_overflowed(pmovsr, idx)) 808 continue; 809 810 hwc = &event->hw; 811 armpmu_event_update(event); 812 perf_sample_data_init(&data, 0, hwc->last_period); 813 if (!armpmu_event_set_period(event)) 814 continue; 815 816 /* 817 * Perf event overflow will queue the processing of the event as 818 * an irq_work which will be taken care of in the handling of 819 * IPI_IRQ_WORK. 820 */ 821 if (perf_event_overflow(event, &data, regs)) 822 cpu_pmu->disable(event); 823 } 824 armv8pmu_start(cpu_pmu); 825 826 return IRQ_HANDLED; 827} 828 829static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc, 830 struct arm_pmu *cpu_pmu) 831{ 832 int idx; 833 834 for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; idx++) { 835 if (!test_and_set_bit(idx, cpuc->used_mask)) 836 return idx; 837 } 838 return -EAGAIN; 839} 840 841static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc, 842 struct arm_pmu *cpu_pmu) 843{ 844 int idx; 845 846 /* 847 * Chaining requires two consecutive event counters, where 848 * the lower idx must be even. 849 */ 850 for (idx = ARMV8_IDX_COUNTER0 + 1; idx < cpu_pmu->num_events; idx += 2) { 851 if (!test_and_set_bit(idx, cpuc->used_mask)) { 852 /* Check if the preceding even counter is available */ 853 if (!test_and_set_bit(idx - 1, cpuc->used_mask)) 854 return idx; 855 /* Release the Odd counter */ 856 clear_bit(idx, cpuc->used_mask); 857 } 858 } 859 return -EAGAIN; 860} 861 862static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, 863 struct perf_event *event) 864{ 865 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 866 struct hw_perf_event *hwc = &event->hw; 867 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT; 868 869 /* Always prefer to place a cycle counter into the cycle counter. */ 870 if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) { 871 if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask)) 872 return ARMV8_IDX_CYCLE_COUNTER; 873 else if (armv8pmu_event_is_64bit(event) && 874 armv8pmu_event_want_user_access(event) && 875 !armv8pmu_has_long_event(cpu_pmu)) 876 return -EAGAIN; 877 } 878 879 /* 880 * Otherwise use events counters 881 */ 882 if (armv8pmu_event_is_chained(event)) 883 return armv8pmu_get_chain_idx(cpuc, cpu_pmu); 884 else 885 return armv8pmu_get_single_idx(cpuc, cpu_pmu); 886} 887 888static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc, 889 struct perf_event *event) 890{ 891 int idx = event->hw.idx; 892 893 clear_bit(idx, cpuc->used_mask); 894 if (armv8pmu_event_is_chained(event)) 895 clear_bit(idx - 1, cpuc->used_mask); 896} 897 898static int armv8pmu_user_event_idx(struct perf_event *event) 899{ 900 if (!sysctl_perf_user_access || !armv8pmu_event_has_user_read(event)) 901 return 0; 902 903 /* 904 * We remap the cycle counter index to 32 to 905 * match the offset applied to the rest of 906 * the counter indices. 907 */ 908 if (event->hw.idx == ARMV8_IDX_CYCLE_COUNTER) 909 return ARMV8_IDX_CYCLE_COUNTER_USER; 910 911 return event->hw.idx; 912} 913 914/* 915 * Add an event filter to a given event. 916 */ 917static int armv8pmu_set_event_filter(struct hw_perf_event *event, 918 struct perf_event_attr *attr) 919{ 920 unsigned long config_base = 0; 921 922 if (attr->exclude_idle) 923 return -EPERM; 924 925 /* 926 * If we're running in hyp mode, then we *are* the hypervisor. 927 * Therefore we ignore exclude_hv in this configuration, since 928 * there's no hypervisor to sample anyway. This is consistent 929 * with other architectures (x86 and Power). 930 */ 931 if (is_kernel_in_hyp_mode()) { 932 if (!attr->exclude_kernel && !attr->exclude_host) 933 config_base |= ARMV8_PMU_INCLUDE_EL2; 934 if (attr->exclude_guest) 935 config_base |= ARMV8_PMU_EXCLUDE_EL1; 936 if (attr->exclude_host) 937 config_base |= ARMV8_PMU_EXCLUDE_EL0; 938 } else { 939 if (!attr->exclude_hv && !attr->exclude_host) 940 config_base |= ARMV8_PMU_INCLUDE_EL2; 941 } 942 943 /* 944 * Filter out !VHE kernels and guest kernels 945 */ 946 if (attr->exclude_kernel) 947 config_base |= ARMV8_PMU_EXCLUDE_EL1; 948 949 if (attr->exclude_user) 950 config_base |= ARMV8_PMU_EXCLUDE_EL0; 951 952 /* 953 * Install the filter into config_base as this is used to 954 * construct the event type. 955 */ 956 event->config_base = config_base; 957 958 return 0; 959} 960 961static void armv8pmu_reset(void *info) 962{ 963 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info; 964 u64 pmcr; 965 966 /* The counter and interrupt enable registers are unknown at reset. */ 967 armv8pmu_disable_counter(U32_MAX); 968 armv8pmu_disable_intens(U32_MAX); 969 970 /* Clear the counters we flip at guest entry/exit */ 971 kvm_clr_pmu_events(U32_MAX); 972 973 /* 974 * Initialize & Reset PMNC. Request overflow interrupt for 975 * 64 bit cycle counter but cheat in armv8pmu_write_counter(). 976 */ 977 pmcr = ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC; 978 979 /* Enable long event counter support where available */ 980 if (armv8pmu_has_long_event(cpu_pmu)) 981 pmcr |= ARMV8_PMU_PMCR_LP; 982 983 armv8pmu_pmcr_write(pmcr); 984} 985 986static int __armv8_pmuv3_map_event_id(struct arm_pmu *armpmu, 987 struct perf_event *event) 988{ 989 if (event->attr.type == PERF_TYPE_HARDWARE && 990 event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) { 991 992 if (test_bit(ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED, 993 armpmu->pmceid_bitmap)) 994 return ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED; 995 996 if (test_bit(ARMV8_PMUV3_PERFCTR_BR_RETIRED, 997 armpmu->pmceid_bitmap)) 998 return ARMV8_PMUV3_PERFCTR_BR_RETIRED; 999 1000 return HW_OP_UNSUPPORTED; 1001 } 1002 1003 return armpmu_map_event(event, &armv8_pmuv3_perf_map, 1004 &armv8_pmuv3_perf_cache_map, 1005 ARMV8_PMU_EVTYPE_EVENT); 1006} 1007 1008static int __armv8_pmuv3_map_event(struct perf_event *event, 1009 const unsigned (*extra_event_map) 1010 [PERF_COUNT_HW_MAX], 1011 const unsigned (*extra_cache_map) 1012 [PERF_COUNT_HW_CACHE_MAX] 1013 [PERF_COUNT_HW_CACHE_OP_MAX] 1014 [PERF_COUNT_HW_CACHE_RESULT_MAX]) 1015{ 1016 int hw_event_id; 1017 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); 1018 1019 hw_event_id = __armv8_pmuv3_map_event_id(armpmu, event); 1020 1021 /* 1022 * CHAIN events only work when paired with an adjacent counter, and it 1023 * never makes sense for a user to open one in isolation, as they'll be 1024 * rotated arbitrarily. 1025 */ 1026 if (hw_event_id == ARMV8_PMUV3_PERFCTR_CHAIN) 1027 return -EINVAL; 1028 1029 if (armv8pmu_event_is_64bit(event)) 1030 event->hw.flags |= ARMPMU_EVT_64BIT; 1031 1032 /* 1033 * User events must be allocated into a single counter, and so 1034 * must not be chained. 1035 * 1036 * Most 64-bit events require long counter support, but 64-bit 1037 * CPU_CYCLES events can be placed into the dedicated cycle 1038 * counter when this is free. 1039 */ 1040 if (armv8pmu_event_want_user_access(event)) { 1041 if (!(event->attach_state & PERF_ATTACH_TASK)) 1042 return -EINVAL; 1043 if (armv8pmu_event_is_64bit(event) && 1044 (hw_event_id != ARMV8_PMUV3_PERFCTR_CPU_CYCLES) && 1045 !armv8pmu_has_long_event(armpmu)) 1046 return -EOPNOTSUPP; 1047 1048 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT; 1049 } 1050 1051 /* Only expose micro/arch events supported by this PMU */ 1052 if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS) 1053 && test_bit(hw_event_id, armpmu->pmceid_bitmap)) { 1054 return hw_event_id; 1055 } 1056 1057 return armpmu_map_event(event, extra_event_map, extra_cache_map, 1058 ARMV8_PMU_EVTYPE_EVENT); 1059} 1060 1061static int armv8_pmuv3_map_event(struct perf_event *event) 1062{ 1063 return __armv8_pmuv3_map_event(event, NULL, NULL); 1064} 1065 1066static int armv8_a53_map_event(struct perf_event *event) 1067{ 1068 return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map); 1069} 1070 1071static int armv8_a57_map_event(struct perf_event *event) 1072{ 1073 return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map); 1074} 1075 1076static int armv8_a73_map_event(struct perf_event *event) 1077{ 1078 return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map); 1079} 1080 1081static int armv8_thunder_map_event(struct perf_event *event) 1082{ 1083 return __armv8_pmuv3_map_event(event, NULL, 1084 &armv8_thunder_perf_cache_map); 1085} 1086 1087static int armv8_vulcan_map_event(struct perf_event *event) 1088{ 1089 return __armv8_pmuv3_map_event(event, NULL, 1090 &armv8_vulcan_perf_cache_map); 1091} 1092 1093struct armv8pmu_probe_info { 1094 struct arm_pmu *pmu; 1095 bool present; 1096}; 1097 1098static void __armv8pmu_probe_pmu(void *info) 1099{ 1100 struct armv8pmu_probe_info *probe = info; 1101 struct arm_pmu *cpu_pmu = probe->pmu; 1102 u64 pmceid_raw[2]; 1103 u32 pmceid[2]; 1104 int pmuver; 1105 1106 pmuver = read_pmuver(); 1107 if (!pmuv3_implemented(pmuver)) 1108 return; 1109 1110 cpu_pmu->pmuver = pmuver; 1111 probe->present = true; 1112 1113 /* Read the nb of CNTx counters supported from PMNC */ 1114 cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT) 1115 & ARMV8_PMU_PMCR_N_MASK; 1116 1117 /* Add the CPU cycles counter */ 1118 cpu_pmu->num_events += 1; 1119 1120 pmceid[0] = pmceid_raw[0] = read_pmceid0(); 1121 pmceid[1] = pmceid_raw[1] = read_pmceid1(); 1122 1123 bitmap_from_arr32(cpu_pmu->pmceid_bitmap, 1124 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS); 1125 1126 pmceid[0] = pmceid_raw[0] >> 32; 1127 pmceid[1] = pmceid_raw[1] >> 32; 1128 1129 bitmap_from_arr32(cpu_pmu->pmceid_ext_bitmap, 1130 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS); 1131 1132 /* store PMMIR register for sysfs */ 1133 if (is_pmuv3p4(pmuver) && (pmceid_raw[1] & BIT(31))) 1134 cpu_pmu->reg_pmmir = read_pmmir(); 1135 else 1136 cpu_pmu->reg_pmmir = 0; 1137} 1138 1139static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu) 1140{ 1141 struct armv8pmu_probe_info probe = { 1142 .pmu = cpu_pmu, 1143 .present = false, 1144 }; 1145 int ret; 1146 1147 ret = smp_call_function_any(&cpu_pmu->supported_cpus, 1148 __armv8pmu_probe_pmu, 1149 &probe, 1); 1150 if (ret) 1151 return ret; 1152 1153 return probe.present ? 0 : -ENODEV; 1154} 1155 1156static void armv8pmu_disable_user_access_ipi(void *unused) 1157{ 1158 armv8pmu_disable_user_access(); 1159} 1160 1161static int armv8pmu_proc_user_access_handler(struct ctl_table *table, int write, 1162 void *buffer, size_t *lenp, loff_t *ppos) 1163{ 1164 int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); 1165 if (ret || !write || sysctl_perf_user_access) 1166 return ret; 1167 1168 on_each_cpu(armv8pmu_disable_user_access_ipi, NULL, 1); 1169 return 0; 1170} 1171 1172static struct ctl_table armv8_pmu_sysctl_table[] = { 1173 { 1174 .procname = "perf_user_access", 1175 .data = &sysctl_perf_user_access, 1176 .maxlen = sizeof(unsigned int), 1177 .mode = 0644, 1178 .proc_handler = armv8pmu_proc_user_access_handler, 1179 .extra1 = SYSCTL_ZERO, 1180 .extra2 = SYSCTL_ONE, 1181 }, 1182 { } 1183}; 1184 1185static void armv8_pmu_register_sysctl_table(void) 1186{ 1187 static u32 tbl_registered = 0; 1188 1189 if (!cmpxchg_relaxed(&tbl_registered, 0, 1)) 1190 register_sysctl("kernel", armv8_pmu_sysctl_table); 1191} 1192 1193static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, 1194 int (*map_event)(struct perf_event *event), 1195 const struct attribute_group *events, 1196 const struct attribute_group *format, 1197 const struct attribute_group *caps) 1198{ 1199 int ret = armv8pmu_probe_pmu(cpu_pmu); 1200 if (ret) 1201 return ret; 1202 1203 cpu_pmu->handle_irq = armv8pmu_handle_irq; 1204 cpu_pmu->enable = armv8pmu_enable_event; 1205 cpu_pmu->disable = armv8pmu_disable_event; 1206 cpu_pmu->read_counter = armv8pmu_read_counter; 1207 cpu_pmu->write_counter = armv8pmu_write_counter; 1208 cpu_pmu->get_event_idx = armv8pmu_get_event_idx; 1209 cpu_pmu->clear_event_idx = armv8pmu_clear_event_idx; 1210 cpu_pmu->start = armv8pmu_start; 1211 cpu_pmu->stop = armv8pmu_stop; 1212 cpu_pmu->reset = armv8pmu_reset; 1213 cpu_pmu->set_event_filter = armv8pmu_set_event_filter; 1214 1215 cpu_pmu->pmu.event_idx = armv8pmu_user_event_idx; 1216 1217 cpu_pmu->name = name; 1218 cpu_pmu->map_event = map_event; 1219 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ? 1220 events : &armv8_pmuv3_events_attr_group; 1221 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ? 1222 format : &armv8_pmuv3_format_attr_group; 1223 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ? 1224 caps : &armv8_pmuv3_caps_attr_group; 1225 1226 armv8_pmu_register_sysctl_table(); 1227 return 0; 1228} 1229 1230static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name, 1231 int (*map_event)(struct perf_event *event)) 1232{ 1233 return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL); 1234} 1235 1236#define PMUV3_INIT_SIMPLE(name) \ 1237static int name##_pmu_init(struct arm_pmu *cpu_pmu) \ 1238{ \ 1239 return armv8_pmu_init_nogroups(cpu_pmu, #name, armv8_pmuv3_map_event);\ 1240} 1241 1242PMUV3_INIT_SIMPLE(armv8_pmuv3) 1243 1244PMUV3_INIT_SIMPLE(armv8_cortex_a34) 1245PMUV3_INIT_SIMPLE(armv8_cortex_a55) 1246PMUV3_INIT_SIMPLE(armv8_cortex_a65) 1247PMUV3_INIT_SIMPLE(armv8_cortex_a75) 1248PMUV3_INIT_SIMPLE(armv8_cortex_a76) 1249PMUV3_INIT_SIMPLE(armv8_cortex_a77) 1250PMUV3_INIT_SIMPLE(armv8_cortex_a78) 1251PMUV3_INIT_SIMPLE(armv9_cortex_a510) 1252PMUV3_INIT_SIMPLE(armv9_cortex_a520) 1253PMUV3_INIT_SIMPLE(armv9_cortex_a710) 1254PMUV3_INIT_SIMPLE(armv9_cortex_a715) 1255PMUV3_INIT_SIMPLE(armv9_cortex_a720) 1256PMUV3_INIT_SIMPLE(armv8_cortex_x1) 1257PMUV3_INIT_SIMPLE(armv9_cortex_x2) 1258PMUV3_INIT_SIMPLE(armv9_cortex_x3) 1259PMUV3_INIT_SIMPLE(armv9_cortex_x4) 1260PMUV3_INIT_SIMPLE(armv8_neoverse_e1) 1261PMUV3_INIT_SIMPLE(armv8_neoverse_n1) 1262PMUV3_INIT_SIMPLE(armv9_neoverse_n2) 1263PMUV3_INIT_SIMPLE(armv8_neoverse_v1) 1264 1265PMUV3_INIT_SIMPLE(armv8_nvidia_carmel) 1266PMUV3_INIT_SIMPLE(armv8_nvidia_denver) 1267 1268static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu) 1269{ 1270 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a35", 1271 armv8_a53_map_event); 1272} 1273 1274static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu) 1275{ 1276 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a53", 1277 armv8_a53_map_event); 1278} 1279 1280static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu) 1281{ 1282 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57", 1283 armv8_a57_map_event); 1284} 1285 1286static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu) 1287{ 1288 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72", 1289 armv8_a57_map_event); 1290} 1291 1292static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu) 1293{ 1294 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a73", 1295 armv8_a73_map_event); 1296} 1297 1298static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu) 1299{ 1300 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder", 1301 armv8_thunder_map_event); 1302} 1303 1304static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu) 1305{ 1306 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_brcm_vulcan", 1307 armv8_vulcan_map_event); 1308} 1309 1310static const struct of_device_id armv8_pmu_of_device_ids[] = { 1311 {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_pmu_init}, 1312 {.compatible = "arm,cortex-a34-pmu", .data = armv8_cortex_a34_pmu_init}, 1313 {.compatible = "arm,cortex-a35-pmu", .data = armv8_a35_pmu_init}, 1314 {.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init}, 1315 {.compatible = "arm,cortex-a55-pmu", .data = armv8_cortex_a55_pmu_init}, 1316 {.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init}, 1317 {.compatible = "arm,cortex-a65-pmu", .data = armv8_cortex_a65_pmu_init}, 1318 {.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init}, 1319 {.compatible = "arm,cortex-a73-pmu", .data = armv8_a73_pmu_init}, 1320 {.compatible = "arm,cortex-a75-pmu", .data = armv8_cortex_a75_pmu_init}, 1321 {.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init}, 1322 {.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init}, 1323 {.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init}, 1324 {.compatible = "arm,cortex-a510-pmu", .data = armv9_cortex_a510_pmu_init}, 1325 {.compatible = "arm,cortex-a520-pmu", .data = armv9_cortex_a520_pmu_init}, 1326 {.compatible = "arm,cortex-a710-pmu", .data = armv9_cortex_a710_pmu_init}, 1327 {.compatible = "arm,cortex-a715-pmu", .data = armv9_cortex_a715_pmu_init}, 1328 {.compatible = "arm,cortex-a720-pmu", .data = armv9_cortex_a720_pmu_init}, 1329 {.compatible = "arm,cortex-x1-pmu", .data = armv8_cortex_x1_pmu_init}, 1330 {.compatible = "arm,cortex-x2-pmu", .data = armv9_cortex_x2_pmu_init}, 1331 {.compatible = "arm,cortex-x3-pmu", .data = armv9_cortex_x3_pmu_init}, 1332 {.compatible = "arm,cortex-x4-pmu", .data = armv9_cortex_x4_pmu_init}, 1333 {.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init}, 1334 {.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init}, 1335 {.compatible = "arm,neoverse-n2-pmu", .data = armv9_neoverse_n2_pmu_init}, 1336 {.compatible = "arm,neoverse-v1-pmu", .data = armv8_neoverse_v1_pmu_init}, 1337 {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init}, 1338 {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init}, 1339 {.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init}, 1340 {.compatible = "nvidia,denver-pmu", .data = armv8_nvidia_denver_pmu_init}, 1341 {}, 1342}; 1343 1344static int armv8_pmu_device_probe(struct platform_device *pdev) 1345{ 1346 return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL); 1347} 1348 1349static struct platform_driver armv8_pmu_driver = { 1350 .driver = { 1351 .name = ARMV8_PMU_PDEV_NAME, 1352 .of_match_table = armv8_pmu_of_device_ids, 1353 .suppress_bind_attrs = true, 1354 }, 1355 .probe = armv8_pmu_device_probe, 1356}; 1357 1358static int __init armv8_pmu_driver_init(void) 1359{ 1360 int ret; 1361 1362 if (acpi_disabled) 1363 ret = platform_driver_register(&armv8_pmu_driver); 1364 else 1365 ret = arm_pmu_acpi_probe(armv8_pmuv3_pmu_init); 1366 1367 if (!ret) 1368 lockup_detector_retry_init(); 1369 1370 return ret; 1371} 1372device_initcall(armv8_pmu_driver_init) 1373 1374void arch_perf_update_userpage(struct perf_event *event, 1375 struct perf_event_mmap_page *userpg, u64 now) 1376{ 1377 struct clock_read_data *rd; 1378 unsigned int seq; 1379 u64 ns; 1380 1381 userpg->cap_user_time = 0; 1382 userpg->cap_user_time_zero = 0; 1383 userpg->cap_user_time_short = 0; 1384 userpg->cap_user_rdpmc = armv8pmu_event_has_user_read(event); 1385 1386 if (userpg->cap_user_rdpmc) { 1387 if (event->hw.flags & ARMPMU_EVT_64BIT) 1388 userpg->pmc_width = 64; 1389 else 1390 userpg->pmc_width = 32; 1391 } 1392 1393 do { 1394 rd = sched_clock_read_begin(&seq); 1395 1396 if (rd->read_sched_clock != arch_timer_read_counter) 1397 return; 1398 1399 userpg->time_mult = rd->mult; 1400 userpg->time_shift = rd->shift; 1401 userpg->time_zero = rd->epoch_ns; 1402 userpg->time_cycles = rd->epoch_cyc; 1403 userpg->time_mask = rd->sched_clock_mask; 1404 1405 /* 1406 * Subtract the cycle base, such that software that 1407 * doesn't know about cap_user_time_short still 'works' 1408 * assuming no wraps. 1409 */ 1410 ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift); 1411 userpg->time_zero -= ns; 1412 1413 } while (sched_clock_read_retry(seq)); 1414 1415 userpg->time_offset = userpg->time_zero - now; 1416 1417 /* 1418 * time_shift is not expected to be greater than 31 due to 1419 * the original published conversion algorithm shifting a 1420 * 32-bit value (now specifies a 64-bit value) - refer 1421 * perf_event_mmap_page documentation in perf_event.h. 1422 */ 1423 if (userpg->time_shift == 32) { 1424 userpg->time_shift = 31; 1425 userpg->time_mult >>= 1; 1426 } 1427 1428 /* 1429 * Internal timekeeping for enabled/running/stopped times 1430 * is always computed with the sched_clock. 1431 */ 1432 userpg->cap_user_time = 1; 1433 userpg->cap_user_time_zero = 1; 1434 userpg->cap_user_time_short = 1; 1435} 1436