162306a36Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0-only 262306a36Sopenharmony_ci# 362306a36Sopenharmony_ci# Performance Monitor Drivers 462306a36Sopenharmony_ci# 562306a36Sopenharmony_ci 662306a36Sopenharmony_cimenu "Performance monitor support" 762306a36Sopenharmony_ci depends on PERF_EVENTS 862306a36Sopenharmony_ci 962306a36Sopenharmony_ciconfig ARM_CCI_PMU 1062306a36Sopenharmony_ci tristate "ARM CCI PMU driver" 1162306a36Sopenharmony_ci depends on (ARM && CPU_V7) || ARM64 1262306a36Sopenharmony_ci select ARM_CCI 1362306a36Sopenharmony_ci help 1462306a36Sopenharmony_ci Support for PMU events monitoring on the ARM CCI (Cache Coherent 1562306a36Sopenharmony_ci Interconnect) family of products. 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci If compiled as a module, it will be called arm-cci. 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ciconfig ARM_CCI400_PMU 2062306a36Sopenharmony_ci bool "support CCI-400" 2162306a36Sopenharmony_ci default y 2262306a36Sopenharmony_ci depends on ARM_CCI_PMU 2362306a36Sopenharmony_ci select ARM_CCI400_COMMON 2462306a36Sopenharmony_ci help 2562306a36Sopenharmony_ci CCI-400 provides 4 independent event counters counting events related 2662306a36Sopenharmony_ci to the connected slave/master interfaces, plus a cycle counter. 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ciconfig ARM_CCI5xx_PMU 2962306a36Sopenharmony_ci bool "support CCI-500/CCI-550" 3062306a36Sopenharmony_ci default y 3162306a36Sopenharmony_ci depends on ARM_CCI_PMU 3262306a36Sopenharmony_ci help 3362306a36Sopenharmony_ci CCI-500/CCI-550 both provide 8 independent event counters, which can 3462306a36Sopenharmony_ci count events pertaining to the slave/master interfaces as well as the 3562306a36Sopenharmony_ci internal events to the CCI. 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ciconfig ARM_CCN 3862306a36Sopenharmony_ci tristate "ARM CCN driver support" 3962306a36Sopenharmony_ci depends on ARM || ARM64 || COMPILE_TEST 4062306a36Sopenharmony_ci help 4162306a36Sopenharmony_ci PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 4262306a36Sopenharmony_ci interconnect. 4362306a36Sopenharmony_ci 4462306a36Sopenharmony_ciconfig ARM_CMN 4562306a36Sopenharmony_ci tristate "Arm CMN-600 PMU support" 4662306a36Sopenharmony_ci depends on ARM64 || COMPILE_TEST 4762306a36Sopenharmony_ci help 4862306a36Sopenharmony_ci Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh 4962306a36Sopenharmony_ci Network interconnect. 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_ciconfig ARM_PMU 5262306a36Sopenharmony_ci depends on ARM || ARM64 5362306a36Sopenharmony_ci bool "ARM PMU framework" 5462306a36Sopenharmony_ci default y 5562306a36Sopenharmony_ci help 5662306a36Sopenharmony_ci Say y if you want to use CPU performance monitors on ARM-based 5762306a36Sopenharmony_ci systems. 5862306a36Sopenharmony_ci 5962306a36Sopenharmony_ciconfig RISCV_PMU 6062306a36Sopenharmony_ci depends on RISCV 6162306a36Sopenharmony_ci bool "RISC-V PMU framework" 6262306a36Sopenharmony_ci default y 6362306a36Sopenharmony_ci help 6462306a36Sopenharmony_ci Say y if you want to use CPU performance monitors on RISCV-based 6562306a36Sopenharmony_ci systems. This provides the core PMU framework that abstracts common 6662306a36Sopenharmony_ci PMU functionalities in a core library so that different PMU drivers 6762306a36Sopenharmony_ci can reuse it. 6862306a36Sopenharmony_ci 6962306a36Sopenharmony_ciconfig RISCV_PMU_LEGACY 7062306a36Sopenharmony_ci depends on RISCV_PMU 7162306a36Sopenharmony_ci bool "RISC-V legacy PMU implementation" 7262306a36Sopenharmony_ci default y 7362306a36Sopenharmony_ci help 7462306a36Sopenharmony_ci Say y if you want to use the legacy CPU performance monitor 7562306a36Sopenharmony_ci implementation on RISC-V based systems. This only allows counting 7662306a36Sopenharmony_ci of cycle/instruction counter and doesn't support counter overflow, 7762306a36Sopenharmony_ci or programmable counters. It will be removed in future. 7862306a36Sopenharmony_ci 7962306a36Sopenharmony_ciconfig RISCV_PMU_SBI 8062306a36Sopenharmony_ci depends on RISCV_PMU && RISCV_SBI 8162306a36Sopenharmony_ci bool "RISC-V PMU based on SBI PMU extension" 8262306a36Sopenharmony_ci default y 8362306a36Sopenharmony_ci help 8462306a36Sopenharmony_ci Say y if you want to use the CPU performance monitor 8562306a36Sopenharmony_ci using SBI PMU extension on RISC-V based systems. This option provides 8662306a36Sopenharmony_ci full perf feature support i.e. counter overflow, privilege mode 8762306a36Sopenharmony_ci filtering, counter configuration. 8862306a36Sopenharmony_ci 8962306a36Sopenharmony_ciconfig ARM_PMU_ACPI 9062306a36Sopenharmony_ci depends on ARM_PMU && ACPI 9162306a36Sopenharmony_ci def_bool y 9262306a36Sopenharmony_ci 9362306a36Sopenharmony_ciconfig ARM_SMMU_V3_PMU 9462306a36Sopenharmony_ci tristate "ARM SMMUv3 Performance Monitors Extension" 9562306a36Sopenharmony_ci depends on ARM64 || (COMPILE_TEST && 64BIT) 9662306a36Sopenharmony_ci depends on GENERIC_MSI_IRQ 9762306a36Sopenharmony_ci help 9862306a36Sopenharmony_ci Provides support for the ARM SMMUv3 Performance Monitor Counter 9962306a36Sopenharmony_ci Groups (PMCG), which provide monitoring of transactions passing 10062306a36Sopenharmony_ci through the SMMU and allow the resulting information to be filtered 10162306a36Sopenharmony_ci based on the Stream ID of the corresponding master. 10262306a36Sopenharmony_ci 10362306a36Sopenharmony_ciconfig ARM_PMUV3 10462306a36Sopenharmony_ci depends on HW_PERF_EVENTS && ((ARM && CPU_V7) || ARM64) 10562306a36Sopenharmony_ci bool "ARM PMUv3 support" if !ARM64 10662306a36Sopenharmony_ci default ARM64 10762306a36Sopenharmony_ci help 10862306a36Sopenharmony_ci Say y if you want to use the ARM performance monitor unit (PMU) 10962306a36Sopenharmony_ci version 3. The PMUv3 is the CPU performance monitors on ARMv8 11062306a36Sopenharmony_ci (aarch32 and aarch64) systems that implement the PMUv3 11162306a36Sopenharmony_ci architecture. 11262306a36Sopenharmony_ci 11362306a36Sopenharmony_ciconfig ARM_DSU_PMU 11462306a36Sopenharmony_ci tristate "ARM DynamIQ Shared Unit (DSU) PMU" 11562306a36Sopenharmony_ci depends on ARM64 11662306a36Sopenharmony_ci help 11762306a36Sopenharmony_ci Provides support for performance monitor unit in ARM DynamIQ Shared 11862306a36Sopenharmony_ci Unit (DSU). The DSU integrates one or more cores with an L3 memory 11962306a36Sopenharmony_ci system, control logic. The PMU allows counting various events related 12062306a36Sopenharmony_ci to DSU. 12162306a36Sopenharmony_ci 12262306a36Sopenharmony_ciconfig FSL_IMX8_DDR_PMU 12362306a36Sopenharmony_ci tristate "Freescale i.MX8 DDR perf monitor" 12462306a36Sopenharmony_ci depends on ARCH_MXC || COMPILE_TEST 12562306a36Sopenharmony_ci help 12662306a36Sopenharmony_ci Provides support for the DDR performance monitor in i.MX8, which 12762306a36Sopenharmony_ci can give information about memory throughput and other related 12862306a36Sopenharmony_ci events. 12962306a36Sopenharmony_ci 13062306a36Sopenharmony_ciconfig FSL_IMX9_DDR_PMU 13162306a36Sopenharmony_ci tristate "Freescale i.MX9 DDR perf monitor" 13262306a36Sopenharmony_ci depends on ARCH_MXC 13362306a36Sopenharmony_ci help 13462306a36Sopenharmony_ci Provides support for the DDR performance monitor in i.MX9, which 13562306a36Sopenharmony_ci can give information about memory throughput and other related 13662306a36Sopenharmony_ci events. 13762306a36Sopenharmony_ci 13862306a36Sopenharmony_ciconfig QCOM_L2_PMU 13962306a36Sopenharmony_ci bool "Qualcomm Technologies L2-cache PMU" 14062306a36Sopenharmony_ci depends on ARCH_QCOM && ARM64 && ACPI 14162306a36Sopenharmony_ci select QCOM_KRYO_L2_ACCESSORS 14262306a36Sopenharmony_ci help 14362306a36Sopenharmony_ci Provides support for the L2 cache performance monitor unit (PMU) 14462306a36Sopenharmony_ci in Qualcomm Technologies processors. 14562306a36Sopenharmony_ci Adds the L2 cache PMU into the perf events subsystem for 14662306a36Sopenharmony_ci monitoring L2 cache events. 14762306a36Sopenharmony_ci 14862306a36Sopenharmony_ciconfig QCOM_L3_PMU 14962306a36Sopenharmony_ci bool "Qualcomm Technologies L3-cache PMU" 15062306a36Sopenharmony_ci depends on ARCH_QCOM && ARM64 && ACPI 15162306a36Sopenharmony_ci select QCOM_IRQ_COMBINER 15262306a36Sopenharmony_ci help 15362306a36Sopenharmony_ci Provides support for the L3 cache performance monitor unit (PMU) 15462306a36Sopenharmony_ci in Qualcomm Technologies processors. 15562306a36Sopenharmony_ci Adds the L3 cache PMU into the perf events subsystem for 15662306a36Sopenharmony_ci monitoring L3 cache events. 15762306a36Sopenharmony_ci 15862306a36Sopenharmony_ciconfig THUNDERX2_PMU 15962306a36Sopenharmony_ci tristate "Cavium ThunderX2 SoC PMU UNCORE" 16062306a36Sopenharmony_ci depends on ARCH_THUNDER2 || COMPILE_TEST 16162306a36Sopenharmony_ci depends on NUMA && ACPI 16262306a36Sopenharmony_ci default m 16362306a36Sopenharmony_ci help 16462306a36Sopenharmony_ci Provides support for ThunderX2 UNCORE events. 16562306a36Sopenharmony_ci The SoC has PMU support in its L3 cache controller (L3C) and 16662306a36Sopenharmony_ci in the DDR4 Memory Controller (DMC). 16762306a36Sopenharmony_ci 16862306a36Sopenharmony_ciconfig XGENE_PMU 16962306a36Sopenharmony_ci depends on ARCH_XGENE || (COMPILE_TEST && 64BIT) 17062306a36Sopenharmony_ci bool "APM X-Gene SoC PMU" 17162306a36Sopenharmony_ci default n 17262306a36Sopenharmony_ci help 17362306a36Sopenharmony_ci Say y if you want to use APM X-Gene SoC performance monitors. 17462306a36Sopenharmony_ci 17562306a36Sopenharmony_ciconfig ARM_SPE_PMU 17662306a36Sopenharmony_ci tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 17762306a36Sopenharmony_ci depends on ARM64 17862306a36Sopenharmony_ci help 17962306a36Sopenharmony_ci Enable perf support for the ARMv8.2 Statistical Profiling 18062306a36Sopenharmony_ci Extension, which provides periodic sampling of operations in 18162306a36Sopenharmony_ci the CPU pipeline and reports this via the perf AUX interface. 18262306a36Sopenharmony_ci 18362306a36Sopenharmony_ciconfig ARM_DMC620_PMU 18462306a36Sopenharmony_ci tristate "Enable PMU support for the ARM DMC-620 memory controller" 18562306a36Sopenharmony_ci depends on (ARM64 && ACPI) || COMPILE_TEST 18662306a36Sopenharmony_ci help 18762306a36Sopenharmony_ci Support for PMU events monitoring on the ARM DMC-620 memory 18862306a36Sopenharmony_ci controller. 18962306a36Sopenharmony_ci 19062306a36Sopenharmony_ciconfig MARVELL_CN10K_TAD_PMU 19162306a36Sopenharmony_ci tristate "Marvell CN10K LLC-TAD PMU" 19262306a36Sopenharmony_ci depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT) 19362306a36Sopenharmony_ci help 19462306a36Sopenharmony_ci Provides support for Last-Level cache Tag-and-data Units (LLC-TAD) 19562306a36Sopenharmony_ci performance monitors on CN10K family silicons. 19662306a36Sopenharmony_ci 19762306a36Sopenharmony_ciconfig APPLE_M1_CPU_PMU 19862306a36Sopenharmony_ci bool "Apple M1 CPU PMU support" 19962306a36Sopenharmony_ci depends on ARM_PMU && ARCH_APPLE 20062306a36Sopenharmony_ci help 20162306a36Sopenharmony_ci Provides support for the non-architectural CPU PMUs present on 20262306a36Sopenharmony_ci the Apple M1 SoCs and derivatives. 20362306a36Sopenharmony_ci 20462306a36Sopenharmony_ciconfig ALIBABA_UNCORE_DRW_PMU 20562306a36Sopenharmony_ci tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver" 20662306a36Sopenharmony_ci depends on (ARM64 && ACPI) || COMPILE_TEST 20762306a36Sopenharmony_ci help 20862306a36Sopenharmony_ci Support for Driveway PMU events monitoring on Yitian 710 DDR 20962306a36Sopenharmony_ci Sub-system. 21062306a36Sopenharmony_ci 21162306a36Sopenharmony_cisource "drivers/perf/hisilicon/Kconfig" 21262306a36Sopenharmony_ci 21362306a36Sopenharmony_ciconfig MARVELL_CN10K_DDR_PMU 21462306a36Sopenharmony_ci tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support" 21562306a36Sopenharmony_ci depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT) 21662306a36Sopenharmony_ci help 21762306a36Sopenharmony_ci Enable perf support for Marvell DDR Performance monitoring 21862306a36Sopenharmony_ci event on CN10K platform. 21962306a36Sopenharmony_ci 22062306a36Sopenharmony_cisource "drivers/perf/arm_cspmu/Kconfig" 22162306a36Sopenharmony_ci 22262306a36Sopenharmony_cisource "drivers/perf/amlogic/Kconfig" 22362306a36Sopenharmony_ci 22462306a36Sopenharmony_ciconfig CXL_PMU 22562306a36Sopenharmony_ci tristate "CXL Performance Monitoring Unit" 22662306a36Sopenharmony_ci depends on CXL_BUS 22762306a36Sopenharmony_ci help 22862306a36Sopenharmony_ci Support performance monitoring as defined in CXL rev 3.0 22962306a36Sopenharmony_ci section 13.2: Performance Monitoring. CXL components may have 23062306a36Sopenharmony_ci one or more CXL Performance Monitoring Units (CPMUs). 23162306a36Sopenharmony_ci 23262306a36Sopenharmony_ci Say 'y/m' to enable a driver that will attach to performance 23362306a36Sopenharmony_ci monitoring units and provide standard perf based interfaces. 23462306a36Sopenharmony_ci 23562306a36Sopenharmony_ci If unsure say 'm'. 23662306a36Sopenharmony_ci 23762306a36Sopenharmony_ciendmenu 238