1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Support routines for initializing a PCI subsystem 4 * 5 * Extruded from code written by 6 * Dave Rusling (david.rusling@reo.mts.dec.com) 7 * David Mosberger (davidm@cs.arizona.edu) 8 * David Miller (davem@redhat.com) 9 * 10 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 11 * PCI-PCI bridges cleanup, sorted resource allocation. 12 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 13 * Converted to allocation in 3 passes, which gives 14 * tighter packing. Prefetchable range support. 15 */ 16 17#include <linux/init.h> 18#include <linux/kernel.h> 19#include <linux/module.h> 20#include <linux/pci.h> 21#include <linux/errno.h> 22#include <linux/ioport.h> 23#include <linux/cache.h> 24#include <linux/slab.h> 25#include <linux/acpi.h> 26#include "pci.h" 27 28unsigned int pci_flags; 29EXPORT_SYMBOL_GPL(pci_flags); 30 31struct pci_dev_resource { 32 struct list_head list; 33 struct resource *res; 34 struct pci_dev *dev; 35 resource_size_t start; 36 resource_size_t end; 37 resource_size_t add_size; 38 resource_size_t min_align; 39 unsigned long flags; 40}; 41 42static void free_list(struct list_head *head) 43{ 44 struct pci_dev_resource *dev_res, *tmp; 45 46 list_for_each_entry_safe(dev_res, tmp, head, list) { 47 list_del(&dev_res->list); 48 kfree(dev_res); 49 } 50} 51 52/** 53 * add_to_list() - Add a new resource tracker to the list 54 * @head: Head of the list 55 * @dev: Device to which the resource belongs 56 * @res: Resource to be tracked 57 * @add_size: Additional size to be optionally added to the resource 58 * @min_align: Minimum memory window alignment 59 */ 60static int add_to_list(struct list_head *head, struct pci_dev *dev, 61 struct resource *res, resource_size_t add_size, 62 resource_size_t min_align) 63{ 64 struct pci_dev_resource *tmp; 65 66 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 67 if (!tmp) 68 return -ENOMEM; 69 70 tmp->res = res; 71 tmp->dev = dev; 72 tmp->start = res->start; 73 tmp->end = res->end; 74 tmp->flags = res->flags; 75 tmp->add_size = add_size; 76 tmp->min_align = min_align; 77 78 list_add(&tmp->list, head); 79 80 return 0; 81} 82 83static void remove_from_list(struct list_head *head, struct resource *res) 84{ 85 struct pci_dev_resource *dev_res, *tmp; 86 87 list_for_each_entry_safe(dev_res, tmp, head, list) { 88 if (dev_res->res == res) { 89 list_del(&dev_res->list); 90 kfree(dev_res); 91 break; 92 } 93 } 94} 95 96static struct pci_dev_resource *res_to_dev_res(struct list_head *head, 97 struct resource *res) 98{ 99 struct pci_dev_resource *dev_res; 100 101 list_for_each_entry(dev_res, head, list) { 102 if (dev_res->res == res) 103 return dev_res; 104 } 105 106 return NULL; 107} 108 109static resource_size_t get_res_add_size(struct list_head *head, 110 struct resource *res) 111{ 112 struct pci_dev_resource *dev_res; 113 114 dev_res = res_to_dev_res(head, res); 115 return dev_res ? dev_res->add_size : 0; 116} 117 118static resource_size_t get_res_add_align(struct list_head *head, 119 struct resource *res) 120{ 121 struct pci_dev_resource *dev_res; 122 123 dev_res = res_to_dev_res(head, res); 124 return dev_res ? dev_res->min_align : 0; 125} 126 127/* Sort resources by alignment */ 128static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) 129{ 130 struct resource *r; 131 int i; 132 133 pci_dev_for_each_resource(dev, r, i) { 134 struct pci_dev_resource *dev_res, *tmp; 135 resource_size_t r_align; 136 struct list_head *n; 137 138 if (r->flags & IORESOURCE_PCI_FIXED) 139 continue; 140 141 if (!(r->flags) || r->parent) 142 continue; 143 144 r_align = pci_resource_alignment(dev, r); 145 if (!r_align) { 146 pci_warn(dev, "BAR %d: %pR has bogus alignment\n", 147 i, r); 148 continue; 149 } 150 151 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 152 if (!tmp) 153 panic("%s: kzalloc() failed!\n", __func__); 154 tmp->res = r; 155 tmp->dev = dev; 156 157 /* Fallback is smallest one or list is empty */ 158 n = head; 159 list_for_each_entry(dev_res, head, list) { 160 resource_size_t align; 161 162 align = pci_resource_alignment(dev_res->dev, 163 dev_res->res); 164 165 if (r_align > align) { 166 n = &dev_res->list; 167 break; 168 } 169 } 170 /* Insert it just before n */ 171 list_add_tail(&tmp->list, n); 172 } 173} 174 175static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head) 176{ 177 u16 class = dev->class >> 8; 178 179 /* Don't touch classless devices or host bridges or IOAPICs */ 180 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) 181 return; 182 183 /* Don't touch IOAPIC devices already enabled by firmware */ 184 if (class == PCI_CLASS_SYSTEM_PIC) { 185 u16 command; 186 pci_read_config_word(dev, PCI_COMMAND, &command); 187 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) 188 return; 189 } 190 191 pdev_sort_resources(dev, head); 192} 193 194static inline void reset_resource(struct resource *res) 195{ 196 res->start = 0; 197 res->end = 0; 198 res->flags = 0; 199} 200 201/** 202 * reassign_resources_sorted() - Satisfy any additional resource requests 203 * 204 * @realloc_head: Head of the list tracking requests requiring 205 * additional resources 206 * @head: Head of the list tracking requests with allocated 207 * resources 208 * 209 * Walk through each element of the realloc_head and try to procure additional 210 * resources for the element, provided the element is in the head list. 211 */ 212static void reassign_resources_sorted(struct list_head *realloc_head, 213 struct list_head *head) 214{ 215 struct resource *res; 216 struct pci_dev_resource *add_res, *tmp; 217 struct pci_dev_resource *dev_res; 218 resource_size_t add_size, align; 219 int idx; 220 221 list_for_each_entry_safe(add_res, tmp, realloc_head, list) { 222 bool found_match = false; 223 224 res = add_res->res; 225 /* Skip resource that has been reset */ 226 if (!res->flags) 227 goto out; 228 229 /* Skip this resource if not found in head list */ 230 list_for_each_entry(dev_res, head, list) { 231 if (dev_res->res == res) { 232 found_match = true; 233 break; 234 } 235 } 236 if (!found_match) /* Just skip */ 237 continue; 238 239 idx = res - &add_res->dev->resource[0]; 240 add_size = add_res->add_size; 241 align = add_res->min_align; 242 if (!resource_size(res)) { 243 res->start = align; 244 res->end = res->start + add_size - 1; 245 if (pci_assign_resource(add_res->dev, idx)) 246 reset_resource(res); 247 } else { 248 res->flags |= add_res->flags & 249 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); 250 if (pci_reassign_resource(add_res->dev, idx, 251 add_size, align)) 252 pci_info(add_res->dev, "failed to add %llx res[%d]=%pR\n", 253 (unsigned long long) add_size, idx, 254 res); 255 } 256out: 257 list_del(&add_res->list); 258 kfree(add_res); 259 } 260} 261 262/** 263 * assign_requested_resources_sorted() - Satisfy resource requests 264 * 265 * @head: Head of the list tracking requests for resources 266 * @fail_head: Head of the list tracking requests that could not be 267 * allocated 268 * 269 * Satisfy resource requests of each element in the list. Add requests that 270 * could not be satisfied to the failed_list. 271 */ 272static void assign_requested_resources_sorted(struct list_head *head, 273 struct list_head *fail_head) 274{ 275 struct resource *res; 276 struct pci_dev_resource *dev_res; 277 int idx; 278 279 list_for_each_entry(dev_res, head, list) { 280 res = dev_res->res; 281 idx = res - &dev_res->dev->resource[0]; 282 if (resource_size(res) && 283 pci_assign_resource(dev_res->dev, idx)) { 284 if (fail_head) { 285 /* 286 * If the failed resource is a ROM BAR and 287 * it will be enabled later, don't add it 288 * to the list. 289 */ 290 if (!((idx == PCI_ROM_RESOURCE) && 291 (!(res->flags & IORESOURCE_ROM_ENABLE)))) 292 add_to_list(fail_head, 293 dev_res->dev, res, 294 0 /* don't care */, 295 0 /* don't care */); 296 } 297 reset_resource(res); 298 } 299 } 300} 301 302static unsigned long pci_fail_res_type_mask(struct list_head *fail_head) 303{ 304 struct pci_dev_resource *fail_res; 305 unsigned long mask = 0; 306 307 /* Check failed type */ 308 list_for_each_entry(fail_res, fail_head, list) 309 mask |= fail_res->flags; 310 311 /* 312 * One pref failed resource will set IORESOURCE_MEM, as we can 313 * allocate pref in non-pref range. Will release all assigned 314 * non-pref sibling resources according to that bit. 315 */ 316 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); 317} 318 319static bool pci_need_to_release(unsigned long mask, struct resource *res) 320{ 321 if (res->flags & IORESOURCE_IO) 322 return !!(mask & IORESOURCE_IO); 323 324 /* Check pref at first */ 325 if (res->flags & IORESOURCE_PREFETCH) { 326 if (mask & IORESOURCE_PREFETCH) 327 return true; 328 /* Count pref if its parent is non-pref */ 329 else if ((mask & IORESOURCE_MEM) && 330 !(res->parent->flags & IORESOURCE_PREFETCH)) 331 return true; 332 else 333 return false; 334 } 335 336 if (res->flags & IORESOURCE_MEM) 337 return !!(mask & IORESOURCE_MEM); 338 339 return false; /* Should not get here */ 340} 341 342static void __assign_resources_sorted(struct list_head *head, 343 struct list_head *realloc_head, 344 struct list_head *fail_head) 345{ 346 /* 347 * Should not assign requested resources at first. They could be 348 * adjacent, so later reassign can not reallocate them one by one in 349 * parent resource window. 350 * 351 * Try to assign requested + add_size at beginning. If could do that, 352 * could get out early. If could not do that, we still try to assign 353 * requested at first, then try to reassign add_size for some resources. 354 * 355 * Separate three resource type checking if we need to release 356 * assigned resource after requested + add_size try. 357 * 358 * 1. If IO port assignment fails, will release assigned IO 359 * port. 360 * 2. If pref MMIO assignment fails, release assigned pref 361 * MMIO. If assigned pref MMIO's parent is non-pref MMIO 362 * and non-pref MMIO assignment fails, will release that 363 * assigned pref MMIO. 364 * 3. If non-pref MMIO assignment fails or pref MMIO 365 * assignment fails, will release assigned non-pref MMIO. 366 */ 367 LIST_HEAD(save_head); 368 LIST_HEAD(local_fail_head); 369 struct pci_dev_resource *save_res; 370 struct pci_dev_resource *dev_res, *tmp_res, *dev_res2; 371 unsigned long fail_type; 372 resource_size_t add_align, align; 373 374 /* Check if optional add_size is there */ 375 if (!realloc_head || list_empty(realloc_head)) 376 goto requested_and_reassign; 377 378 /* Save original start, end, flags etc at first */ 379 list_for_each_entry(dev_res, head, list) { 380 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { 381 free_list(&save_head); 382 goto requested_and_reassign; 383 } 384 } 385 386 /* Update res in head list with add_size in realloc_head list */ 387 list_for_each_entry_safe(dev_res, tmp_res, head, list) { 388 dev_res->res->end += get_res_add_size(realloc_head, 389 dev_res->res); 390 391 /* 392 * There are two kinds of additional resources in the list: 393 * 1. bridge resource -- IORESOURCE_STARTALIGN 394 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN 395 * Here just fix the additional alignment for bridge 396 */ 397 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN)) 398 continue; 399 400 add_align = get_res_add_align(realloc_head, dev_res->res); 401 402 /* 403 * The "head" list is sorted by alignment so resources with 404 * bigger alignment will be assigned first. After we 405 * change the alignment of a dev_res in "head" list, we 406 * need to reorder the list by alignment to make it 407 * consistent. 408 */ 409 if (add_align > dev_res->res->start) { 410 resource_size_t r_size = resource_size(dev_res->res); 411 412 dev_res->res->start = add_align; 413 dev_res->res->end = add_align + r_size - 1; 414 415 list_for_each_entry(dev_res2, head, list) { 416 align = pci_resource_alignment(dev_res2->dev, 417 dev_res2->res); 418 if (add_align > align) { 419 list_move_tail(&dev_res->list, 420 &dev_res2->list); 421 break; 422 } 423 } 424 } 425 426 } 427 428 /* Try updated head list with add_size added */ 429 assign_requested_resources_sorted(head, &local_fail_head); 430 431 /* All assigned with add_size? */ 432 if (list_empty(&local_fail_head)) { 433 /* Remove head list from realloc_head list */ 434 list_for_each_entry(dev_res, head, list) 435 remove_from_list(realloc_head, dev_res->res); 436 free_list(&save_head); 437 free_list(head); 438 return; 439 } 440 441 /* Check failed type */ 442 fail_type = pci_fail_res_type_mask(&local_fail_head); 443 /* Remove not need to be released assigned res from head list etc */ 444 list_for_each_entry_safe(dev_res, tmp_res, head, list) 445 if (dev_res->res->parent && 446 !pci_need_to_release(fail_type, dev_res->res)) { 447 /* Remove it from realloc_head list */ 448 remove_from_list(realloc_head, dev_res->res); 449 remove_from_list(&save_head, dev_res->res); 450 list_del(&dev_res->list); 451 kfree(dev_res); 452 } 453 454 free_list(&local_fail_head); 455 /* Release assigned resource */ 456 list_for_each_entry(dev_res, head, list) 457 if (dev_res->res->parent) 458 release_resource(dev_res->res); 459 /* Restore start/end/flags from saved list */ 460 list_for_each_entry(save_res, &save_head, list) { 461 struct resource *res = save_res->res; 462 463 res->start = save_res->start; 464 res->end = save_res->end; 465 res->flags = save_res->flags; 466 } 467 free_list(&save_head); 468 469requested_and_reassign: 470 /* Satisfy the must-have resource requests */ 471 assign_requested_resources_sorted(head, fail_head); 472 473 /* Try to satisfy any additional optional resource requests */ 474 if (realloc_head) 475 reassign_resources_sorted(realloc_head, head); 476 free_list(head); 477} 478 479static void pdev_assign_resources_sorted(struct pci_dev *dev, 480 struct list_head *add_head, 481 struct list_head *fail_head) 482{ 483 LIST_HEAD(head); 484 485 __dev_sort_resources(dev, &head); 486 __assign_resources_sorted(&head, add_head, fail_head); 487 488} 489 490static void pbus_assign_resources_sorted(const struct pci_bus *bus, 491 struct list_head *realloc_head, 492 struct list_head *fail_head) 493{ 494 struct pci_dev *dev; 495 LIST_HEAD(head); 496 497 list_for_each_entry(dev, &bus->devices, bus_list) 498 __dev_sort_resources(dev, &head); 499 500 __assign_resources_sorted(&head, realloc_head, fail_head); 501} 502 503void pci_setup_cardbus(struct pci_bus *bus) 504{ 505 struct pci_dev *bridge = bus->self; 506 struct resource *res; 507 struct pci_bus_region region; 508 509 pci_info(bridge, "CardBus bridge to %pR\n", 510 &bus->busn_res); 511 512 res = bus->resource[0]; 513 pcibios_resource_to_bus(bridge->bus, ®ion, res); 514 if (res->flags & IORESOURCE_IO) { 515 /* 516 * The IO resource is allocated a range twice as large as it 517 * would normally need. This allows us to set both IO regs. 518 */ 519 pci_info(bridge, " bridge window %pR\n", res); 520 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 521 region.start); 522 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 523 region.end); 524 } 525 526 res = bus->resource[1]; 527 pcibios_resource_to_bus(bridge->bus, ®ion, res); 528 if (res->flags & IORESOURCE_IO) { 529 pci_info(bridge, " bridge window %pR\n", res); 530 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 531 region.start); 532 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 533 region.end); 534 } 535 536 res = bus->resource[2]; 537 pcibios_resource_to_bus(bridge->bus, ®ion, res); 538 if (res->flags & IORESOURCE_MEM) { 539 pci_info(bridge, " bridge window %pR\n", res); 540 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 541 region.start); 542 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 543 region.end); 544 } 545 546 res = bus->resource[3]; 547 pcibios_resource_to_bus(bridge->bus, ®ion, res); 548 if (res->flags & IORESOURCE_MEM) { 549 pci_info(bridge, " bridge window %pR\n", res); 550 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 551 region.start); 552 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 553 region.end); 554 } 555} 556EXPORT_SYMBOL(pci_setup_cardbus); 557 558/* 559 * Initialize bridges with base/limit values we have collected. PCI-to-PCI 560 * Bridge Architecture Specification rev. 1.1 (1998) requires that if there 561 * are no I/O ports or memory behind the bridge, the corresponding range 562 * must be turned off by writing base value greater than limit to the 563 * bridge's base/limit registers. 564 * 565 * Note: care must be taken when updating I/O base/limit registers of 566 * bridges which support 32-bit I/O. This update requires two config space 567 * writes, so it's quite possible that an I/O window of the bridge will 568 * have some undesirable address (e.g. 0) after the first write. Ditto 569 * 64-bit prefetchable MMIO. 570 */ 571static void pci_setup_bridge_io(struct pci_dev *bridge) 572{ 573 struct resource *res; 574 struct pci_bus_region region; 575 unsigned long io_mask; 576 u8 io_base_lo, io_limit_lo; 577 u16 l; 578 u32 io_upper16; 579 580 io_mask = PCI_IO_RANGE_MASK; 581 if (bridge->io_window_1k) 582 io_mask = PCI_IO_1K_RANGE_MASK; 583 584 /* Set up the top and bottom of the PCI I/O segment for this bus */ 585 res = &bridge->resource[PCI_BRIDGE_IO_WINDOW]; 586 pcibios_resource_to_bus(bridge->bus, ®ion, res); 587 if (res->flags & IORESOURCE_IO) { 588 pci_read_config_word(bridge, PCI_IO_BASE, &l); 589 io_base_lo = (region.start >> 8) & io_mask; 590 io_limit_lo = (region.end >> 8) & io_mask; 591 l = ((u16) io_limit_lo << 8) | io_base_lo; 592 /* Set up upper 16 bits of I/O base/limit */ 593 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); 594 pci_info(bridge, " bridge window %pR\n", res); 595 } else { 596 /* Clear upper 16 bits of I/O base/limit */ 597 io_upper16 = 0; 598 l = 0x00f0; 599 } 600 /* Temporarily disable the I/O range before updating PCI_IO_BASE */ 601 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); 602 /* Update lower 16 bits of I/O base/limit */ 603 pci_write_config_word(bridge, PCI_IO_BASE, l); 604 /* Update upper 16 bits of I/O base/limit */ 605 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); 606} 607 608static void pci_setup_bridge_mmio(struct pci_dev *bridge) 609{ 610 struct resource *res; 611 struct pci_bus_region region; 612 u32 l; 613 614 /* Set up the top and bottom of the PCI Memory segment for this bus */ 615 res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW]; 616 pcibios_resource_to_bus(bridge->bus, ®ion, res); 617 if (res->flags & IORESOURCE_MEM) { 618 l = (region.start >> 16) & 0xfff0; 619 l |= region.end & 0xfff00000; 620 pci_info(bridge, " bridge window %pR\n", res); 621 } else { 622 l = 0x0000fff0; 623 } 624 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); 625} 626 627static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge) 628{ 629 struct resource *res; 630 struct pci_bus_region region; 631 u32 l, bu, lu; 632 633 /* 634 * Clear out the upper 32 bits of PREF limit. If 635 * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables 636 * PREF range, which is ok. 637 */ 638 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); 639 640 /* Set up PREF base/limit */ 641 bu = lu = 0; 642 res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 643 pcibios_resource_to_bus(bridge->bus, ®ion, res); 644 if (res->flags & IORESOURCE_PREFETCH) { 645 l = (region.start >> 16) & 0xfff0; 646 l |= region.end & 0xfff00000; 647 if (res->flags & IORESOURCE_MEM_64) { 648 bu = upper_32_bits(region.start); 649 lu = upper_32_bits(region.end); 650 } 651 pci_info(bridge, " bridge window %pR\n", res); 652 } else { 653 l = 0x0000fff0; 654 } 655 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); 656 657 /* Set the upper 32 bits of PREF base & limit */ 658 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); 659 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); 660} 661 662static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) 663{ 664 struct pci_dev *bridge = bus->self; 665 666 pci_info(bridge, "PCI bridge to %pR\n", 667 &bus->busn_res); 668 669 if (type & IORESOURCE_IO) 670 pci_setup_bridge_io(bridge); 671 672 if (type & IORESOURCE_MEM) 673 pci_setup_bridge_mmio(bridge); 674 675 if (type & IORESOURCE_PREFETCH) 676 pci_setup_bridge_mmio_pref(bridge); 677 678 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); 679} 680 681void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) 682{ 683} 684 685void pci_setup_bridge(struct pci_bus *bus) 686{ 687 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | 688 IORESOURCE_PREFETCH; 689 690 pcibios_setup_bridge(bus, type); 691 __pci_setup_bridge(bus, type); 692} 693 694 695int pci_claim_bridge_resource(struct pci_dev *bridge, int i) 696{ 697 if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END) 698 return 0; 699 700 if (pci_claim_resource(bridge, i) == 0) 701 return 0; /* Claimed the window */ 702 703 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI) 704 return 0; 705 706 if (!pci_bus_clip_resource(bridge, i)) 707 return -EINVAL; /* Clipping didn't change anything */ 708 709 switch (i) { 710 case PCI_BRIDGE_IO_WINDOW: 711 pci_setup_bridge_io(bridge); 712 break; 713 case PCI_BRIDGE_MEM_WINDOW: 714 pci_setup_bridge_mmio(bridge); 715 break; 716 case PCI_BRIDGE_PREF_MEM_WINDOW: 717 pci_setup_bridge_mmio_pref(bridge); 718 break; 719 default: 720 return -EINVAL; 721 } 722 723 if (pci_claim_resource(bridge, i) == 0) 724 return 0; /* Claimed a smaller window */ 725 726 return -EINVAL; 727} 728 729/* 730 * Check whether the bridge supports optional I/O and prefetchable memory 731 * ranges. If not, the respective base/limit registers must be read-only 732 * and read as 0. 733 */ 734static void pci_bridge_check_ranges(struct pci_bus *bus) 735{ 736 struct pci_dev *bridge = bus->self; 737 struct resource *b_res; 738 739 b_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW]; 740 b_res->flags |= IORESOURCE_MEM; 741 742 if (bridge->io_window) { 743 b_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW]; 744 b_res->flags |= IORESOURCE_IO; 745 } 746 747 if (bridge->pref_window) { 748 b_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 749 b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; 750 if (bridge->pref_64_window) { 751 b_res->flags |= IORESOURCE_MEM_64 | 752 PCI_PREF_RANGE_TYPE_64; 753 } 754 } 755} 756 757/* 758 * Helper function for sizing routines. Assigned resources have non-NULL 759 * parent resource. 760 * 761 * Return first unassigned resource of the correct type. If there is none, 762 * return first assigned resource of the correct type. If none of the 763 * above, return NULL. 764 * 765 * Returning an assigned resource of the correct type allows the caller to 766 * distinguish between already assigned and no resource of the correct type. 767 */ 768static struct resource *find_bus_resource_of_type(struct pci_bus *bus, 769 unsigned long type_mask, 770 unsigned long type) 771{ 772 struct resource *r, *r_assigned = NULL; 773 774 pci_bus_for_each_resource(bus, r) { 775 if (r == &ioport_resource || r == &iomem_resource) 776 continue; 777 if (r && (r->flags & type_mask) == type && !r->parent) 778 return r; 779 if (r && (r->flags & type_mask) == type && !r_assigned) 780 r_assigned = r; 781 } 782 return r_assigned; 783} 784 785static resource_size_t calculate_iosize(resource_size_t size, 786 resource_size_t min_size, 787 resource_size_t size1, 788 resource_size_t add_size, 789 resource_size_t children_add_size, 790 resource_size_t old_size, 791 resource_size_t align) 792{ 793 if (size < min_size) 794 size = min_size; 795 if (old_size == 1) 796 old_size = 0; 797 /* 798 * To be fixed in 2.5: we should have sort of HAVE_ISA flag in the 799 * struct pci_bus. 800 */ 801#if defined(CONFIG_ISA) || defined(CONFIG_EISA) 802 size = (size & 0xff) + ((size & ~0xffUL) << 2); 803#endif 804 size = size + size1; 805 if (size < old_size) 806 size = old_size; 807 808 size = ALIGN(max(size, add_size) + children_add_size, align); 809 return size; 810} 811 812static resource_size_t calculate_memsize(resource_size_t size, 813 resource_size_t min_size, 814 resource_size_t add_size, 815 resource_size_t children_add_size, 816 resource_size_t old_size, 817 resource_size_t align) 818{ 819 if (size < min_size) 820 size = min_size; 821 if (old_size == 1) 822 old_size = 0; 823 if (size < old_size) 824 size = old_size; 825 826 size = ALIGN(max(size, add_size) + children_add_size, align); 827 return size; 828} 829 830resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus, 831 unsigned long type) 832{ 833 return 1; 834} 835 836#define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */ 837#define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */ 838#define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */ 839 840static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type) 841{ 842 resource_size_t align = 1, arch_align; 843 844 if (type & IORESOURCE_MEM) 845 align = PCI_P2P_DEFAULT_MEM_ALIGN; 846 else if (type & IORESOURCE_IO) { 847 /* 848 * Per spec, I/O windows are 4K-aligned, but some bridges have 849 * an extension to support 1K alignment. 850 */ 851 if (bus->self && bus->self->io_window_1k) 852 align = PCI_P2P_DEFAULT_IO_ALIGN_1K; 853 else 854 align = PCI_P2P_DEFAULT_IO_ALIGN; 855 } 856 857 arch_align = pcibios_window_alignment(bus, type); 858 return max(align, arch_align); 859} 860 861/** 862 * pbus_size_io() - Size the I/O window of a given bus 863 * 864 * @bus: The bus 865 * @min_size: The minimum I/O window that must be allocated 866 * @add_size: Additional optional I/O window 867 * @realloc_head: Track the additional I/O window on this list 868 * 869 * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these 870 * windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI 871 * devices are limited to 256 bytes. We must be careful with the ISA 872 * aliasing though. 873 */ 874static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, 875 resource_size_t add_size, 876 struct list_head *realloc_head) 877{ 878 struct pci_dev *dev; 879 struct resource *b_res = find_bus_resource_of_type(bus, IORESOURCE_IO, 880 IORESOURCE_IO); 881 resource_size_t size = 0, size0 = 0, size1 = 0; 882 resource_size_t children_add_size = 0; 883 resource_size_t min_align, align; 884 885 if (!b_res) 886 return; 887 888 /* If resource is already assigned, nothing more to do */ 889 if (b_res->parent) 890 return; 891 892 min_align = window_alignment(bus, IORESOURCE_IO); 893 list_for_each_entry(dev, &bus->devices, bus_list) { 894 struct resource *r; 895 896 pci_dev_for_each_resource(dev, r) { 897 unsigned long r_size; 898 899 if (r->parent || !(r->flags & IORESOURCE_IO)) 900 continue; 901 r_size = resource_size(r); 902 903 if (r_size < 0x400) 904 /* Might be re-aligned for ISA */ 905 size += r_size; 906 else 907 size1 += r_size; 908 909 align = pci_resource_alignment(dev, r); 910 if (align > min_align) 911 min_align = align; 912 913 if (realloc_head) 914 children_add_size += get_res_add_size(realloc_head, r); 915 } 916 } 917 918 size0 = calculate_iosize(size, min_size, size1, 0, 0, 919 resource_size(b_res), min_align); 920 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 : 921 calculate_iosize(size, min_size, size1, add_size, children_add_size, 922 resource_size(b_res), min_align); 923 if (!size0 && !size1) { 924 if (bus->self && (b_res->start || b_res->end)) 925 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", 926 b_res, &bus->busn_res); 927 b_res->flags = 0; 928 return; 929 } 930 931 b_res->start = min_align; 932 b_res->end = b_res->start + size0 - 1; 933 b_res->flags |= IORESOURCE_STARTALIGN; 934 if (bus->self && size1 > size0 && realloc_head) { 935 add_to_list(realloc_head, bus->self, b_res, size1-size0, 936 min_align); 937 pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n", 938 b_res, &bus->busn_res, 939 (unsigned long long) size1 - size0); 940 } 941} 942 943static inline resource_size_t calculate_mem_align(resource_size_t *aligns, 944 int max_order) 945{ 946 resource_size_t align = 0; 947 resource_size_t min_align = 0; 948 int order; 949 950 for (order = 0; order <= max_order; order++) { 951 resource_size_t align1 = 1; 952 953 align1 <<= (order + 20); 954 955 if (!align) 956 min_align = align1; 957 else if (ALIGN(align + min_align, min_align) < align1) 958 min_align = align1 >> 1; 959 align += aligns[order]; 960 } 961 962 return min_align; 963} 964 965/** 966 * pbus_size_mem() - Size the memory window of a given bus 967 * 968 * @bus: The bus 969 * @mask: Mask the resource flag, then compare it with type 970 * @type: The type of free resource from bridge 971 * @type2: Second match type 972 * @type3: Third match type 973 * @min_size: The minimum memory window that must be allocated 974 * @add_size: Additional optional memory window 975 * @realloc_head: Track the additional memory window on this list 976 * 977 * Calculate the size of the bus and minimal alignment which guarantees 978 * that all child resources fit in this size. 979 * 980 * Return -ENOSPC if there's no available bus resource of the desired 981 * type. Otherwise, set the bus resource start/end to indicate the 982 * required size, add things to realloc_head (if supplied), and return 0. 983 */ 984static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, 985 unsigned long type, unsigned long type2, 986 unsigned long type3, resource_size_t min_size, 987 resource_size_t add_size, 988 struct list_head *realloc_head) 989{ 990 struct pci_dev *dev; 991 resource_size_t min_align, align, size, size0, size1; 992 resource_size_t aligns[24]; /* Alignments from 1MB to 8TB */ 993 int order, max_order; 994 struct resource *b_res = find_bus_resource_of_type(bus, 995 mask | IORESOURCE_PREFETCH, type); 996 resource_size_t children_add_size = 0; 997 resource_size_t children_add_align = 0; 998 resource_size_t add_align = 0; 999 1000 if (!b_res) 1001 return -ENOSPC; 1002 1003 /* If resource is already assigned, nothing more to do */ 1004 if (b_res->parent) 1005 return 0; 1006 1007 memset(aligns, 0, sizeof(aligns)); 1008 max_order = 0; 1009 size = 0; 1010 1011 list_for_each_entry(dev, &bus->devices, bus_list) { 1012 struct resource *r; 1013 int i; 1014 1015 pci_dev_for_each_resource(dev, r, i) { 1016 resource_size_t r_size; 1017 1018 if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) || 1019 ((r->flags & mask) != type && 1020 (r->flags & mask) != type2 && 1021 (r->flags & mask) != type3)) 1022 continue; 1023 r_size = resource_size(r); 1024#ifdef CONFIG_PCI_IOV 1025 /* Put SRIOV requested res to the optional list */ 1026 if (realloc_head && i >= PCI_IOV_RESOURCES && 1027 i <= PCI_IOV_RESOURCE_END) { 1028 add_align = max(pci_resource_alignment(dev, r), add_align); 1029 r->end = r->start - 1; 1030 add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */); 1031 children_add_size += r_size; 1032 continue; 1033 } 1034#endif 1035 /* 1036 * aligns[0] is for 1MB (since bridge memory 1037 * windows are always at least 1MB aligned), so 1038 * keep "order" from being negative for smaller 1039 * resources. 1040 */ 1041 align = pci_resource_alignment(dev, r); 1042 order = __ffs(align) - 20; 1043 if (order < 0) 1044 order = 0; 1045 if (order >= ARRAY_SIZE(aligns)) { 1046 pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n", 1047 i, r, (unsigned long long) align); 1048 r->flags = 0; 1049 continue; 1050 } 1051 size += max(r_size, align); 1052 /* 1053 * Exclude ranges with size > align from calculation of 1054 * the alignment. 1055 */ 1056 if (r_size <= align) 1057 aligns[order] += align; 1058 if (order > max_order) 1059 max_order = order; 1060 1061 if (realloc_head) { 1062 children_add_size += get_res_add_size(realloc_head, r); 1063 children_add_align = get_res_add_align(realloc_head, r); 1064 add_align = max(add_align, children_add_align); 1065 } 1066 } 1067 } 1068 1069 min_align = calculate_mem_align(aligns, max_order); 1070 min_align = max(min_align, window_alignment(bus, b_res->flags)); 1071 size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align); 1072 add_align = max(min_align, add_align); 1073 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 : 1074 calculate_memsize(size, min_size, add_size, children_add_size, 1075 resource_size(b_res), add_align); 1076 if (!size0 && !size1) { 1077 if (bus->self && (b_res->start || b_res->end)) 1078 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", 1079 b_res, &bus->busn_res); 1080 b_res->flags = 0; 1081 return 0; 1082 } 1083 b_res->start = min_align; 1084 b_res->end = size0 + min_align - 1; 1085 b_res->flags |= IORESOURCE_STARTALIGN; 1086 if (bus->self && size1 > size0 && realloc_head) { 1087 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); 1088 pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n", 1089 b_res, &bus->busn_res, 1090 (unsigned long long) (size1 - size0), 1091 (unsigned long long) add_align); 1092 } 1093 return 0; 1094} 1095 1096unsigned long pci_cardbus_resource_alignment(struct resource *res) 1097{ 1098 if (res->flags & IORESOURCE_IO) 1099 return pci_cardbus_io_size; 1100 if (res->flags & IORESOURCE_MEM) 1101 return pci_cardbus_mem_size; 1102 return 0; 1103} 1104 1105static void pci_bus_size_cardbus(struct pci_bus *bus, 1106 struct list_head *realloc_head) 1107{ 1108 struct pci_dev *bridge = bus->self; 1109 struct resource *b_res; 1110 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; 1111 u16 ctrl; 1112 1113 b_res = &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW]; 1114 if (b_res->parent) 1115 goto handle_b_res_1; 1116 /* 1117 * Reserve some resources for CardBus. We reserve a fixed amount 1118 * of bus space for CardBus bridges. 1119 */ 1120 b_res->start = pci_cardbus_io_size; 1121 b_res->end = b_res->start + pci_cardbus_io_size - 1; 1122 b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 1123 if (realloc_head) { 1124 b_res->end -= pci_cardbus_io_size; 1125 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 1126 pci_cardbus_io_size); 1127 } 1128 1129handle_b_res_1: 1130 b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW]; 1131 if (b_res->parent) 1132 goto handle_b_res_2; 1133 b_res->start = pci_cardbus_io_size; 1134 b_res->end = b_res->start + pci_cardbus_io_size - 1; 1135 b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 1136 if (realloc_head) { 1137 b_res->end -= pci_cardbus_io_size; 1138 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 1139 pci_cardbus_io_size); 1140 } 1141 1142handle_b_res_2: 1143 /* MEM1 must not be pref MMIO */ 1144 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1145 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { 1146 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; 1147 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 1148 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1149 } 1150 1151 /* Check whether prefetchable memory is supported by this bridge. */ 1152 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1153 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { 1154 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; 1155 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 1156 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1157 } 1158 1159 b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW]; 1160 if (b_res->parent) 1161 goto handle_b_res_3; 1162 /* 1163 * If we have prefetchable memory support, allocate two regions. 1164 * Otherwise, allocate one region of twice the size. 1165 */ 1166 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 1167 b_res->start = pci_cardbus_mem_size; 1168 b_res->end = b_res->start + pci_cardbus_mem_size - 1; 1169 b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | 1170 IORESOURCE_STARTALIGN; 1171 if (realloc_head) { 1172 b_res->end -= pci_cardbus_mem_size; 1173 add_to_list(realloc_head, bridge, b_res, 1174 pci_cardbus_mem_size, pci_cardbus_mem_size); 1175 } 1176 1177 /* Reduce that to half */ 1178 b_res_3_size = pci_cardbus_mem_size; 1179 } 1180 1181handle_b_res_3: 1182 b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW]; 1183 if (b_res->parent) 1184 goto handle_done; 1185 b_res->start = pci_cardbus_mem_size; 1186 b_res->end = b_res->start + b_res_3_size - 1; 1187 b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; 1188 if (realloc_head) { 1189 b_res->end -= b_res_3_size; 1190 add_to_list(realloc_head, bridge, b_res, b_res_3_size, 1191 pci_cardbus_mem_size); 1192 } 1193 1194handle_done: 1195 ; 1196} 1197 1198void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head) 1199{ 1200 struct pci_dev *dev; 1201 unsigned long mask, prefmask, type2 = 0, type3 = 0; 1202 resource_size_t additional_io_size = 0, additional_mmio_size = 0, 1203 additional_mmio_pref_size = 0; 1204 struct resource *pref; 1205 struct pci_host_bridge *host; 1206 int hdr_type, ret; 1207 1208 list_for_each_entry(dev, &bus->devices, bus_list) { 1209 struct pci_bus *b = dev->subordinate; 1210 if (!b) 1211 continue; 1212 1213 switch (dev->hdr_type) { 1214 case PCI_HEADER_TYPE_CARDBUS: 1215 pci_bus_size_cardbus(b, realloc_head); 1216 break; 1217 1218 case PCI_HEADER_TYPE_BRIDGE: 1219 default: 1220 __pci_bus_size_bridges(b, realloc_head); 1221 break; 1222 } 1223 } 1224 1225 /* The root bus? */ 1226 if (pci_is_root_bus(bus)) { 1227 host = to_pci_host_bridge(bus->bridge); 1228 if (!host->size_windows) 1229 return; 1230 pci_bus_for_each_resource(bus, pref) 1231 if (pref && (pref->flags & IORESOURCE_PREFETCH)) 1232 break; 1233 hdr_type = -1; /* Intentionally invalid - not a PCI device. */ 1234 } else { 1235 pref = &bus->self->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 1236 hdr_type = bus->self->hdr_type; 1237 } 1238 1239 switch (hdr_type) { 1240 case PCI_HEADER_TYPE_CARDBUS: 1241 /* Don't size CardBuses yet */ 1242 break; 1243 1244 case PCI_HEADER_TYPE_BRIDGE: 1245 pci_bridge_check_ranges(bus); 1246 if (bus->self->is_hotplug_bridge) { 1247 additional_io_size = pci_hotplug_io_size; 1248 additional_mmio_size = pci_hotplug_mmio_size; 1249 additional_mmio_pref_size = pci_hotplug_mmio_pref_size; 1250 } 1251 fallthrough; 1252 default: 1253 pbus_size_io(bus, realloc_head ? 0 : additional_io_size, 1254 additional_io_size, realloc_head); 1255 1256 /* 1257 * If there's a 64-bit prefetchable MMIO window, compute 1258 * the size required to put all 64-bit prefetchable 1259 * resources in it. 1260 */ 1261 mask = IORESOURCE_MEM; 1262 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; 1263 if (pref && (pref->flags & IORESOURCE_MEM_64)) { 1264 prefmask |= IORESOURCE_MEM_64; 1265 ret = pbus_size_mem(bus, prefmask, prefmask, 1266 prefmask, prefmask, 1267 realloc_head ? 0 : additional_mmio_pref_size, 1268 additional_mmio_pref_size, realloc_head); 1269 1270 /* 1271 * If successful, all non-prefetchable resources 1272 * and any 32-bit prefetchable resources will go in 1273 * the non-prefetchable window. 1274 */ 1275 if (ret == 0) { 1276 mask = prefmask; 1277 type2 = prefmask & ~IORESOURCE_MEM_64; 1278 type3 = prefmask & ~IORESOURCE_PREFETCH; 1279 } 1280 } 1281 1282 /* 1283 * If there is no 64-bit prefetchable window, compute the 1284 * size required to put all prefetchable resources in the 1285 * 32-bit prefetchable window (if there is one). 1286 */ 1287 if (!type2) { 1288 prefmask &= ~IORESOURCE_MEM_64; 1289 ret = pbus_size_mem(bus, prefmask, prefmask, 1290 prefmask, prefmask, 1291 realloc_head ? 0 : additional_mmio_pref_size, 1292 additional_mmio_pref_size, realloc_head); 1293 1294 /* 1295 * If successful, only non-prefetchable resources 1296 * will go in the non-prefetchable window. 1297 */ 1298 if (ret == 0) 1299 mask = prefmask; 1300 else 1301 additional_mmio_size += additional_mmio_pref_size; 1302 1303 type2 = type3 = IORESOURCE_MEM; 1304 } 1305 1306 /* 1307 * Compute the size required to put everything else in the 1308 * non-prefetchable window. This includes: 1309 * 1310 * - all non-prefetchable resources 1311 * - 32-bit prefetchable resources if there's a 64-bit 1312 * prefetchable window or no prefetchable window at all 1313 * - 64-bit prefetchable resources if there's no prefetchable 1314 * window at all 1315 * 1316 * Note that the strategy in __pci_assign_resource() must match 1317 * that used here. Specifically, we cannot put a 32-bit 1318 * prefetchable resource in a 64-bit prefetchable window. 1319 */ 1320 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3, 1321 realloc_head ? 0 : additional_mmio_size, 1322 additional_mmio_size, realloc_head); 1323 break; 1324 } 1325} 1326 1327void pci_bus_size_bridges(struct pci_bus *bus) 1328{ 1329 __pci_bus_size_bridges(bus, NULL); 1330} 1331EXPORT_SYMBOL(pci_bus_size_bridges); 1332 1333static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r) 1334{ 1335 struct resource *parent_r; 1336 unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM | 1337 IORESOURCE_PREFETCH; 1338 1339 pci_bus_for_each_resource(b, parent_r) { 1340 if (!parent_r) 1341 continue; 1342 1343 if ((r->flags & mask) == (parent_r->flags & mask) && 1344 resource_contains(parent_r, r)) 1345 request_resource(parent_r, r); 1346 } 1347} 1348 1349/* 1350 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are 1351 * skipped by pbus_assign_resources_sorted(). 1352 */ 1353static void pdev_assign_fixed_resources(struct pci_dev *dev) 1354{ 1355 struct resource *r; 1356 1357 pci_dev_for_each_resource(dev, r) { 1358 struct pci_bus *b; 1359 1360 if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) || 1361 !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 1362 continue; 1363 1364 b = dev->bus; 1365 while (b && !r->parent) { 1366 assign_fixed_resource_on_bus(b, r); 1367 b = b->parent; 1368 } 1369 } 1370} 1371 1372void __pci_bus_assign_resources(const struct pci_bus *bus, 1373 struct list_head *realloc_head, 1374 struct list_head *fail_head) 1375{ 1376 struct pci_bus *b; 1377 struct pci_dev *dev; 1378 1379 pbus_assign_resources_sorted(bus, realloc_head, fail_head); 1380 1381 list_for_each_entry(dev, &bus->devices, bus_list) { 1382 pdev_assign_fixed_resources(dev); 1383 1384 b = dev->subordinate; 1385 if (!b) 1386 continue; 1387 1388 __pci_bus_assign_resources(b, realloc_head, fail_head); 1389 1390 switch (dev->hdr_type) { 1391 case PCI_HEADER_TYPE_BRIDGE: 1392 if (!pci_is_enabled(dev)) 1393 pci_setup_bridge(b); 1394 break; 1395 1396 case PCI_HEADER_TYPE_CARDBUS: 1397 pci_setup_cardbus(b); 1398 break; 1399 1400 default: 1401 pci_info(dev, "not setting up bridge for bus %04x:%02x\n", 1402 pci_domain_nr(b), b->number); 1403 break; 1404 } 1405 } 1406} 1407 1408void pci_bus_assign_resources(const struct pci_bus *bus) 1409{ 1410 __pci_bus_assign_resources(bus, NULL, NULL); 1411} 1412EXPORT_SYMBOL(pci_bus_assign_resources); 1413 1414static void pci_claim_device_resources(struct pci_dev *dev) 1415{ 1416 int i; 1417 1418 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 1419 struct resource *r = &dev->resource[i]; 1420 1421 if (!r->flags || r->parent) 1422 continue; 1423 1424 pci_claim_resource(dev, i); 1425 } 1426} 1427 1428static void pci_claim_bridge_resources(struct pci_dev *dev) 1429{ 1430 int i; 1431 1432 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 1433 struct resource *r = &dev->resource[i]; 1434 1435 if (!r->flags || r->parent) 1436 continue; 1437 1438 pci_claim_bridge_resource(dev, i); 1439 } 1440} 1441 1442static void pci_bus_allocate_dev_resources(struct pci_bus *b) 1443{ 1444 struct pci_dev *dev; 1445 struct pci_bus *child; 1446 1447 list_for_each_entry(dev, &b->devices, bus_list) { 1448 pci_claim_device_resources(dev); 1449 1450 child = dev->subordinate; 1451 if (child) 1452 pci_bus_allocate_dev_resources(child); 1453 } 1454} 1455 1456static void pci_bus_allocate_resources(struct pci_bus *b) 1457{ 1458 struct pci_bus *child; 1459 1460 /* 1461 * Carry out a depth-first search on the PCI bus tree to allocate 1462 * bridge apertures. Read the programmed bridge bases and 1463 * recursively claim the respective bridge resources. 1464 */ 1465 if (b->self) { 1466 pci_read_bridge_bases(b); 1467 pci_claim_bridge_resources(b->self); 1468 } 1469 1470 list_for_each_entry(child, &b->children, node) 1471 pci_bus_allocate_resources(child); 1472} 1473 1474void pci_bus_claim_resources(struct pci_bus *b) 1475{ 1476 pci_bus_allocate_resources(b); 1477 pci_bus_allocate_dev_resources(b); 1478} 1479EXPORT_SYMBOL(pci_bus_claim_resources); 1480 1481static void __pci_bridge_assign_resources(const struct pci_dev *bridge, 1482 struct list_head *add_head, 1483 struct list_head *fail_head) 1484{ 1485 struct pci_bus *b; 1486 1487 pdev_assign_resources_sorted((struct pci_dev *)bridge, 1488 add_head, fail_head); 1489 1490 b = bridge->subordinate; 1491 if (!b) 1492 return; 1493 1494 __pci_bus_assign_resources(b, add_head, fail_head); 1495 1496 switch (bridge->class >> 8) { 1497 case PCI_CLASS_BRIDGE_PCI: 1498 pci_setup_bridge(b); 1499 break; 1500 1501 case PCI_CLASS_BRIDGE_CARDBUS: 1502 pci_setup_cardbus(b); 1503 break; 1504 1505 default: 1506 pci_info(bridge, "not setting up bridge for bus %04x:%02x\n", 1507 pci_domain_nr(b), b->number); 1508 break; 1509 } 1510} 1511 1512#define PCI_RES_TYPE_MASK \ 1513 (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\ 1514 IORESOURCE_MEM_64) 1515 1516static void pci_bridge_release_resources(struct pci_bus *bus, 1517 unsigned long type) 1518{ 1519 struct pci_dev *dev = bus->self; 1520 struct resource *r; 1521 unsigned int old_flags; 1522 struct resource *b_res; 1523 int idx = 1; 1524 1525 b_res = &dev->resource[PCI_BRIDGE_RESOURCES]; 1526 1527 /* 1528 * 1. If IO port assignment fails, release bridge IO port. 1529 * 2. If non pref MMIO assignment fails, release bridge nonpref MMIO. 1530 * 3. If 64bit pref MMIO assignment fails, and bridge pref is 64bit, 1531 * release bridge pref MMIO. 1532 * 4. If pref MMIO assignment fails, and bridge pref is 32bit, 1533 * release bridge pref MMIO. 1534 * 5. If pref MMIO assignment fails, and bridge pref is not 1535 * assigned, release bridge nonpref MMIO. 1536 */ 1537 if (type & IORESOURCE_IO) 1538 idx = 0; 1539 else if (!(type & IORESOURCE_PREFETCH)) 1540 idx = 1; 1541 else if ((type & IORESOURCE_MEM_64) && 1542 (b_res[2].flags & IORESOURCE_MEM_64)) 1543 idx = 2; 1544 else if (!(b_res[2].flags & IORESOURCE_MEM_64) && 1545 (b_res[2].flags & IORESOURCE_PREFETCH)) 1546 idx = 2; 1547 else 1548 idx = 1; 1549 1550 r = &b_res[idx]; 1551 1552 if (!r->parent) 1553 return; 1554 1555 /* If there are children, release them all */ 1556 release_child_resources(r); 1557 if (!release_resource(r)) { 1558 type = old_flags = r->flags & PCI_RES_TYPE_MASK; 1559 pci_info(dev, "resource %d %pR released\n", 1560 PCI_BRIDGE_RESOURCES + idx, r); 1561 /* Keep the old size */ 1562 r->end = resource_size(r) - 1; 1563 r->start = 0; 1564 r->flags = 0; 1565 1566 /* Avoiding touch the one without PREF */ 1567 if (type & IORESOURCE_PREFETCH) 1568 type = IORESOURCE_PREFETCH; 1569 __pci_setup_bridge(bus, type); 1570 /* For next child res under same bridge */ 1571 r->flags = old_flags; 1572 } 1573} 1574 1575enum release_type { 1576 leaf_only, 1577 whole_subtree, 1578}; 1579 1580/* 1581 * Try to release PCI bridge resources from leaf bridge, so we can allocate 1582 * a larger window later. 1583 */ 1584static void pci_bus_release_bridge_resources(struct pci_bus *bus, 1585 unsigned long type, 1586 enum release_type rel_type) 1587{ 1588 struct pci_dev *dev; 1589 bool is_leaf_bridge = true; 1590 1591 list_for_each_entry(dev, &bus->devices, bus_list) { 1592 struct pci_bus *b = dev->subordinate; 1593 if (!b) 1594 continue; 1595 1596 is_leaf_bridge = false; 1597 1598 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 1599 continue; 1600 1601 if (rel_type == whole_subtree) 1602 pci_bus_release_bridge_resources(b, type, 1603 whole_subtree); 1604 } 1605 1606 if (pci_is_root_bus(bus)) 1607 return; 1608 1609 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) 1610 return; 1611 1612 if ((rel_type == whole_subtree) || is_leaf_bridge) 1613 pci_bridge_release_resources(bus, type); 1614} 1615 1616static void pci_bus_dump_res(struct pci_bus *bus) 1617{ 1618 struct resource *res; 1619 int i; 1620 1621 pci_bus_for_each_resource(bus, res, i) { 1622 if (!res || !res->end || !res->flags) 1623 continue; 1624 1625 dev_info(&bus->dev, "resource %d %pR\n", i, res); 1626 } 1627} 1628 1629static void pci_bus_dump_resources(struct pci_bus *bus) 1630{ 1631 struct pci_bus *b; 1632 struct pci_dev *dev; 1633 1634 1635 pci_bus_dump_res(bus); 1636 1637 list_for_each_entry(dev, &bus->devices, bus_list) { 1638 b = dev->subordinate; 1639 if (!b) 1640 continue; 1641 1642 pci_bus_dump_resources(b); 1643 } 1644} 1645 1646static int pci_bus_get_depth(struct pci_bus *bus) 1647{ 1648 int depth = 0; 1649 struct pci_bus *child_bus; 1650 1651 list_for_each_entry(child_bus, &bus->children, node) { 1652 int ret; 1653 1654 ret = pci_bus_get_depth(child_bus); 1655 if (ret + 1 > depth) 1656 depth = ret + 1; 1657 } 1658 1659 return depth; 1660} 1661 1662/* 1663 * -1: undefined, will auto detect later 1664 * 0: disabled by user 1665 * 1: disabled by auto detect 1666 * 2: enabled by user 1667 * 3: enabled by auto detect 1668 */ 1669enum enable_type { 1670 undefined = -1, 1671 user_disabled, 1672 auto_disabled, 1673 user_enabled, 1674 auto_enabled, 1675}; 1676 1677static enum enable_type pci_realloc_enable = undefined; 1678void __init pci_realloc_get_opt(char *str) 1679{ 1680 if (!strncmp(str, "off", 3)) 1681 pci_realloc_enable = user_disabled; 1682 else if (!strncmp(str, "on", 2)) 1683 pci_realloc_enable = user_enabled; 1684} 1685static bool pci_realloc_enabled(enum enable_type enable) 1686{ 1687 return enable >= user_enabled; 1688} 1689 1690#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO) 1691static int iov_resources_unassigned(struct pci_dev *dev, void *data) 1692{ 1693 int i; 1694 bool *unassigned = data; 1695 1696 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1697 struct resource *r = &dev->resource[i + PCI_IOV_RESOURCES]; 1698 struct pci_bus_region region; 1699 1700 /* Not assigned or rejected by kernel? */ 1701 if (!r->flags) 1702 continue; 1703 1704 pcibios_resource_to_bus(dev->bus, ®ion, r); 1705 if (!region.start) { 1706 *unassigned = true; 1707 return 1; /* Return early from pci_walk_bus() */ 1708 } 1709 } 1710 1711 return 0; 1712} 1713 1714static enum enable_type pci_realloc_detect(struct pci_bus *bus, 1715 enum enable_type enable_local) 1716{ 1717 bool unassigned = false; 1718 struct pci_host_bridge *host; 1719 1720 if (enable_local != undefined) 1721 return enable_local; 1722 1723 host = pci_find_host_bridge(bus); 1724 if (host->preserve_config) 1725 return auto_disabled; 1726 1727 pci_walk_bus(bus, iov_resources_unassigned, &unassigned); 1728 if (unassigned) 1729 return auto_enabled; 1730 1731 return enable_local; 1732} 1733#else 1734static enum enable_type pci_realloc_detect(struct pci_bus *bus, 1735 enum enable_type enable_local) 1736{ 1737 return enable_local; 1738} 1739#endif 1740 1741static void adjust_bridge_window(struct pci_dev *bridge, struct resource *res, 1742 struct list_head *add_list, 1743 resource_size_t new_size) 1744{ 1745 resource_size_t add_size, size = resource_size(res); 1746 1747 if (res->parent) 1748 return; 1749 1750 if (!new_size) 1751 return; 1752 1753 if (new_size > size) { 1754 add_size = new_size - size; 1755 pci_dbg(bridge, "bridge window %pR extended by %pa\n", res, 1756 &add_size); 1757 } else if (new_size < size) { 1758 add_size = size - new_size; 1759 pci_dbg(bridge, "bridge window %pR shrunken by %pa\n", res, 1760 &add_size); 1761 } else { 1762 return; 1763 } 1764 1765 res->end = res->start + new_size - 1; 1766 1767 /* If the resource is part of the add_list, remove it now */ 1768 if (add_list) 1769 remove_from_list(add_list, res); 1770} 1771 1772static void remove_dev_resource(struct resource *avail, struct pci_dev *dev, 1773 struct resource *res) 1774{ 1775 resource_size_t size, align, tmp; 1776 1777 size = resource_size(res); 1778 if (!size) 1779 return; 1780 1781 align = pci_resource_alignment(dev, res); 1782 align = align ? ALIGN(avail->start, align) - avail->start : 0; 1783 tmp = align + size; 1784 avail->start = min(avail->start + tmp, avail->end + 1); 1785} 1786 1787static void remove_dev_resources(struct pci_dev *dev, struct resource *io, 1788 struct resource *mmio, 1789 struct resource *mmio_pref) 1790{ 1791 struct resource *res; 1792 1793 pci_dev_for_each_resource(dev, res) { 1794 if (resource_type(res) == IORESOURCE_IO) { 1795 remove_dev_resource(io, dev, res); 1796 } else if (resource_type(res) == IORESOURCE_MEM) { 1797 1798 /* 1799 * Make sure prefetchable memory is reduced from 1800 * the correct resource. Specifically we put 32-bit 1801 * prefetchable memory in non-prefetchable window 1802 * if there is an 64-bit prefetchable window. 1803 * 1804 * See comments in __pci_bus_size_bridges() for 1805 * more information. 1806 */ 1807 if ((res->flags & IORESOURCE_PREFETCH) && 1808 ((res->flags & IORESOURCE_MEM_64) == 1809 (mmio_pref->flags & IORESOURCE_MEM_64))) 1810 remove_dev_resource(mmio_pref, dev, res); 1811 else 1812 remove_dev_resource(mmio, dev, res); 1813 } 1814 } 1815} 1816 1817/* 1818 * io, mmio and mmio_pref contain the total amount of bridge window space 1819 * available. This includes the minimal space needed to cover all the 1820 * existing devices on the bus and the possible extra space that can be 1821 * shared with the bridges. 1822 */ 1823static void pci_bus_distribute_available_resources(struct pci_bus *bus, 1824 struct list_head *add_list, 1825 struct resource io, 1826 struct resource mmio, 1827 struct resource mmio_pref) 1828{ 1829 unsigned int normal_bridges = 0, hotplug_bridges = 0; 1830 struct resource *io_res, *mmio_res, *mmio_pref_res; 1831 struct pci_dev *dev, *bridge = bus->self; 1832 resource_size_t io_per_b, mmio_per_b, mmio_pref_per_b, align; 1833 1834 io_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW]; 1835 mmio_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW]; 1836 mmio_pref_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 1837 1838 /* 1839 * The alignment of this bridge is yet to be considered, hence it must 1840 * be done now before extending its bridge window. 1841 */ 1842 align = pci_resource_alignment(bridge, io_res); 1843 if (!io_res->parent && align) 1844 io.start = min(ALIGN(io.start, align), io.end + 1); 1845 1846 align = pci_resource_alignment(bridge, mmio_res); 1847 if (!mmio_res->parent && align) 1848 mmio.start = min(ALIGN(mmio.start, align), mmio.end + 1); 1849 1850 align = pci_resource_alignment(bridge, mmio_pref_res); 1851 if (!mmio_pref_res->parent && align) 1852 mmio_pref.start = min(ALIGN(mmio_pref.start, align), 1853 mmio_pref.end + 1); 1854 1855 /* 1856 * Now that we have adjusted for alignment, update the bridge window 1857 * resources to fill as much remaining resource space as possible. 1858 */ 1859 adjust_bridge_window(bridge, io_res, add_list, resource_size(&io)); 1860 adjust_bridge_window(bridge, mmio_res, add_list, resource_size(&mmio)); 1861 adjust_bridge_window(bridge, mmio_pref_res, add_list, 1862 resource_size(&mmio_pref)); 1863 1864 /* 1865 * Calculate how many hotplug bridges and normal bridges there 1866 * are on this bus. We will distribute the additional available 1867 * resources between hotplug bridges. 1868 */ 1869 for_each_pci_bridge(dev, bus) { 1870 if (dev->is_hotplug_bridge) 1871 hotplug_bridges++; 1872 else 1873 normal_bridges++; 1874 } 1875 1876 if (!(hotplug_bridges + normal_bridges)) 1877 return; 1878 1879 /* 1880 * Calculate the amount of space we can forward from "bus" to any 1881 * downstream buses, i.e., the space left over after assigning the 1882 * BARs and windows on "bus". 1883 */ 1884 list_for_each_entry(dev, &bus->devices, bus_list) { 1885 if (!dev->is_virtfn) 1886 remove_dev_resources(dev, &io, &mmio, &mmio_pref); 1887 } 1888 1889 /* 1890 * If there is at least one hotplug bridge on this bus it gets all 1891 * the extra resource space that was left after the reductions 1892 * above. 1893 * 1894 * If there are no hotplug bridges the extra resource space is 1895 * split between non-hotplug bridges. This is to allow possible 1896 * hotplug bridges below them to get the extra space as well. 1897 */ 1898 if (hotplug_bridges) { 1899 io_per_b = div64_ul(resource_size(&io), hotplug_bridges); 1900 mmio_per_b = div64_ul(resource_size(&mmio), hotplug_bridges); 1901 mmio_pref_per_b = div64_ul(resource_size(&mmio_pref), 1902 hotplug_bridges); 1903 } else { 1904 io_per_b = div64_ul(resource_size(&io), normal_bridges); 1905 mmio_per_b = div64_ul(resource_size(&mmio), normal_bridges); 1906 mmio_pref_per_b = div64_ul(resource_size(&mmio_pref), 1907 normal_bridges); 1908 } 1909 1910 for_each_pci_bridge(dev, bus) { 1911 struct resource *res; 1912 struct pci_bus *b; 1913 1914 b = dev->subordinate; 1915 if (!b) 1916 continue; 1917 if (hotplug_bridges && !dev->is_hotplug_bridge) 1918 continue; 1919 1920 res = &dev->resource[PCI_BRIDGE_IO_WINDOW]; 1921 1922 /* 1923 * Make sure the split resource space is properly aligned 1924 * for bridge windows (align it down to avoid going above 1925 * what is available). 1926 */ 1927 align = pci_resource_alignment(dev, res); 1928 io.end = align ? io.start + ALIGN_DOWN(io_per_b, align) - 1 1929 : io.start + io_per_b - 1; 1930 1931 /* 1932 * The x_per_b holds the extra resource space that can be 1933 * added for each bridge but there is the minimal already 1934 * reserved as well so adjust x.start down accordingly to 1935 * cover the whole space. 1936 */ 1937 io.start -= resource_size(res); 1938 1939 res = &dev->resource[PCI_BRIDGE_MEM_WINDOW]; 1940 align = pci_resource_alignment(dev, res); 1941 mmio.end = align ? mmio.start + ALIGN_DOWN(mmio_per_b, align) - 1 1942 : mmio.start + mmio_per_b - 1; 1943 mmio.start -= resource_size(res); 1944 1945 res = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 1946 align = pci_resource_alignment(dev, res); 1947 mmio_pref.end = align ? mmio_pref.start + 1948 ALIGN_DOWN(mmio_pref_per_b, align) - 1 1949 : mmio_pref.start + mmio_pref_per_b - 1; 1950 mmio_pref.start -= resource_size(res); 1951 1952 pci_bus_distribute_available_resources(b, add_list, io, mmio, 1953 mmio_pref); 1954 1955 io.start += io.end + 1; 1956 mmio.start += mmio.end + 1; 1957 mmio_pref.start += mmio_pref.end + 1; 1958 } 1959} 1960 1961static void pci_bridge_distribute_available_resources(struct pci_dev *bridge, 1962 struct list_head *add_list) 1963{ 1964 struct resource available_io, available_mmio, available_mmio_pref; 1965 1966 if (!bridge->is_hotplug_bridge) 1967 return; 1968 1969 pci_dbg(bridge, "distributing available resources\n"); 1970 1971 /* Take the initial extra resources from the hotplug port */ 1972 available_io = bridge->resource[PCI_BRIDGE_IO_WINDOW]; 1973 available_mmio = bridge->resource[PCI_BRIDGE_MEM_WINDOW]; 1974 available_mmio_pref = bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 1975 1976 pci_bus_distribute_available_resources(bridge->subordinate, 1977 add_list, available_io, 1978 available_mmio, 1979 available_mmio_pref); 1980} 1981 1982static bool pci_bridge_resources_not_assigned(struct pci_dev *dev) 1983{ 1984 const struct resource *r; 1985 1986 /* 1987 * If the child device's resources are not yet assigned it means we 1988 * are configuring them (not the boot firmware), so we should be 1989 * able to extend the upstream bridge resources in the same way we 1990 * do with the normal hotplug case. 1991 */ 1992 r = &dev->resource[PCI_BRIDGE_IO_WINDOW]; 1993 if (r->flags && !(r->flags & IORESOURCE_STARTALIGN)) 1994 return false; 1995 r = &dev->resource[PCI_BRIDGE_MEM_WINDOW]; 1996 if (r->flags && !(r->flags & IORESOURCE_STARTALIGN)) 1997 return false; 1998 r = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 1999 if (r->flags && !(r->flags & IORESOURCE_STARTALIGN)) 2000 return false; 2001 2002 return true; 2003} 2004 2005static void 2006pci_root_bus_distribute_available_resources(struct pci_bus *bus, 2007 struct list_head *add_list) 2008{ 2009 struct pci_dev *dev, *bridge = bus->self; 2010 2011 for_each_pci_bridge(dev, bus) { 2012 struct pci_bus *b; 2013 2014 b = dev->subordinate; 2015 if (!b) 2016 continue; 2017 2018 /* 2019 * Need to check "bridge" here too because it is NULL 2020 * in case of root bus. 2021 */ 2022 if (bridge && pci_bridge_resources_not_assigned(dev)) 2023 pci_bridge_distribute_available_resources(bridge, 2024 add_list); 2025 else 2026 pci_root_bus_distribute_available_resources(b, add_list); 2027 } 2028} 2029 2030/* 2031 * First try will not touch PCI bridge res. 2032 * Second and later try will clear small leaf bridge res. 2033 * Will stop till to the max depth if can not find good one. 2034 */ 2035void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) 2036{ 2037 LIST_HEAD(realloc_head); 2038 /* List of resources that want additional resources */ 2039 struct list_head *add_list = NULL; 2040 int tried_times = 0; 2041 enum release_type rel_type = leaf_only; 2042 LIST_HEAD(fail_head); 2043 struct pci_dev_resource *fail_res; 2044 int pci_try_num = 1; 2045 enum enable_type enable_local; 2046 2047 /* Don't realloc if asked to do so */ 2048 enable_local = pci_realloc_detect(bus, pci_realloc_enable); 2049 if (pci_realloc_enabled(enable_local)) { 2050 int max_depth = pci_bus_get_depth(bus); 2051 2052 pci_try_num = max_depth + 1; 2053 dev_info(&bus->dev, "max bus depth: %d pci_try_num: %d\n", 2054 max_depth, pci_try_num); 2055 } 2056 2057again: 2058 /* 2059 * Last try will use add_list, otherwise will try good to have as must 2060 * have, so can realloc parent bridge resource 2061 */ 2062 if (tried_times + 1 == pci_try_num) 2063 add_list = &realloc_head; 2064 /* 2065 * Depth first, calculate sizes and alignments of all subordinate buses. 2066 */ 2067 __pci_bus_size_bridges(bus, add_list); 2068 2069 pci_root_bus_distribute_available_resources(bus, add_list); 2070 2071 /* Depth last, allocate resources and update the hardware. */ 2072 __pci_bus_assign_resources(bus, add_list, &fail_head); 2073 if (add_list) 2074 BUG_ON(!list_empty(add_list)); 2075 tried_times++; 2076 2077 /* Any device complain? */ 2078 if (list_empty(&fail_head)) 2079 goto dump; 2080 2081 if (tried_times >= pci_try_num) { 2082 if (enable_local == undefined) 2083 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n"); 2084 else if (enable_local == auto_enabled) 2085 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); 2086 2087 free_list(&fail_head); 2088 goto dump; 2089 } 2090 2091 dev_info(&bus->dev, "No. %d try to assign unassigned res\n", 2092 tried_times + 1); 2093 2094 /* Third times and later will not check if it is leaf */ 2095 if ((tried_times + 1) > 2) 2096 rel_type = whole_subtree; 2097 2098 /* 2099 * Try to release leaf bridge's resources that doesn't fit resource of 2100 * child device under that bridge. 2101 */ 2102 list_for_each_entry(fail_res, &fail_head, list) 2103 pci_bus_release_bridge_resources(fail_res->dev->bus, 2104 fail_res->flags & PCI_RES_TYPE_MASK, 2105 rel_type); 2106 2107 /* Restore size and flags */ 2108 list_for_each_entry(fail_res, &fail_head, list) { 2109 struct resource *res = fail_res->res; 2110 int idx; 2111 2112 res->start = fail_res->start; 2113 res->end = fail_res->end; 2114 res->flags = fail_res->flags; 2115 2116 if (pci_is_bridge(fail_res->dev)) { 2117 idx = res - &fail_res->dev->resource[0]; 2118 if (idx >= PCI_BRIDGE_RESOURCES && 2119 idx <= PCI_BRIDGE_RESOURCE_END) 2120 res->flags = 0; 2121 } 2122 } 2123 free_list(&fail_head); 2124 2125 goto again; 2126 2127dump: 2128 /* Dump the resource on buses */ 2129 pci_bus_dump_resources(bus); 2130} 2131 2132void __init pci_assign_unassigned_resources(void) 2133{ 2134 struct pci_bus *root_bus; 2135 2136 list_for_each_entry(root_bus, &pci_root_buses, node) { 2137 pci_assign_unassigned_root_bus_resources(root_bus); 2138 2139 /* Make sure the root bridge has a companion ACPI device */ 2140 if (ACPI_HANDLE(root_bus->bridge)) 2141 acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge)); 2142 } 2143} 2144 2145void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) 2146{ 2147 struct pci_bus *parent = bridge->subordinate; 2148 /* List of resources that want additional resources */ 2149 LIST_HEAD(add_list); 2150 2151 int tried_times = 0; 2152 LIST_HEAD(fail_head); 2153 struct pci_dev_resource *fail_res; 2154 int retval; 2155 2156again: 2157 __pci_bus_size_bridges(parent, &add_list); 2158 2159 /* 2160 * Distribute remaining resources (if any) equally between hotplug 2161 * bridges below. This makes it possible to extend the hierarchy 2162 * later without running out of resources. 2163 */ 2164 pci_bridge_distribute_available_resources(bridge, &add_list); 2165 2166 __pci_bridge_assign_resources(bridge, &add_list, &fail_head); 2167 BUG_ON(!list_empty(&add_list)); 2168 tried_times++; 2169 2170 if (list_empty(&fail_head)) 2171 goto enable_all; 2172 2173 if (tried_times >= 2) { 2174 /* Still fail, don't need to try more */ 2175 free_list(&fail_head); 2176 goto enable_all; 2177 } 2178 2179 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", 2180 tried_times + 1); 2181 2182 /* 2183 * Try to release leaf bridge's resources that aren't big enough 2184 * to contain child device resources. 2185 */ 2186 list_for_each_entry(fail_res, &fail_head, list) 2187 pci_bus_release_bridge_resources(fail_res->dev->bus, 2188 fail_res->flags & PCI_RES_TYPE_MASK, 2189 whole_subtree); 2190 2191 /* Restore size and flags */ 2192 list_for_each_entry(fail_res, &fail_head, list) { 2193 struct resource *res = fail_res->res; 2194 int idx; 2195 2196 res->start = fail_res->start; 2197 res->end = fail_res->end; 2198 res->flags = fail_res->flags; 2199 2200 if (pci_is_bridge(fail_res->dev)) { 2201 idx = res - &fail_res->dev->resource[0]; 2202 if (idx >= PCI_BRIDGE_RESOURCES && 2203 idx <= PCI_BRIDGE_RESOURCE_END) 2204 res->flags = 0; 2205 } 2206 } 2207 free_list(&fail_head); 2208 2209 goto again; 2210 2211enable_all: 2212 retval = pci_reenable_device(bridge); 2213 if (retval) 2214 pci_err(bridge, "Error reenabling bridge (%d)\n", retval); 2215 pci_set_master(bridge); 2216} 2217EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); 2218 2219int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type) 2220{ 2221 struct pci_dev_resource *dev_res; 2222 struct pci_dev *next; 2223 LIST_HEAD(saved); 2224 LIST_HEAD(added); 2225 LIST_HEAD(failed); 2226 unsigned int i; 2227 int ret; 2228 2229 down_read(&pci_bus_sem); 2230 2231 /* Walk to the root hub, releasing bridge BARs when possible */ 2232 next = bridge; 2233 do { 2234 bridge = next; 2235 for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END; 2236 i++) { 2237 struct resource *res = &bridge->resource[i]; 2238 2239 if ((res->flags ^ type) & PCI_RES_TYPE_MASK) 2240 continue; 2241 2242 /* Ignore BARs which are still in use */ 2243 if (res->child) 2244 continue; 2245 2246 ret = add_to_list(&saved, bridge, res, 0, 0); 2247 if (ret) 2248 goto cleanup; 2249 2250 pci_info(bridge, "BAR %d: releasing %pR\n", 2251 i, res); 2252 2253 if (res->parent) 2254 release_resource(res); 2255 res->start = 0; 2256 res->end = 0; 2257 break; 2258 } 2259 if (i == PCI_BRIDGE_RESOURCE_END) 2260 break; 2261 2262 next = bridge->bus ? bridge->bus->self : NULL; 2263 } while (next); 2264 2265 if (list_empty(&saved)) { 2266 up_read(&pci_bus_sem); 2267 return -ENOENT; 2268 } 2269 2270 __pci_bus_size_bridges(bridge->subordinate, &added); 2271 __pci_bridge_assign_resources(bridge, &added, &failed); 2272 BUG_ON(!list_empty(&added)); 2273 2274 if (!list_empty(&failed)) { 2275 ret = -ENOSPC; 2276 goto cleanup; 2277 } 2278 2279 list_for_each_entry(dev_res, &saved, list) { 2280 /* Skip the bridge we just assigned resources for */ 2281 if (bridge == dev_res->dev) 2282 continue; 2283 2284 bridge = dev_res->dev; 2285 pci_setup_bridge(bridge->subordinate); 2286 } 2287 2288 free_list(&saved); 2289 up_read(&pci_bus_sem); 2290 return 0; 2291 2292cleanup: 2293 /* Restore size and flags */ 2294 list_for_each_entry(dev_res, &failed, list) { 2295 struct resource *res = dev_res->res; 2296 2297 res->start = dev_res->start; 2298 res->end = dev_res->end; 2299 res->flags = dev_res->flags; 2300 } 2301 free_list(&failed); 2302 2303 /* Revert to the old configuration */ 2304 list_for_each_entry(dev_res, &saved, list) { 2305 struct resource *res = dev_res->res; 2306 2307 bridge = dev_res->dev; 2308 i = res - bridge->resource; 2309 2310 res->start = dev_res->start; 2311 res->end = dev_res->end; 2312 res->flags = dev_res->flags; 2313 2314 pci_claim_resource(bridge, i); 2315 pci_setup_bridge(bridge->subordinate); 2316 } 2317 free_list(&saved); 2318 up_read(&pci_bus_sem); 2319 2320 return ret; 2321} 2322 2323void pci_assign_unassigned_bus_resources(struct pci_bus *bus) 2324{ 2325 struct pci_dev *dev; 2326 /* List of resources that want additional resources */ 2327 LIST_HEAD(add_list); 2328 2329 down_read(&pci_bus_sem); 2330 for_each_pci_bridge(dev, bus) 2331 if (pci_has_subordinate(dev)) 2332 __pci_bus_size_bridges(dev->subordinate, &add_list); 2333 up_read(&pci_bus_sem); 2334 __pci_bus_assign_resources(bus, &add_list, NULL); 2335 BUG_ON(!list_empty(&add_list)); 2336} 2337EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources); 2338