162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * PCI Express Precision Time Measurement 462306a36Sopenharmony_ci * Copyright (c) 2016, Intel Corporation. 562306a36Sopenharmony_ci */ 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci#include <linux/module.h> 862306a36Sopenharmony_ci#include <linux/init.h> 962306a36Sopenharmony_ci#include <linux/pci.h> 1062306a36Sopenharmony_ci#include "../pci.h" 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci/* 1362306a36Sopenharmony_ci * If the next upstream device supports PTM, return it; otherwise return 1462306a36Sopenharmony_ci * NULL. PTM Messages are local, so both link partners must support it. 1562306a36Sopenharmony_ci */ 1662306a36Sopenharmony_cistatic struct pci_dev *pci_upstream_ptm(struct pci_dev *dev) 1762306a36Sopenharmony_ci{ 1862306a36Sopenharmony_ci struct pci_dev *ups = pci_upstream_bridge(dev); 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ci /* 2162306a36Sopenharmony_ci * Switch Downstream Ports are not permitted to have a PTM 2262306a36Sopenharmony_ci * capability; their PTM behavior is controlled by the Upstream 2362306a36Sopenharmony_ci * Port (PCIe r5.0, sec 7.9.16), so if the upstream bridge is a 2462306a36Sopenharmony_ci * Switch Downstream Port, look up one more level. 2562306a36Sopenharmony_ci */ 2662306a36Sopenharmony_ci if (ups && pci_pcie_type(ups) == PCI_EXP_TYPE_DOWNSTREAM) 2762306a36Sopenharmony_ci ups = pci_upstream_bridge(ups); 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci if (ups && ups->ptm_cap) 3062306a36Sopenharmony_ci return ups; 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci return NULL; 3362306a36Sopenharmony_ci} 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci/* 3662306a36Sopenharmony_ci * Find the PTM Capability (if present) and extract the information we need 3762306a36Sopenharmony_ci * to use it. 3862306a36Sopenharmony_ci */ 3962306a36Sopenharmony_civoid pci_ptm_init(struct pci_dev *dev) 4062306a36Sopenharmony_ci{ 4162306a36Sopenharmony_ci u16 ptm; 4262306a36Sopenharmony_ci u32 cap; 4362306a36Sopenharmony_ci struct pci_dev *ups; 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_ci if (!pci_is_pcie(dev)) 4662306a36Sopenharmony_ci return; 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_ci ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM); 4962306a36Sopenharmony_ci if (!ptm) 5062306a36Sopenharmony_ci return; 5162306a36Sopenharmony_ci 5262306a36Sopenharmony_ci dev->ptm_cap = ptm; 5362306a36Sopenharmony_ci pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_PTM, sizeof(u32)); 5462306a36Sopenharmony_ci 5562306a36Sopenharmony_ci pci_read_config_dword(dev, ptm + PCI_PTM_CAP, &cap); 5662306a36Sopenharmony_ci dev->ptm_granularity = (cap & PCI_PTM_GRANULARITY_MASK) >> 8; 5762306a36Sopenharmony_ci 5862306a36Sopenharmony_ci /* 5962306a36Sopenharmony_ci * Per the spec recommendation (PCIe r6.0, sec 7.9.15.3), select the 6062306a36Sopenharmony_ci * furthest upstream Time Source as the PTM Root. For Endpoints, 6162306a36Sopenharmony_ci * "the Effective Granularity is the maximum Local Clock Granularity 6262306a36Sopenharmony_ci * reported by the PTM Root and all intervening PTM Time Sources." 6362306a36Sopenharmony_ci */ 6462306a36Sopenharmony_ci ups = pci_upstream_ptm(dev); 6562306a36Sopenharmony_ci if (ups) { 6662306a36Sopenharmony_ci if (ups->ptm_granularity == 0) 6762306a36Sopenharmony_ci dev->ptm_granularity = 0; 6862306a36Sopenharmony_ci else if (ups->ptm_granularity > dev->ptm_granularity) 6962306a36Sopenharmony_ci dev->ptm_granularity = ups->ptm_granularity; 7062306a36Sopenharmony_ci } else if (cap & PCI_PTM_CAP_ROOT) { 7162306a36Sopenharmony_ci dev->ptm_root = 1; 7262306a36Sopenharmony_ci } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { 7362306a36Sopenharmony_ci 7462306a36Sopenharmony_ci /* 7562306a36Sopenharmony_ci * Per sec 7.9.15.3, this should be the Local Clock 7662306a36Sopenharmony_ci * Granularity of the associated Time Source. But it 7762306a36Sopenharmony_ci * doesn't say how to find that Time Source. 7862306a36Sopenharmony_ci */ 7962306a36Sopenharmony_ci dev->ptm_granularity = 0; 8062306a36Sopenharmony_ci } 8162306a36Sopenharmony_ci 8262306a36Sopenharmony_ci if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || 8362306a36Sopenharmony_ci pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM) 8462306a36Sopenharmony_ci pci_enable_ptm(dev, NULL); 8562306a36Sopenharmony_ci} 8662306a36Sopenharmony_ci 8762306a36Sopenharmony_civoid pci_save_ptm_state(struct pci_dev *dev) 8862306a36Sopenharmony_ci{ 8962306a36Sopenharmony_ci u16 ptm = dev->ptm_cap; 9062306a36Sopenharmony_ci struct pci_cap_saved_state *save_state; 9162306a36Sopenharmony_ci u32 *cap; 9262306a36Sopenharmony_ci 9362306a36Sopenharmony_ci if (!ptm) 9462306a36Sopenharmony_ci return; 9562306a36Sopenharmony_ci 9662306a36Sopenharmony_ci save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_PTM); 9762306a36Sopenharmony_ci if (!save_state) 9862306a36Sopenharmony_ci return; 9962306a36Sopenharmony_ci 10062306a36Sopenharmony_ci cap = (u32 *)&save_state->cap.data[0]; 10162306a36Sopenharmony_ci pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, cap); 10262306a36Sopenharmony_ci} 10362306a36Sopenharmony_ci 10462306a36Sopenharmony_civoid pci_restore_ptm_state(struct pci_dev *dev) 10562306a36Sopenharmony_ci{ 10662306a36Sopenharmony_ci u16 ptm = dev->ptm_cap; 10762306a36Sopenharmony_ci struct pci_cap_saved_state *save_state; 10862306a36Sopenharmony_ci u32 *cap; 10962306a36Sopenharmony_ci 11062306a36Sopenharmony_ci if (!ptm) 11162306a36Sopenharmony_ci return; 11262306a36Sopenharmony_ci 11362306a36Sopenharmony_ci save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_PTM); 11462306a36Sopenharmony_ci if (!save_state) 11562306a36Sopenharmony_ci return; 11662306a36Sopenharmony_ci 11762306a36Sopenharmony_ci cap = (u32 *)&save_state->cap.data[0]; 11862306a36Sopenharmony_ci pci_write_config_dword(dev, ptm + PCI_PTM_CTRL, *cap); 11962306a36Sopenharmony_ci} 12062306a36Sopenharmony_ci 12162306a36Sopenharmony_ci/* Enable PTM in the Control register if possible */ 12262306a36Sopenharmony_cistatic int __pci_enable_ptm(struct pci_dev *dev) 12362306a36Sopenharmony_ci{ 12462306a36Sopenharmony_ci u16 ptm = dev->ptm_cap; 12562306a36Sopenharmony_ci struct pci_dev *ups; 12662306a36Sopenharmony_ci u32 ctrl; 12762306a36Sopenharmony_ci 12862306a36Sopenharmony_ci if (!ptm) 12962306a36Sopenharmony_ci return -EINVAL; 13062306a36Sopenharmony_ci 13162306a36Sopenharmony_ci /* 13262306a36Sopenharmony_ci * A device uses local PTM Messages to request time information 13362306a36Sopenharmony_ci * from a PTM Root that's farther upstream. Every device along the 13462306a36Sopenharmony_ci * path must support PTM and have it enabled so it can handle the 13562306a36Sopenharmony_ci * messages. Therefore, if this device is not a PTM Root, the 13662306a36Sopenharmony_ci * upstream link partner must have PTM enabled before we can enable 13762306a36Sopenharmony_ci * PTM. 13862306a36Sopenharmony_ci */ 13962306a36Sopenharmony_ci if (!dev->ptm_root) { 14062306a36Sopenharmony_ci ups = pci_upstream_ptm(dev); 14162306a36Sopenharmony_ci if (!ups || !ups->ptm_enabled) 14262306a36Sopenharmony_ci return -EINVAL; 14362306a36Sopenharmony_ci } 14462306a36Sopenharmony_ci 14562306a36Sopenharmony_ci pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, &ctrl); 14662306a36Sopenharmony_ci 14762306a36Sopenharmony_ci ctrl |= PCI_PTM_CTRL_ENABLE; 14862306a36Sopenharmony_ci ctrl &= ~PCI_PTM_GRANULARITY_MASK; 14962306a36Sopenharmony_ci ctrl |= dev->ptm_granularity << 8; 15062306a36Sopenharmony_ci if (dev->ptm_root) 15162306a36Sopenharmony_ci ctrl |= PCI_PTM_CTRL_ROOT; 15262306a36Sopenharmony_ci 15362306a36Sopenharmony_ci pci_write_config_dword(dev, ptm + PCI_PTM_CTRL, ctrl); 15462306a36Sopenharmony_ci return 0; 15562306a36Sopenharmony_ci} 15662306a36Sopenharmony_ci 15762306a36Sopenharmony_ci/** 15862306a36Sopenharmony_ci * pci_enable_ptm() - Enable Precision Time Measurement 15962306a36Sopenharmony_ci * @dev: PCI device 16062306a36Sopenharmony_ci * @granularity: pointer to return granularity 16162306a36Sopenharmony_ci * 16262306a36Sopenharmony_ci * Enable Precision Time Measurement for @dev. If successful and 16362306a36Sopenharmony_ci * @granularity is non-NULL, return the Effective Granularity. 16462306a36Sopenharmony_ci * 16562306a36Sopenharmony_ci * Return: zero if successful, or -EINVAL if @dev lacks a PTM Capability or 16662306a36Sopenharmony_ci * is not a PTM Root and lacks an upstream path of PTM-enabled devices. 16762306a36Sopenharmony_ci */ 16862306a36Sopenharmony_ciint pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 16962306a36Sopenharmony_ci{ 17062306a36Sopenharmony_ci int rc; 17162306a36Sopenharmony_ci char clock_desc[8]; 17262306a36Sopenharmony_ci 17362306a36Sopenharmony_ci rc = __pci_enable_ptm(dev); 17462306a36Sopenharmony_ci if (rc) 17562306a36Sopenharmony_ci return rc; 17662306a36Sopenharmony_ci 17762306a36Sopenharmony_ci dev->ptm_enabled = 1; 17862306a36Sopenharmony_ci 17962306a36Sopenharmony_ci if (granularity) 18062306a36Sopenharmony_ci *granularity = dev->ptm_granularity; 18162306a36Sopenharmony_ci 18262306a36Sopenharmony_ci switch (dev->ptm_granularity) { 18362306a36Sopenharmony_ci case 0: 18462306a36Sopenharmony_ci snprintf(clock_desc, sizeof(clock_desc), "unknown"); 18562306a36Sopenharmony_ci break; 18662306a36Sopenharmony_ci case 255: 18762306a36Sopenharmony_ci snprintf(clock_desc, sizeof(clock_desc), ">254ns"); 18862306a36Sopenharmony_ci break; 18962306a36Sopenharmony_ci default: 19062306a36Sopenharmony_ci snprintf(clock_desc, sizeof(clock_desc), "%uns", 19162306a36Sopenharmony_ci dev->ptm_granularity); 19262306a36Sopenharmony_ci break; 19362306a36Sopenharmony_ci } 19462306a36Sopenharmony_ci pci_info(dev, "PTM enabled%s, %s granularity\n", 19562306a36Sopenharmony_ci dev->ptm_root ? " (root)" : "", clock_desc); 19662306a36Sopenharmony_ci 19762306a36Sopenharmony_ci return 0; 19862306a36Sopenharmony_ci} 19962306a36Sopenharmony_ciEXPORT_SYMBOL(pci_enable_ptm); 20062306a36Sopenharmony_ci 20162306a36Sopenharmony_cistatic void __pci_disable_ptm(struct pci_dev *dev) 20262306a36Sopenharmony_ci{ 20362306a36Sopenharmony_ci u16 ptm = dev->ptm_cap; 20462306a36Sopenharmony_ci u32 ctrl; 20562306a36Sopenharmony_ci 20662306a36Sopenharmony_ci if (!ptm) 20762306a36Sopenharmony_ci return; 20862306a36Sopenharmony_ci 20962306a36Sopenharmony_ci pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, &ctrl); 21062306a36Sopenharmony_ci ctrl &= ~(PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT); 21162306a36Sopenharmony_ci pci_write_config_dword(dev, ptm + PCI_PTM_CTRL, ctrl); 21262306a36Sopenharmony_ci} 21362306a36Sopenharmony_ci 21462306a36Sopenharmony_ci/** 21562306a36Sopenharmony_ci * pci_disable_ptm() - Disable Precision Time Measurement 21662306a36Sopenharmony_ci * @dev: PCI device 21762306a36Sopenharmony_ci * 21862306a36Sopenharmony_ci * Disable Precision Time Measurement for @dev. 21962306a36Sopenharmony_ci */ 22062306a36Sopenharmony_civoid pci_disable_ptm(struct pci_dev *dev) 22162306a36Sopenharmony_ci{ 22262306a36Sopenharmony_ci if (dev->ptm_enabled) { 22362306a36Sopenharmony_ci __pci_disable_ptm(dev); 22462306a36Sopenharmony_ci dev->ptm_enabled = 0; 22562306a36Sopenharmony_ci } 22662306a36Sopenharmony_ci} 22762306a36Sopenharmony_ciEXPORT_SYMBOL(pci_disable_ptm); 22862306a36Sopenharmony_ci 22962306a36Sopenharmony_ci/* 23062306a36Sopenharmony_ci * Disable PTM, but preserve dev->ptm_enabled so we silently re-enable it on 23162306a36Sopenharmony_ci * resume if necessary. 23262306a36Sopenharmony_ci */ 23362306a36Sopenharmony_civoid pci_suspend_ptm(struct pci_dev *dev) 23462306a36Sopenharmony_ci{ 23562306a36Sopenharmony_ci if (dev->ptm_enabled) 23662306a36Sopenharmony_ci __pci_disable_ptm(dev); 23762306a36Sopenharmony_ci} 23862306a36Sopenharmony_ci 23962306a36Sopenharmony_ci/* If PTM was enabled before suspend, re-enable it when resuming */ 24062306a36Sopenharmony_civoid pci_resume_ptm(struct pci_dev *dev) 24162306a36Sopenharmony_ci{ 24262306a36Sopenharmony_ci if (dev->ptm_enabled) 24362306a36Sopenharmony_ci __pci_enable_ptm(dev); 24462306a36Sopenharmony_ci} 24562306a36Sopenharmony_ci 24662306a36Sopenharmony_cibool pcie_ptm_enabled(struct pci_dev *dev) 24762306a36Sopenharmony_ci{ 24862306a36Sopenharmony_ci if (!dev) 24962306a36Sopenharmony_ci return false; 25062306a36Sopenharmony_ci 25162306a36Sopenharmony_ci return dev->ptm_enabled; 25262306a36Sopenharmony_ci} 25362306a36Sopenharmony_ciEXPORT_SYMBOL(pcie_ptm_enabled); 254