162306a36Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0
262306a36Sopenharmony_ci#
362306a36Sopenharmony_ci# PCI Express Port Bus Configuration
462306a36Sopenharmony_ci#
562306a36Sopenharmony_ciconfig PCIEPORTBUS
662306a36Sopenharmony_ci	bool "PCI Express Port Bus support"
762306a36Sopenharmony_ci	default y if USB4
862306a36Sopenharmony_ci	help
962306a36Sopenharmony_ci	  This enables PCI Express Port Bus support. Users can then enable
1062306a36Sopenharmony_ci	  support for Native Hot-Plug, Advanced Error Reporting, Power
1162306a36Sopenharmony_ci	  Management Events, and Downstream Port Containment.
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ci#
1462306a36Sopenharmony_ci# Include service Kconfig here
1562306a36Sopenharmony_ci#
1662306a36Sopenharmony_ciconfig HOTPLUG_PCI_PCIE
1762306a36Sopenharmony_ci	bool "PCI Express Hotplug driver"
1862306a36Sopenharmony_ci	depends on HOTPLUG_PCI && PCIEPORTBUS
1962306a36Sopenharmony_ci	default y if USB4
2062306a36Sopenharmony_ci	help
2162306a36Sopenharmony_ci	  Say Y here if you have a motherboard that supports PCIe native
2262306a36Sopenharmony_ci	  hotplug.
2362306a36Sopenharmony_ci
2462306a36Sopenharmony_ci	  Thunderbolt/USB4 PCIe tunneling depends on native PCIe hotplug.
2562306a36Sopenharmony_ci
2662306a36Sopenharmony_ci	  When in doubt, say N.
2762306a36Sopenharmony_ci
2862306a36Sopenharmony_ciconfig PCIEAER
2962306a36Sopenharmony_ci	bool "PCI Express Advanced Error Reporting support"
3062306a36Sopenharmony_ci	depends on PCIEPORTBUS
3162306a36Sopenharmony_ci	select RAS
3262306a36Sopenharmony_ci	help
3362306a36Sopenharmony_ci	  This enables PCI Express Root Port Advanced Error Reporting
3462306a36Sopenharmony_ci	  (AER) driver support. Error reporting messages sent to Root
3562306a36Sopenharmony_ci	  Port will be handled by PCI Express AER driver.
3662306a36Sopenharmony_ci
3762306a36Sopenharmony_ciconfig PCIEAER_INJECT
3862306a36Sopenharmony_ci	tristate "PCI Express error injection support"
3962306a36Sopenharmony_ci	depends on PCIEAER
4062306a36Sopenharmony_ci	select GENERIC_IRQ_INJECTION
4162306a36Sopenharmony_ci	help
4262306a36Sopenharmony_ci	  This enables PCI Express Root Port Advanced Error Reporting
4362306a36Sopenharmony_ci	  (AER) software error injector.
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_ci	  Debugging AER code is quite difficult because it is hard
4662306a36Sopenharmony_ci	  to trigger various real hardware errors. Software-based
4762306a36Sopenharmony_ci	  error injection can fake almost all kinds of errors with the
4862306a36Sopenharmony_ci	  help of a user space helper tool aer-inject, which can be
4962306a36Sopenharmony_ci	  gotten from:
5062306a36Sopenharmony_ci	     https://git.kernel.org/cgit/linux/kernel/git/gong.chen/aer-inject.git/
5162306a36Sopenharmony_ci
5262306a36Sopenharmony_ci#
5362306a36Sopenharmony_ci# PCI Express ECRC
5462306a36Sopenharmony_ci#
5562306a36Sopenharmony_ciconfig PCIE_ECRC
5662306a36Sopenharmony_ci	bool "PCI Express ECRC settings control"
5762306a36Sopenharmony_ci	depends on PCIEAER
5862306a36Sopenharmony_ci	help
5962306a36Sopenharmony_ci	  Used to override firmware/bios settings for PCI Express ECRC
6062306a36Sopenharmony_ci	  (transaction layer end-to-end CRC checking).
6162306a36Sopenharmony_ci
6262306a36Sopenharmony_ci	  When in doubt, say N.
6362306a36Sopenharmony_ci
6462306a36Sopenharmony_ci#
6562306a36Sopenharmony_ci# PCI Express ASPM
6662306a36Sopenharmony_ci#
6762306a36Sopenharmony_ciconfig PCIEASPM
6862306a36Sopenharmony_ci	bool "PCI Express ASPM control" if EXPERT
6962306a36Sopenharmony_ci	default y
7062306a36Sopenharmony_ci	help
7162306a36Sopenharmony_ci	  This enables OS control over PCI Express ASPM (Active State
7262306a36Sopenharmony_ci	  Power Management) and Clock Power Management. ASPM supports
7362306a36Sopenharmony_ci	  state L0/L0s/L1.
7462306a36Sopenharmony_ci
7562306a36Sopenharmony_ci	  ASPM is initially set up by the firmware. With this option enabled,
7662306a36Sopenharmony_ci	  Linux can modify this state in order to disable ASPM on known-bad
7762306a36Sopenharmony_ci	  hardware or configurations and enable it when known-safe.
7862306a36Sopenharmony_ci
7962306a36Sopenharmony_ci	  ASPM can be disabled or enabled at runtime via
8062306a36Sopenharmony_ci	  /sys/module/pcie_aspm/parameters/policy
8162306a36Sopenharmony_ci
8262306a36Sopenharmony_ci	  When in doubt, say Y.
8362306a36Sopenharmony_ci
8462306a36Sopenharmony_cichoice
8562306a36Sopenharmony_ci	prompt "Default ASPM policy"
8662306a36Sopenharmony_ci	default PCIEASPM_DEFAULT
8762306a36Sopenharmony_ci	depends on PCIEASPM
8862306a36Sopenharmony_ci
8962306a36Sopenharmony_ciconfig PCIEASPM_DEFAULT
9062306a36Sopenharmony_ci	bool "BIOS default"
9162306a36Sopenharmony_ci	depends on PCIEASPM
9262306a36Sopenharmony_ci	help
9362306a36Sopenharmony_ci	  Use the BIOS defaults for PCI Express ASPM.
9462306a36Sopenharmony_ci
9562306a36Sopenharmony_ciconfig PCIEASPM_POWERSAVE
9662306a36Sopenharmony_ci	bool "Powersave"
9762306a36Sopenharmony_ci	depends on PCIEASPM
9862306a36Sopenharmony_ci	help
9962306a36Sopenharmony_ci	  Enable PCI Express ASPM L0s and L1 where possible, even if the
10062306a36Sopenharmony_ci	  BIOS did not.
10162306a36Sopenharmony_ci
10262306a36Sopenharmony_ciconfig PCIEASPM_POWER_SUPERSAVE
10362306a36Sopenharmony_ci	bool "Power Supersave"
10462306a36Sopenharmony_ci	depends on PCIEASPM
10562306a36Sopenharmony_ci	help
10662306a36Sopenharmony_ci	  Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
10762306a36Sopenharmony_ci	  possible. This would result in higher power savings while staying in L1
10862306a36Sopenharmony_ci	  where the components support it.
10962306a36Sopenharmony_ci
11062306a36Sopenharmony_ciconfig PCIEASPM_PERFORMANCE
11162306a36Sopenharmony_ci	bool "Performance"
11262306a36Sopenharmony_ci	depends on PCIEASPM
11362306a36Sopenharmony_ci	help
11462306a36Sopenharmony_ci	  Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
11562306a36Sopenharmony_ciendchoice
11662306a36Sopenharmony_ci
11762306a36Sopenharmony_ciconfig PCIE_PME
11862306a36Sopenharmony_ci	def_bool y
11962306a36Sopenharmony_ci	depends on PCIEPORTBUS && PM
12062306a36Sopenharmony_ci
12162306a36Sopenharmony_ciconfig PCIE_DPC
12262306a36Sopenharmony_ci	bool "PCI Express Downstream Port Containment support"
12362306a36Sopenharmony_ci	depends on PCIEPORTBUS && PCIEAER
12462306a36Sopenharmony_ci	help
12562306a36Sopenharmony_ci	  This enables PCI Express Downstream Port Containment (DPC)
12662306a36Sopenharmony_ci	  driver support.  DPC events from Root and Downstream ports
12762306a36Sopenharmony_ci	  will be handled by the DPC driver.  If your system doesn't
12862306a36Sopenharmony_ci	  have this capability or you do not want to use this feature,
12962306a36Sopenharmony_ci	  it is safe to answer N.
13062306a36Sopenharmony_ci
13162306a36Sopenharmony_ciconfig PCIE_PTM
13262306a36Sopenharmony_ci	bool "PCI Express Precision Time Measurement support"
13362306a36Sopenharmony_ci	help
13462306a36Sopenharmony_ci	  This enables PCI Express Precision Time Measurement (PTM)
13562306a36Sopenharmony_ci	  support.
13662306a36Sopenharmony_ci
13762306a36Sopenharmony_ci	  This is only useful if you have devices that support PTM, but it
13862306a36Sopenharmony_ci	  is safe to enable even if you don't.
13962306a36Sopenharmony_ci
14062306a36Sopenharmony_ciconfig PCIE_EDR
14162306a36Sopenharmony_ci	bool "PCI Express Error Disconnect Recover support"
14262306a36Sopenharmony_ci	depends on PCIE_DPC && ACPI
14362306a36Sopenharmony_ci	help
14462306a36Sopenharmony_ci	  This option adds Error Disconnect Recover support as specified
14562306a36Sopenharmony_ci	  in the Downstream Port Containment Related Enhancements ECN to
14662306a36Sopenharmony_ci	  the PCI Firmware Specification r3.2.  Enable this if you want to
14762306a36Sopenharmony_ci	  support hybrid DPC model which uses both firmware and OS to
14862306a36Sopenharmony_ci	  implement DPC.
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