1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef DRIVERS_PCI_H 3#define DRIVERS_PCI_H 4 5#include <linux/pci.h> 6 7/* Number of possible devfns: 0.0 to 1f.7 inclusive */ 8#define MAX_NR_DEVFNS 256 9 10#define PCI_FIND_CAP_TTL 48 11 12#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 13 14#define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 15 16/* 17 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 18 * Recommends 1ms to 10ms timeout to check L2 ready. 19 */ 20#define PCIE_PME_TO_L2_TIMEOUT_US 10000 21 22extern const unsigned char pcie_link_speed[]; 23extern bool pci_early_dump; 24 25bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 26bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 27bool pcie_cap_has_rtctl(const struct pci_dev *dev); 28 29/* Functions internal to the PCI core code */ 30 31int pci_create_sysfs_dev_files(struct pci_dev *pdev); 32void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 33void pci_cleanup_rom(struct pci_dev *dev); 34#ifdef CONFIG_DMI 35extern const struct attribute_group pci_dev_smbios_attr_group; 36#endif 37 38enum pci_mmap_api { 39 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 40 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 41}; 42int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 43 enum pci_mmap_api mmap_api); 44 45bool pci_reset_supported(struct pci_dev *dev); 46void pci_init_reset_methods(struct pci_dev *dev); 47int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 48int pci_bus_error_reset(struct pci_dev *dev); 49 50struct pci_cap_saved_data { 51 u16 cap_nr; 52 bool cap_extended; 53 unsigned int size; 54 u32 data[]; 55}; 56 57struct pci_cap_saved_state { 58 struct hlist_node next; 59 struct pci_cap_saved_data cap; 60}; 61 62void pci_allocate_cap_save_buffers(struct pci_dev *dev); 63void pci_free_cap_save_buffers(struct pci_dev *dev); 64int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 65int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 66 u16 cap, unsigned int size); 67struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 68struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 69 u16 cap); 70 71#define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 72#define PCI_PM_D3HOT_WAIT 10 /* msec */ 73#define PCI_PM_D3COLD_WAIT 100 /* msec */ 74 75void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 76void pci_refresh_power_state(struct pci_dev *dev); 77int pci_power_up(struct pci_dev *dev); 78void pci_disable_enabled_device(struct pci_dev *dev); 79int pci_finish_runtime_suspend(struct pci_dev *dev); 80void pcie_clear_device_status(struct pci_dev *dev); 81void pcie_clear_root_pme_status(struct pci_dev *dev); 82bool pci_check_pme_status(struct pci_dev *dev); 83void pci_pme_wakeup_bus(struct pci_bus *bus); 84int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 85void pci_pme_restore(struct pci_dev *dev); 86bool pci_dev_need_resume(struct pci_dev *dev); 87void pci_dev_adjust_pme(struct pci_dev *dev); 88void pci_dev_complete_resume(struct pci_dev *pci_dev); 89void pci_config_pm_runtime_get(struct pci_dev *dev); 90void pci_config_pm_runtime_put(struct pci_dev *dev); 91void pci_pm_init(struct pci_dev *dev); 92void pci_ea_init(struct pci_dev *dev); 93void pci_msi_init(struct pci_dev *dev); 94void pci_msix_init(struct pci_dev *dev); 95bool pci_bridge_d3_possible(struct pci_dev *dev); 96void pci_bridge_d3_update(struct pci_dev *dev); 97void pci_bridge_reconfigure_ltr(struct pci_dev *dev); 98int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 99 100static inline void pci_wakeup_event(struct pci_dev *dev) 101{ 102 /* Wait 100 ms before the system can be put into a sleep state. */ 103 pm_wakeup_event(&dev->dev, 100); 104} 105 106static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 107{ 108 return !!(pci_dev->subordinate); 109} 110 111static inline bool pci_power_manageable(struct pci_dev *pci_dev) 112{ 113 /* 114 * Currently we allow normal PCI devices and PCI bridges transition 115 * into D3 if their bridge_d3 is set. 116 */ 117 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 118} 119 120static inline bool pcie_downstream_port(const struct pci_dev *dev) 121{ 122 int type = pci_pcie_type(dev); 123 124 return type == PCI_EXP_TYPE_ROOT_PORT || 125 type == PCI_EXP_TYPE_DOWNSTREAM || 126 type == PCI_EXP_TYPE_PCIE_BRIDGE; 127} 128 129void pci_vpd_init(struct pci_dev *dev); 130void pci_vpd_release(struct pci_dev *dev); 131extern const struct attribute_group pci_dev_vpd_attr_group; 132 133/* PCI Virtual Channel */ 134int pci_save_vc_state(struct pci_dev *dev); 135void pci_restore_vc_state(struct pci_dev *dev); 136void pci_allocate_vc_save_buffers(struct pci_dev *dev); 137 138/* PCI /proc functions */ 139#ifdef CONFIG_PROC_FS 140int pci_proc_attach_device(struct pci_dev *dev); 141int pci_proc_detach_device(struct pci_dev *dev); 142int pci_proc_detach_bus(struct pci_bus *bus); 143#else 144static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 145static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 146static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 147#endif 148 149/* Functions for PCI Hotplug drivers to use */ 150int pci_hp_add_bridge(struct pci_dev *dev); 151 152#ifdef HAVE_PCI_LEGACY 153void pci_create_legacy_files(struct pci_bus *bus); 154void pci_remove_legacy_files(struct pci_bus *bus); 155#else 156static inline void pci_create_legacy_files(struct pci_bus *bus) { } 157static inline void pci_remove_legacy_files(struct pci_bus *bus) { } 158#endif 159 160/* Lock for read/write access to pci device and bus lists */ 161extern struct rw_semaphore pci_bus_sem; 162extern struct mutex pci_slot_mutex; 163 164extern raw_spinlock_t pci_lock; 165 166extern unsigned int pci_pm_d3hot_delay; 167 168#ifdef CONFIG_PCI_MSI 169void pci_no_msi(void); 170#else 171static inline void pci_no_msi(void) { } 172#endif 173 174void pci_realloc_get_opt(char *); 175 176static inline int pci_no_d1d2(struct pci_dev *dev) 177{ 178 unsigned int parent_dstates = 0; 179 180 if (dev->bus->self) 181 parent_dstates = dev->bus->self->no_d1d2; 182 return (dev->no_d1d2 || parent_dstates); 183 184} 185extern const struct attribute_group *pci_dev_groups[]; 186extern const struct attribute_group *pcibus_groups[]; 187extern const struct device_type pci_dev_type; 188extern const struct attribute_group *pci_bus_groups[]; 189 190extern unsigned long pci_hotplug_io_size; 191extern unsigned long pci_hotplug_mmio_size; 192extern unsigned long pci_hotplug_mmio_pref_size; 193extern unsigned long pci_hotplug_bus_size; 194 195/** 196 * pci_match_one_device - Tell if a PCI device structure has a matching 197 * PCI device id structure 198 * @id: single PCI device id structure to match 199 * @dev: the PCI device structure to match against 200 * 201 * Returns the matching pci_device_id structure or %NULL if there is no match. 202 */ 203static inline const struct pci_device_id * 204pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 205{ 206 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 207 (id->device == PCI_ANY_ID || id->device == dev->device) && 208 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 209 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 210 !((id->class ^ dev->class) & id->class_mask)) 211 return id; 212 return NULL; 213} 214 215/* PCI slot sysfs helper code */ 216#define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 217 218extern struct kset *pci_slots_kset; 219 220struct pci_slot_attribute { 221 struct attribute attr; 222 ssize_t (*show)(struct pci_slot *, char *); 223 ssize_t (*store)(struct pci_slot *, const char *, size_t); 224}; 225#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 226 227enum pci_bar_type { 228 pci_bar_unknown, /* Standard PCI BAR probe */ 229 pci_bar_io, /* An I/O port BAR */ 230 pci_bar_mem32, /* A 32-bit memory BAR */ 231 pci_bar_mem64, /* A 64-bit memory BAR */ 232}; 233 234struct device *pci_get_host_bridge_device(struct pci_dev *dev); 235void pci_put_host_bridge_device(struct device *dev); 236 237int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 238bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 239 int crs_timeout); 240bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 241 int crs_timeout); 242int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 243 244int pci_setup_device(struct pci_dev *dev); 245int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 246 struct resource *res, unsigned int reg); 247void pci_configure_ari(struct pci_dev *dev); 248void __pci_bus_size_bridges(struct pci_bus *bus, 249 struct list_head *realloc_head); 250void __pci_bus_assign_resources(const struct pci_bus *bus, 251 struct list_head *realloc_head, 252 struct list_head *fail_head); 253bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 254 255void pci_reassigndev_resource_alignment(struct pci_dev *dev); 256void pci_disable_bridge_window(struct pci_dev *dev); 257struct pci_bus *pci_bus_get(struct pci_bus *bus); 258void pci_bus_put(struct pci_bus *bus); 259 260/* PCIe link information from Link Capabilities 2 */ 261#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 262 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 263 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 264 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 265 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 266 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 267 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 268 PCI_SPEED_UNKNOWN) 269 270/* PCIe speed to Mb/s reduced by encoding overhead */ 271#define PCIE_SPEED2MBS_ENC(speed) \ 272 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 273 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 274 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 275 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 276 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 277 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 278 0) 279 280const char *pci_speed_string(enum pci_bus_speed speed); 281enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 282enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 283u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, 284 enum pcie_link_width *width); 285void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 286void pcie_report_downtraining(struct pci_dev *dev); 287void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 288 289/* Single Root I/O Virtualization */ 290struct pci_sriov { 291 int pos; /* Capability position */ 292 int nres; /* Number of resources */ 293 u32 cap; /* SR-IOV Capabilities */ 294 u16 ctrl; /* SR-IOV Control */ 295 u16 total_VFs; /* Total VFs associated with the PF */ 296 u16 initial_VFs; /* Initial VFs associated with the PF */ 297 u16 num_VFs; /* Number of VFs available */ 298 u16 offset; /* First VF Routing ID offset */ 299 u16 stride; /* Following VF stride */ 300 u16 vf_device; /* VF device ID */ 301 u32 pgsz; /* Page size for BAR alignment */ 302 u8 link; /* Function Dependency Link */ 303 u8 max_VF_buses; /* Max buses consumed by VFs */ 304 u16 driver_max_VFs; /* Max num VFs driver supports */ 305 struct pci_dev *dev; /* Lowest numbered PF */ 306 struct pci_dev *self; /* This PF */ 307 u32 class; /* VF device */ 308 u8 hdr_type; /* VF header type */ 309 u16 subsystem_vendor; /* VF subsystem vendor */ 310 u16 subsystem_device; /* VF subsystem device */ 311 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 312 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 313}; 314 315#ifdef CONFIG_PCI_DOE 316void pci_doe_init(struct pci_dev *pdev); 317void pci_doe_destroy(struct pci_dev *pdev); 318void pci_doe_disconnected(struct pci_dev *pdev); 319#else 320static inline void pci_doe_init(struct pci_dev *pdev) { } 321static inline void pci_doe_destroy(struct pci_dev *pdev) { } 322static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 323#endif 324 325/** 326 * pci_dev_set_io_state - Set the new error state if possible. 327 * 328 * @dev: PCI device to set new error_state 329 * @new: the state we want dev to be in 330 * 331 * If the device is experiencing perm_failure, it has to remain in that state. 332 * Any other transition is allowed. 333 * 334 * Returns true if state has been changed to the requested state. 335 */ 336static inline bool pci_dev_set_io_state(struct pci_dev *dev, 337 pci_channel_state_t new) 338{ 339 pci_channel_state_t old; 340 341 switch (new) { 342 case pci_channel_io_perm_failure: 343 xchg(&dev->error_state, pci_channel_io_perm_failure); 344 return true; 345 case pci_channel_io_frozen: 346 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 347 pci_channel_io_frozen); 348 return old != pci_channel_io_perm_failure; 349 case pci_channel_io_normal: 350 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 351 pci_channel_io_normal); 352 return old != pci_channel_io_perm_failure; 353 default: 354 return false; 355 } 356} 357 358static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 359{ 360 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 361 pci_doe_disconnected(dev); 362 363 return 0; 364} 365 366/* pci_dev priv_flags */ 367#define PCI_DEV_ADDED 0 368#define PCI_DPC_RECOVERED 1 369#define PCI_DPC_RECOVERING 2 370 371static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) 372{ 373 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); 374} 375 376static inline bool pci_dev_is_added(const struct pci_dev *dev) 377{ 378 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 379} 380 381#ifdef CONFIG_PCIEAER 382#include <linux/aer.h> 383 384#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 385 386struct aer_err_info { 387 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 388 int error_dev_num; 389 390 unsigned int id:16; 391 392 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 393 unsigned int __pad1:5; 394 unsigned int multi_error_valid:1; 395 396 unsigned int first_error:5; 397 unsigned int __pad2:2; 398 unsigned int tlp_header_valid:1; 399 400 unsigned int status; /* COR/UNCOR Error Status */ 401 unsigned int mask; /* COR/UNCOR Error Mask */ 402 struct aer_header_log_regs tlp; /* TLP Header */ 403}; 404 405int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 406void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 407#endif /* CONFIG_PCIEAER */ 408 409#ifdef CONFIG_PCIEPORTBUS 410/* Cached RCEC Endpoint Association */ 411struct rcec_ea { 412 u8 nextbusn; 413 u8 lastbusn; 414 u32 bitmap; 415}; 416#endif 417 418#ifdef CONFIG_PCIE_DPC 419void pci_save_dpc_state(struct pci_dev *dev); 420void pci_restore_dpc_state(struct pci_dev *dev); 421void pci_dpc_init(struct pci_dev *pdev); 422void dpc_process_error(struct pci_dev *pdev); 423pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 424bool pci_dpc_recovered(struct pci_dev *pdev); 425#else 426static inline void pci_save_dpc_state(struct pci_dev *dev) { } 427static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 428static inline void pci_dpc_init(struct pci_dev *pdev) { } 429static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 430#endif 431 432#ifdef CONFIG_PCIEPORTBUS 433void pci_rcec_init(struct pci_dev *dev); 434void pci_rcec_exit(struct pci_dev *dev); 435void pcie_link_rcec(struct pci_dev *rcec); 436void pcie_walk_rcec(struct pci_dev *rcec, 437 int (*cb)(struct pci_dev *, void *), 438 void *userdata); 439#else 440static inline void pci_rcec_init(struct pci_dev *dev) { } 441static inline void pci_rcec_exit(struct pci_dev *dev) { } 442static inline void pcie_link_rcec(struct pci_dev *rcec) { } 443static inline void pcie_walk_rcec(struct pci_dev *rcec, 444 int (*cb)(struct pci_dev *, void *), 445 void *userdata) { } 446#endif 447 448#ifdef CONFIG_PCI_ATS 449/* Address Translation Service */ 450void pci_ats_init(struct pci_dev *dev); 451void pci_restore_ats_state(struct pci_dev *dev); 452#else 453static inline void pci_ats_init(struct pci_dev *d) { } 454static inline void pci_restore_ats_state(struct pci_dev *dev) { } 455#endif /* CONFIG_PCI_ATS */ 456 457#ifdef CONFIG_PCI_PRI 458void pci_pri_init(struct pci_dev *dev); 459void pci_restore_pri_state(struct pci_dev *pdev); 460#else 461static inline void pci_pri_init(struct pci_dev *dev) { } 462static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 463#endif 464 465#ifdef CONFIG_PCI_PASID 466void pci_pasid_init(struct pci_dev *dev); 467void pci_restore_pasid_state(struct pci_dev *pdev); 468#else 469static inline void pci_pasid_init(struct pci_dev *dev) { } 470static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 471#endif 472 473#ifdef CONFIG_PCI_IOV 474int pci_iov_init(struct pci_dev *dev); 475void pci_iov_release(struct pci_dev *dev); 476void pci_iov_remove(struct pci_dev *dev); 477void pci_iov_update_resource(struct pci_dev *dev, int resno); 478resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 479void pci_restore_iov_state(struct pci_dev *dev); 480int pci_iov_bus_range(struct pci_bus *bus); 481extern const struct attribute_group sriov_pf_dev_attr_group; 482extern const struct attribute_group sriov_vf_dev_attr_group; 483#else 484static inline int pci_iov_init(struct pci_dev *dev) 485{ 486 return -ENODEV; 487} 488static inline void pci_iov_release(struct pci_dev *dev) { } 489static inline void pci_iov_remove(struct pci_dev *dev) { } 490static inline void pci_restore_iov_state(struct pci_dev *dev) { } 491static inline int pci_iov_bus_range(struct pci_bus *bus) 492{ 493 return 0; 494} 495 496#endif /* CONFIG_PCI_IOV */ 497 498#ifdef CONFIG_PCIE_PTM 499void pci_ptm_init(struct pci_dev *dev); 500void pci_save_ptm_state(struct pci_dev *dev); 501void pci_restore_ptm_state(struct pci_dev *dev); 502void pci_suspend_ptm(struct pci_dev *dev); 503void pci_resume_ptm(struct pci_dev *dev); 504#else 505static inline void pci_ptm_init(struct pci_dev *dev) { } 506static inline void pci_save_ptm_state(struct pci_dev *dev) { } 507static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 508static inline void pci_suspend_ptm(struct pci_dev *dev) { } 509static inline void pci_resume_ptm(struct pci_dev *dev) { } 510#endif 511 512unsigned long pci_cardbus_resource_alignment(struct resource *); 513 514static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 515 struct resource *res) 516{ 517#ifdef CONFIG_PCI_IOV 518 int resno = res - dev->resource; 519 520 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 521 return pci_sriov_resource_alignment(dev, resno); 522#endif 523 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 524 return pci_cardbus_resource_alignment(res); 525 return resource_alignment(res); 526} 527 528void pci_acs_init(struct pci_dev *dev); 529#ifdef CONFIG_PCI_QUIRKS 530int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 531int pci_dev_specific_enable_acs(struct pci_dev *dev); 532int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 533bool pcie_failed_link_retrain(struct pci_dev *dev); 534#else 535static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 536 u16 acs_flags) 537{ 538 return -ENOTTY; 539} 540static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 541{ 542 return -ENOTTY; 543} 544static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 545{ 546 return -ENOTTY; 547} 548static inline bool pcie_failed_link_retrain(struct pci_dev *dev) 549{ 550 return false; 551} 552#endif 553 554/* PCI error reporting and recovery */ 555pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 556 pci_channel_state_t state, 557 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 558 559bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 560int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 561#ifdef CONFIG_PCIEASPM 562void pcie_aspm_init_link_state(struct pci_dev *pdev); 563void pcie_aspm_exit_link_state(struct pci_dev *pdev); 564void pcie_aspm_pm_state_change(struct pci_dev *pdev); 565void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 566#else 567static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 568static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 569static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } 570static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 571#endif 572 573#ifdef CONFIG_PCIE_ECRC 574void pcie_set_ecrc_checking(struct pci_dev *dev); 575void pcie_ecrc_get_policy(char *str); 576#else 577static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 578static inline void pcie_ecrc_get_policy(char *str) { } 579#endif 580 581struct pci_dev_reset_methods { 582 u16 vendor; 583 u16 device; 584 int (*reset)(struct pci_dev *dev, bool probe); 585}; 586 587struct pci_reset_fn_method { 588 int (*reset_fn)(struct pci_dev *pdev, bool probe); 589 char *name; 590}; 591 592#ifdef CONFIG_PCI_QUIRKS 593int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 594#else 595static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 596{ 597 return -ENOTTY; 598} 599#endif 600 601#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 602int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 603 struct resource *res); 604#else 605static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 606 u16 segment, struct resource *res) 607{ 608 return -ENODEV; 609} 610#endif 611 612int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 613int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 614static inline u64 pci_rebar_size_to_bytes(int size) 615{ 616 return 1ULL << (size + 20); 617} 618 619struct device_node; 620 621#ifdef CONFIG_OF 622int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 623int of_get_pci_domain_nr(struct device_node *node); 624int of_pci_get_max_link_speed(struct device_node *node); 625u32 of_pci_get_slot_power_limit(struct device_node *node, 626 u8 *slot_power_limit_value, 627 u8 *slot_power_limit_scale); 628int pci_set_of_node(struct pci_dev *dev); 629void pci_release_of_node(struct pci_dev *dev); 630void pci_set_bus_of_node(struct pci_bus *bus); 631void pci_release_bus_of_node(struct pci_bus *bus); 632 633int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 634 635#else 636static inline int 637of_pci_parse_bus_range(struct device_node *node, struct resource *res) 638{ 639 return -EINVAL; 640} 641 642static inline int 643of_get_pci_domain_nr(struct device_node *node) 644{ 645 return -1; 646} 647 648static inline int 649of_pci_get_max_link_speed(struct device_node *node) 650{ 651 return -EINVAL; 652} 653 654static inline u32 655of_pci_get_slot_power_limit(struct device_node *node, 656 u8 *slot_power_limit_value, 657 u8 *slot_power_limit_scale) 658{ 659 if (slot_power_limit_value) 660 *slot_power_limit_value = 0; 661 if (slot_power_limit_scale) 662 *slot_power_limit_scale = 0; 663 return 0; 664} 665 666static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 667static inline void pci_release_of_node(struct pci_dev *dev) { } 668static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 669static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 670 671static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 672{ 673 return 0; 674} 675 676#endif /* CONFIG_OF */ 677 678struct of_changeset; 679 680#ifdef CONFIG_PCI_DYNAMIC_OF_NODES 681void of_pci_make_dev_node(struct pci_dev *pdev); 682void of_pci_remove_node(struct pci_dev *pdev); 683int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 684 struct device_node *np); 685#else 686static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 687static inline void of_pci_remove_node(struct pci_dev *pdev) { } 688#endif 689 690#ifdef CONFIG_PCIEAER 691void pci_no_aer(void); 692void pci_aer_init(struct pci_dev *dev); 693void pci_aer_exit(struct pci_dev *dev); 694extern const struct attribute_group aer_stats_attr_group; 695void pci_aer_clear_fatal_status(struct pci_dev *dev); 696int pci_aer_clear_status(struct pci_dev *dev); 697int pci_aer_raw_clear_status(struct pci_dev *dev); 698void pci_save_aer_state(struct pci_dev *dev); 699void pci_restore_aer_state(struct pci_dev *dev); 700#else 701static inline void pci_no_aer(void) { } 702static inline void pci_aer_init(struct pci_dev *d) { } 703static inline void pci_aer_exit(struct pci_dev *d) { } 704static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 705static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 706static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 707static inline void pci_save_aer_state(struct pci_dev *dev) { } 708static inline void pci_restore_aer_state(struct pci_dev *dev) { } 709#endif 710 711#ifdef CONFIG_ACPI 712int pci_acpi_program_hp_params(struct pci_dev *dev); 713extern const struct attribute_group pci_dev_acpi_attr_group; 714void pci_set_acpi_fwnode(struct pci_dev *dev); 715int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 716bool acpi_pci_power_manageable(struct pci_dev *dev); 717bool acpi_pci_bridge_d3(struct pci_dev *dev); 718int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 719pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 720void acpi_pci_refresh_power_state(struct pci_dev *dev); 721int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 722bool acpi_pci_need_resume(struct pci_dev *dev); 723pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 724#else 725static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 726{ 727 return -ENOTTY; 728} 729static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 730static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 731{ 732 return -ENODEV; 733} 734static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 735{ 736 return false; 737} 738static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 739{ 740 return false; 741} 742static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 743{ 744 return -ENODEV; 745} 746static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 747{ 748 return PCI_UNKNOWN; 749} 750static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 751static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 752{ 753 return -ENODEV; 754} 755static inline bool acpi_pci_need_resume(struct pci_dev *dev) 756{ 757 return false; 758} 759static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 760{ 761 return PCI_POWER_ERROR; 762} 763#endif 764 765#ifdef CONFIG_PCIEASPM 766extern const struct attribute_group aspm_ctrl_attr_group; 767#endif 768 769extern const struct attribute_group pci_dev_reset_method_attr_group; 770 771#ifdef CONFIG_X86_INTEL_MID 772bool pci_use_mid_pm(void); 773int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 774pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 775#else 776static inline bool pci_use_mid_pm(void) 777{ 778 return false; 779} 780static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 781{ 782 return -ENODEV; 783} 784static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 785{ 786 return PCI_UNKNOWN; 787} 788#endif 789 790/* 791 * Config Address for PCI Configuration Mechanism #1 792 * 793 * See PCI Local Bus Specification, Revision 3.0, 794 * Section 3.2.2.3.2, Figure 3-2, p. 50. 795 */ 796 797#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 798#define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 799#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 800 801#define PCI_CONF1_BUS_MASK 0xff 802#define PCI_CONF1_DEV_MASK 0x1f 803#define PCI_CONF1_FUNC_MASK 0x7 804#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 805 806#define PCI_CONF1_ENABLE BIT(31) 807#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 808#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 809#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 810#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 811 812#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 813 (PCI_CONF1_ENABLE | \ 814 PCI_CONF1_BUS(bus) | \ 815 PCI_CONF1_DEV(dev) | \ 816 PCI_CONF1_FUNC(func) | \ 817 PCI_CONF1_REG(reg)) 818 819/* 820 * Extension of PCI Config Address for accessing extended PCIe registers 821 * 822 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 823 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 824 * are used for specifying additional 4 high bits of PCI Express register. 825 */ 826 827#define PCI_CONF1_EXT_REG_SHIFT 16 828#define PCI_CONF1_EXT_REG_MASK 0xf00 829#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 830 831#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 832 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 833 PCI_CONF1_EXT_REG(reg)) 834 835#endif /* DRIVERS_PCI_H */ 836