1// SPDX-License-Identifier: GPL-2.0 2/* 3 * PCIe host controller driver for Kirin Phone SoCs 4 * 5 * Copyright (C) 2017 HiSilicon Electronics Co., Ltd. 6 * https://www.huawei.com 7 * 8 * Author: Xiaowei Song <songxiaowei@huawei.com> 9 */ 10 11#include <linux/clk.h> 12#include <linux/compiler.h> 13#include <linux/delay.h> 14#include <linux/err.h> 15#include <linux/gpio.h> 16#include <linux/gpio/consumer.h> 17#include <linux/interrupt.h> 18#include <linux/mfd/syscon.h> 19#include <linux/of.h> 20#include <linux/of_gpio.h> 21#include <linux/of_pci.h> 22#include <linux/phy/phy.h> 23#include <linux/pci.h> 24#include <linux/pci_regs.h> 25#include <linux/platform_device.h> 26#include <linux/regmap.h> 27#include <linux/resource.h> 28#include <linux/types.h> 29#include "pcie-designware.h" 30 31#define to_kirin_pcie(x) dev_get_drvdata((x)->dev) 32 33/* PCIe ELBI registers */ 34#define SOC_PCIECTRL_CTRL0_ADDR 0x000 35#define SOC_PCIECTRL_CTRL1_ADDR 0x004 36#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21) 37 38/* info located in APB */ 39#define PCIE_APP_LTSSM_ENABLE 0x01c 40#define PCIE_APB_PHY_STATUS0 0x400 41#define PCIE_LINKUP_ENABLE (0x8020) 42#define PCIE_LTSSM_ENABLE_BIT (0x1 << 11) 43 44/* info located in sysctrl */ 45#define SCTRL_PCIE_CMOS_OFFSET 0x60 46#define SCTRL_PCIE_CMOS_BIT 0x10 47#define SCTRL_PCIE_ISO_OFFSET 0x44 48#define SCTRL_PCIE_ISO_BIT 0x30 49#define SCTRL_PCIE_HPCLK_OFFSET 0x190 50#define SCTRL_PCIE_HPCLK_BIT 0x184000 51#define SCTRL_PCIE_OE_OFFSET 0x14a 52#define PCIE_DEBOUNCE_PARAM 0xF0F400 53#define PCIE_OE_BYPASS (0x3 << 28) 54 55/* 56 * Max number of connected PCI slots at an external PCI bridge 57 * 58 * This is used on HiKey 970, which has a PEX 8606 bridge with 4 connected 59 * lanes (lane 0 upstream, and the other three lanes, one connected to an 60 * in-board Ethernet adapter and the other two connected to M.2 and mini 61 * PCI slots. 62 * 63 * Each slot has a different clock source and uses a separate PERST# pin. 64 */ 65#define MAX_PCI_SLOTS 3 66 67enum pcie_kirin_phy_type { 68 PCIE_KIRIN_INTERNAL_PHY, 69 PCIE_KIRIN_EXTERNAL_PHY 70}; 71 72struct kirin_pcie { 73 enum pcie_kirin_phy_type type; 74 75 struct dw_pcie *pci; 76 struct regmap *apb; 77 struct phy *phy; 78 void *phy_priv; /* only for PCIE_KIRIN_INTERNAL_PHY */ 79 80 /* DWC PERST# */ 81 int gpio_id_dwc_perst; 82 83 /* Per-slot PERST# */ 84 int num_slots; 85 int gpio_id_reset[MAX_PCI_SLOTS]; 86 const char *reset_names[MAX_PCI_SLOTS]; 87 88 /* Per-slot clkreq */ 89 int n_gpio_clkreq; 90 int gpio_id_clkreq[MAX_PCI_SLOTS]; 91 const char *clkreq_names[MAX_PCI_SLOTS]; 92}; 93 94/* 95 * Kirin 960 PHY. Can't be split into a PHY driver without changing the 96 * DT schema. 97 */ 98 99#define REF_CLK_FREQ 100000000 100 101/* PHY info located in APB */ 102#define PCIE_APB_PHY_CTRL0 0x0 103#define PCIE_APB_PHY_CTRL1 0x4 104#define PCIE_APB_PHY_STATUS0 0x400 105#define PIPE_CLK_STABLE BIT(19) 106#define PHY_REF_PAD_BIT BIT(8) 107#define PHY_PWR_DOWN_BIT BIT(22) 108#define PHY_RST_ACK_BIT BIT(16) 109 110/* peri_crg ctrl */ 111#define CRGCTRL_PCIE_ASSERT_OFFSET 0x88 112#define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000 113 114/* Time for delay */ 115#define REF_2_PERST_MIN 21000 116#define REF_2_PERST_MAX 25000 117#define PERST_2_ACCESS_MIN 10000 118#define PERST_2_ACCESS_MAX 12000 119#define PIPE_CLK_WAIT_MIN 550 120#define PIPE_CLK_WAIT_MAX 600 121#define TIME_CMOS_MIN 100 122#define TIME_CMOS_MAX 105 123#define TIME_PHY_PD_MIN 10 124#define TIME_PHY_PD_MAX 11 125 126struct hi3660_pcie_phy { 127 struct device *dev; 128 void __iomem *base; 129 struct regmap *crgctrl; 130 struct regmap *sysctrl; 131 struct clk *apb_sys_clk; 132 struct clk *apb_phy_clk; 133 struct clk *phy_ref_clk; 134 struct clk *aclk; 135 struct clk *aux_clk; 136}; 137 138/* Registers in PCIePHY */ 139static inline void kirin_apb_phy_writel(struct hi3660_pcie_phy *hi3660_pcie_phy, 140 u32 val, u32 reg) 141{ 142 writel(val, hi3660_pcie_phy->base + reg); 143} 144 145static inline u32 kirin_apb_phy_readl(struct hi3660_pcie_phy *hi3660_pcie_phy, 146 u32 reg) 147{ 148 return readl(hi3660_pcie_phy->base + reg); 149} 150 151static int hi3660_pcie_phy_get_clk(struct hi3660_pcie_phy *phy) 152{ 153 struct device *dev = phy->dev; 154 155 phy->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref"); 156 if (IS_ERR(phy->phy_ref_clk)) 157 return PTR_ERR(phy->phy_ref_clk); 158 159 phy->aux_clk = devm_clk_get(dev, "pcie_aux"); 160 if (IS_ERR(phy->aux_clk)) 161 return PTR_ERR(phy->aux_clk); 162 163 phy->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy"); 164 if (IS_ERR(phy->apb_phy_clk)) 165 return PTR_ERR(phy->apb_phy_clk); 166 167 phy->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys"); 168 if (IS_ERR(phy->apb_sys_clk)) 169 return PTR_ERR(phy->apb_sys_clk); 170 171 phy->aclk = devm_clk_get(dev, "pcie_aclk"); 172 if (IS_ERR(phy->aclk)) 173 return PTR_ERR(phy->aclk); 174 175 return 0; 176} 177 178static int hi3660_pcie_phy_get_resource(struct hi3660_pcie_phy *phy) 179{ 180 struct device *dev = phy->dev; 181 struct platform_device *pdev; 182 183 /* registers */ 184 pdev = container_of(dev, struct platform_device, dev); 185 186 phy->base = devm_platform_ioremap_resource_byname(pdev, "phy"); 187 if (IS_ERR(phy->base)) 188 return PTR_ERR(phy->base); 189 190 phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl"); 191 if (IS_ERR(phy->crgctrl)) 192 return PTR_ERR(phy->crgctrl); 193 194 phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl"); 195 if (IS_ERR(phy->sysctrl)) 196 return PTR_ERR(phy->sysctrl); 197 198 return 0; 199} 200 201static int hi3660_pcie_phy_start(struct hi3660_pcie_phy *phy) 202{ 203 struct device *dev = phy->dev; 204 u32 reg_val; 205 206 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1); 207 reg_val &= ~PHY_REF_PAD_BIT; 208 kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1); 209 210 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL0); 211 reg_val &= ~PHY_PWR_DOWN_BIT; 212 kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL0); 213 usleep_range(TIME_PHY_PD_MIN, TIME_PHY_PD_MAX); 214 215 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_CTRL1); 216 reg_val &= ~PHY_RST_ACK_BIT; 217 kirin_apb_phy_writel(phy, reg_val, PCIE_APB_PHY_CTRL1); 218 219 usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX); 220 reg_val = kirin_apb_phy_readl(phy, PCIE_APB_PHY_STATUS0); 221 if (reg_val & PIPE_CLK_STABLE) { 222 dev_err(dev, "PIPE clk is not stable\n"); 223 return -EINVAL; 224 } 225 226 return 0; 227} 228 229static void hi3660_pcie_phy_oe_enable(struct hi3660_pcie_phy *phy) 230{ 231 u32 val; 232 233 regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val); 234 val |= PCIE_DEBOUNCE_PARAM; 235 val &= ~PCIE_OE_BYPASS; 236 regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val); 237} 238 239static int hi3660_pcie_phy_clk_ctrl(struct hi3660_pcie_phy *phy, bool enable) 240{ 241 int ret = 0; 242 243 if (!enable) 244 goto close_clk; 245 246 ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ); 247 if (ret) 248 return ret; 249 250 ret = clk_prepare_enable(phy->phy_ref_clk); 251 if (ret) 252 return ret; 253 254 ret = clk_prepare_enable(phy->apb_sys_clk); 255 if (ret) 256 goto apb_sys_fail; 257 258 ret = clk_prepare_enable(phy->apb_phy_clk); 259 if (ret) 260 goto apb_phy_fail; 261 262 ret = clk_prepare_enable(phy->aclk); 263 if (ret) 264 goto aclk_fail; 265 266 ret = clk_prepare_enable(phy->aux_clk); 267 if (ret) 268 goto aux_clk_fail; 269 270 return 0; 271 272close_clk: 273 clk_disable_unprepare(phy->aux_clk); 274aux_clk_fail: 275 clk_disable_unprepare(phy->aclk); 276aclk_fail: 277 clk_disable_unprepare(phy->apb_phy_clk); 278apb_phy_fail: 279 clk_disable_unprepare(phy->apb_sys_clk); 280apb_sys_fail: 281 clk_disable_unprepare(phy->phy_ref_clk); 282 283 return ret; 284} 285 286static int hi3660_pcie_phy_power_on(struct kirin_pcie *pcie) 287{ 288 struct hi3660_pcie_phy *phy = pcie->phy_priv; 289 int ret; 290 291 /* Power supply for Host */ 292 regmap_write(phy->sysctrl, 293 SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT); 294 usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX); 295 296 hi3660_pcie_phy_oe_enable(phy); 297 298 ret = hi3660_pcie_phy_clk_ctrl(phy, true); 299 if (ret) 300 return ret; 301 302 /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */ 303 regmap_write(phy->sysctrl, 304 SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT); 305 regmap_write(phy->crgctrl, 306 CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT); 307 regmap_write(phy->sysctrl, 308 SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT); 309 310 ret = hi3660_pcie_phy_start(phy); 311 if (ret) 312 goto disable_clks; 313 314 return 0; 315 316disable_clks: 317 hi3660_pcie_phy_clk_ctrl(phy, false); 318 return ret; 319} 320 321static int hi3660_pcie_phy_init(struct platform_device *pdev, 322 struct kirin_pcie *pcie) 323{ 324 struct device *dev = &pdev->dev; 325 struct hi3660_pcie_phy *phy; 326 int ret; 327 328 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); 329 if (!phy) 330 return -ENOMEM; 331 332 pcie->phy_priv = phy; 333 phy->dev = dev; 334 335 ret = hi3660_pcie_phy_get_clk(phy); 336 if (ret) 337 return ret; 338 339 return hi3660_pcie_phy_get_resource(phy); 340} 341 342static int hi3660_pcie_phy_power_off(struct kirin_pcie *pcie) 343{ 344 struct hi3660_pcie_phy *phy = pcie->phy_priv; 345 346 /* Drop power supply for Host */ 347 regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0x00); 348 349 hi3660_pcie_phy_clk_ctrl(phy, false); 350 351 return 0; 352} 353 354/* 355 * The non-PHY part starts here 356 */ 357 358static const struct regmap_config pcie_kirin_regmap_conf = { 359 .name = "kirin_pcie_apb", 360 .reg_bits = 32, 361 .val_bits = 32, 362 .reg_stride = 4, 363}; 364 365static int kirin_pcie_get_gpio_enable(struct kirin_pcie *pcie, 366 struct platform_device *pdev) 367{ 368 struct device *dev = &pdev->dev; 369 char name[32]; 370 int ret, i; 371 372 /* This is an optional property */ 373 ret = gpiod_count(dev, "hisilicon,clken"); 374 if (ret < 0) 375 return 0; 376 377 if (ret > MAX_PCI_SLOTS) { 378 dev_err(dev, "Too many GPIO clock requests!\n"); 379 return -EINVAL; 380 } 381 382 pcie->n_gpio_clkreq = ret; 383 384 for (i = 0; i < pcie->n_gpio_clkreq; i++) { 385 pcie->gpio_id_clkreq[i] = of_get_named_gpio(dev->of_node, 386 "hisilicon,clken-gpios", i); 387 if (pcie->gpio_id_clkreq[i] < 0) 388 return pcie->gpio_id_clkreq[i]; 389 390 sprintf(name, "pcie_clkreq_%d", i); 391 pcie->clkreq_names[i] = devm_kstrdup_const(dev, name, 392 GFP_KERNEL); 393 if (!pcie->clkreq_names[i]) 394 return -ENOMEM; 395 } 396 397 return 0; 398} 399 400static int kirin_pcie_parse_port(struct kirin_pcie *pcie, 401 struct platform_device *pdev, 402 struct device_node *node) 403{ 404 struct device *dev = &pdev->dev; 405 struct device_node *parent, *child; 406 int ret, slot, i; 407 char name[32]; 408 409 for_each_available_child_of_node(node, parent) { 410 for_each_available_child_of_node(parent, child) { 411 i = pcie->num_slots; 412 413 pcie->gpio_id_reset[i] = of_get_named_gpio(child, 414 "reset-gpios", 0); 415 if (pcie->gpio_id_reset[i] < 0) 416 continue; 417 418 pcie->num_slots++; 419 if (pcie->num_slots > MAX_PCI_SLOTS) { 420 dev_err(dev, "Too many PCI slots!\n"); 421 ret = -EINVAL; 422 goto put_node; 423 } 424 425 ret = of_pci_get_devfn(child); 426 if (ret < 0) { 427 dev_err(dev, "failed to parse devfn: %d\n", ret); 428 goto put_node; 429 } 430 431 slot = PCI_SLOT(ret); 432 433 sprintf(name, "pcie_perst_%d", slot); 434 pcie->reset_names[i] = devm_kstrdup_const(dev, name, 435 GFP_KERNEL); 436 if (!pcie->reset_names[i]) { 437 ret = -ENOMEM; 438 goto put_node; 439 } 440 } 441 } 442 443 return 0; 444 445put_node: 446 of_node_put(child); 447 of_node_put(parent); 448 return ret; 449} 450 451static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, 452 struct platform_device *pdev) 453{ 454 struct device *dev = &pdev->dev; 455 struct device_node *child, *node = dev->of_node; 456 void __iomem *apb_base; 457 int ret; 458 459 apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); 460 if (IS_ERR(apb_base)) 461 return PTR_ERR(apb_base); 462 463 kirin_pcie->apb = devm_regmap_init_mmio(dev, apb_base, 464 &pcie_kirin_regmap_conf); 465 if (IS_ERR(kirin_pcie->apb)) 466 return PTR_ERR(kirin_pcie->apb); 467 468 /* pcie internal PERST# gpio */ 469 kirin_pcie->gpio_id_dwc_perst = of_get_named_gpio(dev->of_node, 470 "reset-gpios", 0); 471 if (kirin_pcie->gpio_id_dwc_perst == -EPROBE_DEFER) { 472 return -EPROBE_DEFER; 473 } else if (!gpio_is_valid(kirin_pcie->gpio_id_dwc_perst)) { 474 dev_err(dev, "unable to get a valid gpio pin\n"); 475 return -ENODEV; 476 } 477 478 ret = kirin_pcie_get_gpio_enable(kirin_pcie, pdev); 479 if (ret) 480 return ret; 481 482 /* Parse OF children */ 483 for_each_available_child_of_node(node, child) { 484 ret = kirin_pcie_parse_port(kirin_pcie, pdev, child); 485 if (ret) 486 goto put_node; 487 } 488 489 return 0; 490 491put_node: 492 of_node_put(child); 493 return ret; 494} 495 496static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie, 497 bool on) 498{ 499 u32 val; 500 501 regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, &val); 502 if (on) 503 val = val | PCIE_ELBI_SLV_DBI_ENABLE; 504 else 505 val = val & ~PCIE_ELBI_SLV_DBI_ENABLE; 506 507 regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, val); 508} 509 510static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie, 511 bool on) 512{ 513 u32 val; 514 515 regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, &val); 516 if (on) 517 val = val | PCIE_ELBI_SLV_DBI_ENABLE; 518 else 519 val = val & ~PCIE_ELBI_SLV_DBI_ENABLE; 520 521 regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, val); 522} 523 524static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, 525 int where, int size, u32 *val) 526{ 527 struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); 528 529 if (PCI_SLOT(devfn)) 530 return PCIBIOS_DEVICE_NOT_FOUND; 531 532 *val = dw_pcie_read_dbi(pci, where, size); 533 return PCIBIOS_SUCCESSFUL; 534} 535 536static int kirin_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn, 537 int where, int size, u32 val) 538{ 539 struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); 540 541 if (PCI_SLOT(devfn)) 542 return PCIBIOS_DEVICE_NOT_FOUND; 543 544 dw_pcie_write_dbi(pci, where, size, val); 545 return PCIBIOS_SUCCESSFUL; 546} 547 548static int kirin_pcie_add_bus(struct pci_bus *bus) 549{ 550 struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); 551 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); 552 int i, ret; 553 554 if (!kirin_pcie->num_slots) 555 return 0; 556 557 /* Send PERST# to each slot */ 558 for (i = 0; i < kirin_pcie->num_slots; i++) { 559 ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1); 560 if (ret) { 561 dev_err(pci->dev, "PERST# %s error: %d\n", 562 kirin_pcie->reset_names[i], ret); 563 } 564 } 565 usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); 566 567 return 0; 568} 569 570static struct pci_ops kirin_pci_ops = { 571 .read = kirin_pcie_rd_own_conf, 572 .write = kirin_pcie_wr_own_conf, 573 .add_bus = kirin_pcie_add_bus, 574}; 575 576static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, 577 u32 reg, size_t size) 578{ 579 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); 580 u32 ret; 581 582 kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true); 583 dw_pcie_read(base + reg, size, &ret); 584 kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false); 585 586 return ret; 587} 588 589static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, 590 u32 reg, size_t size, u32 val) 591{ 592 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); 593 594 kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true); 595 dw_pcie_write(base + reg, size, val); 596 kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false); 597} 598 599static int kirin_pcie_link_up(struct dw_pcie *pci) 600{ 601 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); 602 u32 val; 603 604 regmap_read(kirin_pcie->apb, PCIE_APB_PHY_STATUS0, &val); 605 if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE) 606 return 1; 607 608 return 0; 609} 610 611static int kirin_pcie_start_link(struct dw_pcie *pci) 612{ 613 struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); 614 615 /* assert LTSSM enable */ 616 regmap_write(kirin_pcie->apb, PCIE_APP_LTSSM_ENABLE, 617 PCIE_LTSSM_ENABLE_BIT); 618 619 return 0; 620} 621 622static int kirin_pcie_host_init(struct dw_pcie_rp *pp) 623{ 624 pp->bridge->ops = &kirin_pci_ops; 625 626 return 0; 627} 628 629static int kirin_pcie_gpio_request(struct kirin_pcie *kirin_pcie, 630 struct device *dev) 631{ 632 int ret, i; 633 634 for (i = 0; i < kirin_pcie->num_slots; i++) { 635 if (!gpio_is_valid(kirin_pcie->gpio_id_reset[i])) { 636 dev_err(dev, "unable to get a valid %s gpio\n", 637 kirin_pcie->reset_names[i]); 638 return -ENODEV; 639 } 640 641 ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[i], 642 kirin_pcie->reset_names[i]); 643 if (ret) 644 return ret; 645 } 646 647 for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) { 648 if (!gpio_is_valid(kirin_pcie->gpio_id_clkreq[i])) { 649 dev_err(dev, "unable to get a valid %s gpio\n", 650 kirin_pcie->clkreq_names[i]); 651 return -ENODEV; 652 } 653 654 ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[i], 655 kirin_pcie->clkreq_names[i]); 656 if (ret) 657 return ret; 658 659 ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 0); 660 if (ret) 661 return ret; 662 } 663 664 return 0; 665} 666 667static const struct dw_pcie_ops kirin_dw_pcie_ops = { 668 .read_dbi = kirin_pcie_read_dbi, 669 .write_dbi = kirin_pcie_write_dbi, 670 .link_up = kirin_pcie_link_up, 671 .start_link = kirin_pcie_start_link, 672}; 673 674static const struct dw_pcie_host_ops kirin_pcie_host_ops = { 675 .host_init = kirin_pcie_host_init, 676}; 677 678static int kirin_pcie_power_off(struct kirin_pcie *kirin_pcie) 679{ 680 int i; 681 682 if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) 683 return hi3660_pcie_phy_power_off(kirin_pcie); 684 685 for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) 686 gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 1); 687 688 phy_power_off(kirin_pcie->phy); 689 phy_exit(kirin_pcie->phy); 690 691 return 0; 692} 693 694static int kirin_pcie_power_on(struct platform_device *pdev, 695 struct kirin_pcie *kirin_pcie) 696{ 697 struct device *dev = &pdev->dev; 698 int ret; 699 700 if (kirin_pcie->type == PCIE_KIRIN_INTERNAL_PHY) { 701 ret = hi3660_pcie_phy_init(pdev, kirin_pcie); 702 if (ret) 703 return ret; 704 705 ret = hi3660_pcie_phy_power_on(kirin_pcie); 706 if (ret) 707 return ret; 708 } else { 709 kirin_pcie->phy = devm_of_phy_get(dev, dev->of_node, NULL); 710 if (IS_ERR(kirin_pcie->phy)) 711 return PTR_ERR(kirin_pcie->phy); 712 713 ret = kirin_pcie_gpio_request(kirin_pcie, dev); 714 if (ret) 715 return ret; 716 717 ret = phy_init(kirin_pcie->phy); 718 if (ret) 719 goto err; 720 721 ret = phy_power_on(kirin_pcie->phy); 722 if (ret) 723 goto err; 724 } 725 726 /* perst assert Endpoint */ 727 usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX); 728 729 if (!gpio_request(kirin_pcie->gpio_id_dwc_perst, "pcie_perst_bridge")) { 730 ret = gpio_direction_output(kirin_pcie->gpio_id_dwc_perst, 1); 731 if (ret) 732 goto err; 733 } 734 735 usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); 736 737 return 0; 738err: 739 kirin_pcie_power_off(kirin_pcie); 740 741 return ret; 742} 743 744static int kirin_pcie_remove(struct platform_device *pdev) 745{ 746 struct kirin_pcie *kirin_pcie = platform_get_drvdata(pdev); 747 748 dw_pcie_host_deinit(&kirin_pcie->pci->pp); 749 750 kirin_pcie_power_off(kirin_pcie); 751 752 return 0; 753} 754 755struct kirin_pcie_data { 756 enum pcie_kirin_phy_type phy_type; 757}; 758 759static const struct kirin_pcie_data kirin_960_data = { 760 .phy_type = PCIE_KIRIN_INTERNAL_PHY, 761}; 762 763static const struct kirin_pcie_data kirin_970_data = { 764 .phy_type = PCIE_KIRIN_EXTERNAL_PHY, 765}; 766 767static const struct of_device_id kirin_pcie_match[] = { 768 { .compatible = "hisilicon,kirin960-pcie", .data = &kirin_960_data }, 769 { .compatible = "hisilicon,kirin970-pcie", .data = &kirin_970_data }, 770 {}, 771}; 772 773static int kirin_pcie_probe(struct platform_device *pdev) 774{ 775 struct device *dev = &pdev->dev; 776 const struct kirin_pcie_data *data; 777 struct kirin_pcie *kirin_pcie; 778 struct dw_pcie *pci; 779 int ret; 780 781 if (!dev->of_node) { 782 dev_err(dev, "NULL node\n"); 783 return -EINVAL; 784 } 785 786 data = of_device_get_match_data(dev); 787 if (!data) { 788 dev_err(dev, "OF data missing\n"); 789 return -EINVAL; 790 } 791 792 kirin_pcie = devm_kzalloc(dev, sizeof(struct kirin_pcie), GFP_KERNEL); 793 if (!kirin_pcie) 794 return -ENOMEM; 795 796 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 797 if (!pci) 798 return -ENOMEM; 799 800 pci->dev = dev; 801 pci->ops = &kirin_dw_pcie_ops; 802 pci->pp.ops = &kirin_pcie_host_ops; 803 kirin_pcie->pci = pci; 804 kirin_pcie->type = data->phy_type; 805 806 ret = kirin_pcie_get_resource(kirin_pcie, pdev); 807 if (ret) 808 return ret; 809 810 platform_set_drvdata(pdev, kirin_pcie); 811 812 ret = kirin_pcie_power_on(pdev, kirin_pcie); 813 if (ret) 814 return ret; 815 816 return dw_pcie_host_init(&pci->pp); 817} 818 819static struct platform_driver kirin_pcie_driver = { 820 .probe = kirin_pcie_probe, 821 .remove = kirin_pcie_remove, 822 .driver = { 823 .name = "kirin-pcie", 824 .of_match_table = kirin_pcie_match, 825 .suppress_bind_attrs = true, 826 }, 827}; 828module_platform_driver(kirin_pcie_driver); 829 830MODULE_DEVICE_TABLE(of, kirin_pcie_match); 831MODULE_DESCRIPTION("PCIe host controller driver for Kirin Phone SoCs"); 832MODULE_AUTHOR("Xiaowei Song <songxiaowei@huawei.com>"); 833MODULE_LICENSE("GPL v2"); 834