1// SPDX-License-Identifier: GPL-2.0 2/* 3 * PCIe host controller driver for Texas Instruments Keystone SoCs 4 * 5 * Copyright (C) 2013-2014 Texas Instruments., Ltd. 6 * https://www.ti.com 7 * 8 * Author: Murali Karicheri <m-karicheri2@ti.com> 9 * Implementation based on pci-exynos.c and pcie-designware.c 10 */ 11 12#include <linux/clk.h> 13#include <linux/delay.h> 14#include <linux/gpio/consumer.h> 15#include <linux/init.h> 16#include <linux/interrupt.h> 17#include <linux/irqchip/chained_irq.h> 18#include <linux/irqdomain.h> 19#include <linux/mfd/syscon.h> 20#include <linux/msi.h> 21#include <linux/of.h> 22#include <linux/of_irq.h> 23#include <linux/of_pci.h> 24#include <linux/phy/phy.h> 25#include <linux/platform_device.h> 26#include <linux/regmap.h> 27#include <linux/resource.h> 28#include <linux/signal.h> 29 30#include "../../pci.h" 31#include "pcie-designware.h" 32 33#define PCIE_VENDORID_MASK 0xffff 34#define PCIE_DEVICEID_SHIFT 16 35 36/* Application registers */ 37#define CMD_STATUS 0x004 38#define LTSSM_EN_VAL BIT(0) 39#define OB_XLAT_EN_VAL BIT(1) 40#define DBI_CS2 BIT(5) 41 42#define CFG_SETUP 0x008 43#define CFG_BUS(x) (((x) & 0xff) << 16) 44#define CFG_DEVICE(x) (((x) & 0x1f) << 8) 45#define CFG_FUNC(x) ((x) & 0x7) 46#define CFG_TYPE1 BIT(24) 47 48#define OB_SIZE 0x030 49#define OB_OFFSET_INDEX(n) (0x200 + (8 * (n))) 50#define OB_OFFSET_HI(n) (0x204 + (8 * (n))) 51#define OB_ENABLEN BIT(0) 52#define OB_WIN_SIZE 8 /* 8MB */ 53 54#define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1))) 55#define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1))) 56#define PCIE_EP_IRQ_SET 0x64 57#define PCIE_EP_IRQ_CLR 0x68 58#define INT_ENABLE BIT(0) 59 60/* IRQ register defines */ 61#define IRQ_EOI 0x050 62 63#define MSI_IRQ 0x054 64#define MSI_IRQ_STATUS(n) (0x104 + ((n) << 4)) 65#define MSI_IRQ_ENABLE_SET(n) (0x108 + ((n) << 4)) 66#define MSI_IRQ_ENABLE_CLR(n) (0x10c + ((n) << 4)) 67#define MSI_IRQ_OFFSET 4 68 69#define IRQ_STATUS(n) (0x184 + ((n) << 4)) 70#define IRQ_ENABLE_SET(n) (0x188 + ((n) << 4)) 71#define INTx_EN BIT(0) 72 73#define ERR_IRQ_STATUS 0x1c4 74#define ERR_IRQ_ENABLE_SET 0x1c8 75#define ERR_AER BIT(5) /* ECRC error */ 76#define AM6_ERR_AER BIT(4) /* AM6 ECRC error */ 77#define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ 78#define ERR_CORR BIT(3) /* Correctable error */ 79#define ERR_NONFATAL BIT(2) /* Non-fatal error */ 80#define ERR_FATAL BIT(1) /* Fatal error */ 81#define ERR_SYS BIT(0) /* System error */ 82#define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ 83 ERR_NONFATAL | ERR_FATAL | ERR_SYS) 84 85/* PCIE controller device IDs */ 86#define PCIE_RC_K2HK 0xb008 87#define PCIE_RC_K2E 0xb009 88#define PCIE_RC_K2L 0xb00a 89#define PCIE_RC_K2G 0xb00b 90 91#define KS_PCIE_DEV_TYPE_MASK (0x3 << 1) 92#define KS_PCIE_DEV_TYPE(mode) ((mode) << 1) 93 94#define EP 0x0 95#define LEG_EP 0x1 96#define RC 0x2 97 98#define KS_PCIE_SYSCLOCKOUTEN BIT(0) 99 100#define AM654_PCIE_DEV_TYPE_MASK 0x3 101#define AM654_WIN_SIZE SZ_64K 102 103#define APP_ADDR_SPACE_0 (16 * SZ_1K) 104 105#define to_keystone_pcie(x) dev_get_drvdata((x)->dev) 106 107struct ks_pcie_of_data { 108 enum dw_pcie_device_mode mode; 109 const struct dw_pcie_host_ops *host_ops; 110 const struct dw_pcie_ep_ops *ep_ops; 111 u32 version; 112}; 113 114struct keystone_pcie { 115 struct dw_pcie *pci; 116 /* PCI Device ID */ 117 u32 device_id; 118 int legacy_host_irqs[PCI_NUM_INTX]; 119 struct device_node *legacy_intc_np; 120 121 int msi_host_irq; 122 int num_lanes; 123 u32 num_viewport; 124 struct phy **phy; 125 struct device_link **link; 126 struct device_node *msi_intc_np; 127 struct irq_domain *legacy_irq_domain; 128 struct device_node *np; 129 130 /* Application register space */ 131 void __iomem *va_app_base; /* DT 1st resource */ 132 struct resource app; 133 bool is_am6; 134}; 135 136static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) 137{ 138 return readl(ks_pcie->va_app_base + offset); 139} 140 141static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, 142 u32 val) 143{ 144 writel(val, ks_pcie->va_app_base + offset); 145} 146 147static void ks_pcie_msi_irq_ack(struct irq_data *data) 148{ 149 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 150 struct keystone_pcie *ks_pcie; 151 u32 irq = data->hwirq; 152 struct dw_pcie *pci; 153 u32 reg_offset; 154 u32 bit_pos; 155 156 pci = to_dw_pcie_from_pp(pp); 157 ks_pcie = to_keystone_pcie(pci); 158 159 reg_offset = irq % 8; 160 bit_pos = irq >> 3; 161 162 ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), 163 BIT(bit_pos)); 164 ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); 165} 166 167static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 168{ 169 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 170 struct keystone_pcie *ks_pcie; 171 struct dw_pcie *pci; 172 u64 msi_target; 173 174 pci = to_dw_pcie_from_pp(pp); 175 ks_pcie = to_keystone_pcie(pci); 176 177 msi_target = ks_pcie->app.start + MSI_IRQ; 178 msg->address_lo = lower_32_bits(msi_target); 179 msg->address_hi = upper_32_bits(msi_target); 180 msg->data = data->hwirq; 181 182 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 183 (int)data->hwirq, msg->address_hi, msg->address_lo); 184} 185 186static int ks_pcie_msi_set_affinity(struct irq_data *irq_data, 187 const struct cpumask *mask, bool force) 188{ 189 return -EINVAL; 190} 191 192static void ks_pcie_msi_mask(struct irq_data *data) 193{ 194 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 195 struct keystone_pcie *ks_pcie; 196 u32 irq = data->hwirq; 197 struct dw_pcie *pci; 198 unsigned long flags; 199 u32 reg_offset; 200 u32 bit_pos; 201 202 raw_spin_lock_irqsave(&pp->lock, flags); 203 204 pci = to_dw_pcie_from_pp(pp); 205 ks_pcie = to_keystone_pcie(pci); 206 207 reg_offset = irq % 8; 208 bit_pos = irq >> 3; 209 210 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), 211 BIT(bit_pos)); 212 213 raw_spin_unlock_irqrestore(&pp->lock, flags); 214} 215 216static void ks_pcie_msi_unmask(struct irq_data *data) 217{ 218 struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(data); 219 struct keystone_pcie *ks_pcie; 220 u32 irq = data->hwirq; 221 struct dw_pcie *pci; 222 unsigned long flags; 223 u32 reg_offset; 224 u32 bit_pos; 225 226 raw_spin_lock_irqsave(&pp->lock, flags); 227 228 pci = to_dw_pcie_from_pp(pp); 229 ks_pcie = to_keystone_pcie(pci); 230 231 reg_offset = irq % 8; 232 bit_pos = irq >> 3; 233 234 ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), 235 BIT(bit_pos)); 236 237 raw_spin_unlock_irqrestore(&pp->lock, flags); 238} 239 240static struct irq_chip ks_pcie_msi_irq_chip = { 241 .name = "KEYSTONE-PCI-MSI", 242 .irq_ack = ks_pcie_msi_irq_ack, 243 .irq_compose_msi_msg = ks_pcie_compose_msi_msg, 244 .irq_set_affinity = ks_pcie_msi_set_affinity, 245 .irq_mask = ks_pcie_msi_mask, 246 .irq_unmask = ks_pcie_msi_unmask, 247}; 248 249static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp) 250{ 251 pp->msi_irq_chip = &ks_pcie_msi_irq_chip; 252 return dw_pcie_allocate_domains(pp); 253} 254 255static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, 256 int offset) 257{ 258 struct dw_pcie *pci = ks_pcie->pci; 259 struct device *dev = pci->dev; 260 u32 pending; 261 262 pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset)); 263 264 if (BIT(0) & pending) { 265 dev_dbg(dev, ": irq: irq_offset %d", offset); 266 generic_handle_domain_irq(ks_pcie->legacy_irq_domain, offset); 267 } 268 269 /* EOI the INTx interrupt */ 270 ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); 271} 272 273static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) 274{ 275 ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); 276} 277 278static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) 279{ 280 u32 reg; 281 struct device *dev = ks_pcie->pci->dev; 282 283 reg = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS); 284 if (!reg) 285 return IRQ_NONE; 286 287 if (reg & ERR_SYS) 288 dev_err(dev, "System Error\n"); 289 290 if (reg & ERR_FATAL) 291 dev_err(dev, "Fatal Error\n"); 292 293 if (reg & ERR_NONFATAL) 294 dev_dbg(dev, "Non Fatal Error\n"); 295 296 if (reg & ERR_CORR) 297 dev_dbg(dev, "Correctable Error\n"); 298 299 if (!ks_pcie->is_am6 && (reg & ERR_AXI)) 300 dev_err(dev, "AXI tag lookup fatal Error\n"); 301 302 if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER))) 303 dev_err(dev, "ECRC Error\n"); 304 305 ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg); 306 307 return IRQ_HANDLED; 308} 309 310static void ks_pcie_ack_legacy_irq(struct irq_data *d) 311{ 312} 313 314static void ks_pcie_mask_legacy_irq(struct irq_data *d) 315{ 316} 317 318static void ks_pcie_unmask_legacy_irq(struct irq_data *d) 319{ 320} 321 322static struct irq_chip ks_pcie_legacy_irq_chip = { 323 .name = "Keystone-PCI-Legacy-IRQ", 324 .irq_ack = ks_pcie_ack_legacy_irq, 325 .irq_mask = ks_pcie_mask_legacy_irq, 326 .irq_unmask = ks_pcie_unmask_legacy_irq, 327}; 328 329static int ks_pcie_init_legacy_irq_map(struct irq_domain *d, 330 unsigned int irq, 331 irq_hw_number_t hw_irq) 332{ 333 irq_set_chip_and_handler(irq, &ks_pcie_legacy_irq_chip, 334 handle_level_irq); 335 irq_set_chip_data(irq, d->host_data); 336 337 return 0; 338} 339 340static const struct irq_domain_ops ks_pcie_legacy_irq_domain_ops = { 341 .map = ks_pcie_init_legacy_irq_map, 342 .xlate = irq_domain_xlate_onetwocell, 343}; 344 345/** 346 * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask registers 347 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone 348 * PCIe host controller driver information. 349 * 350 * Since modification of dbi_cs2 involves different clock domain, read the 351 * status back to ensure the transition is complete. 352 */ 353static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) 354{ 355 u32 val; 356 357 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 358 val |= DBI_CS2; 359 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 360 361 do { 362 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 363 } while (!(val & DBI_CS2)); 364} 365 366/** 367 * ks_pcie_clear_dbi_mode() - Disable DBI mode 368 * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyStone 369 * PCIe host controller driver information. 370 * 371 * Since modification of dbi_cs2 involves different clock domain, read the 372 * status back to ensure the transition is complete. 373 */ 374static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) 375{ 376 u32 val; 377 378 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 379 val &= ~DBI_CS2; 380 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 381 382 do { 383 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 384 } while (val & DBI_CS2); 385} 386 387static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) 388{ 389 u32 val; 390 u32 num_viewport = ks_pcie->num_viewport; 391 struct dw_pcie *pci = ks_pcie->pci; 392 struct dw_pcie_rp *pp = &pci->pp; 393 u64 start, end; 394 struct resource *mem; 395 int i; 396 397 mem = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM)->res; 398 start = mem->start; 399 end = mem->end; 400 401 /* Disable BARs for inbound access */ 402 ks_pcie_set_dbi_mode(ks_pcie); 403 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); 404 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); 405 ks_pcie_clear_dbi_mode(ks_pcie); 406 407 if (ks_pcie->is_am6) 408 return; 409 410 val = ilog2(OB_WIN_SIZE); 411 ks_pcie_app_writel(ks_pcie, OB_SIZE, val); 412 413 /* Using Direct 1:1 mapping of RC <-> PCI memory space */ 414 for (i = 0; i < num_viewport && (start < end); i++) { 415 ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), 416 lower_32_bits(start) | OB_ENABLEN); 417 ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 418 upper_32_bits(start)); 419 start += OB_WIN_SIZE * SZ_1M; 420 } 421 422 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 423 val |= OB_XLAT_EN_VAL; 424 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 425} 426 427static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus, 428 unsigned int devfn, int where) 429{ 430 struct dw_pcie_rp *pp = bus->sysdata; 431 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 432 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 433 u32 reg; 434 435 reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | 436 CFG_FUNC(PCI_FUNC(devfn)); 437 if (!pci_is_root_bus(bus->parent)) 438 reg |= CFG_TYPE1; 439 ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); 440 441 return pp->va_cfg0_base + where; 442} 443 444static struct pci_ops ks_child_pcie_ops = { 445 .map_bus = ks_pcie_other_map_bus, 446 .read = pci_generic_config_read, 447 .write = pci_generic_config_write, 448}; 449 450/** 451 * ks_pcie_v3_65_add_bus() - keystone add_bus post initialization 452 * @bus: A pointer to the PCI bus structure. 453 * 454 * This sets BAR0 to enable inbound access for MSI_IRQ register 455 */ 456static int ks_pcie_v3_65_add_bus(struct pci_bus *bus) 457{ 458 struct dw_pcie_rp *pp = bus->sysdata; 459 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 460 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 461 462 if (!pci_is_root_bus(bus)) 463 return 0; 464 465 /* Configure and set up BAR0 */ 466 ks_pcie_set_dbi_mode(ks_pcie); 467 468 /* Enable BAR0 */ 469 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); 470 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); 471 472 ks_pcie_clear_dbi_mode(ks_pcie); 473 474 /* 475 * For BAR0, just setting bus address for inbound writes (MSI) should 476 * be sufficient. Use physical address to avoid any conflicts. 477 */ 478 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); 479 480 return 0; 481} 482 483static struct pci_ops ks_pcie_ops = { 484 .map_bus = dw_pcie_own_conf_map_bus, 485 .read = pci_generic_config_read, 486 .write = pci_generic_config_write, 487 .add_bus = ks_pcie_v3_65_add_bus, 488}; 489 490/** 491 * ks_pcie_link_up() - Check if link up 492 * @pci: A pointer to the dw_pcie structure which holds the DesignWare PCIe host 493 * controller driver information. 494 */ 495static int ks_pcie_link_up(struct dw_pcie *pci) 496{ 497 u32 val; 498 499 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); 500 val &= PORT_LOGIC_LTSSM_STATE_MASK; 501 return (val == PORT_LOGIC_LTSSM_STATE_L0); 502} 503 504static void ks_pcie_stop_link(struct dw_pcie *pci) 505{ 506 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 507 u32 val; 508 509 /* Disable Link training */ 510 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 511 val &= ~LTSSM_EN_VAL; 512 ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); 513} 514 515static int ks_pcie_start_link(struct dw_pcie *pci) 516{ 517 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 518 u32 val; 519 520 /* Initiate Link Training */ 521 val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); 522 ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); 523 524 return 0; 525} 526 527static void ks_pcie_quirk(struct pci_dev *dev) 528{ 529 struct pci_bus *bus = dev->bus; 530 struct pci_dev *bridge; 531 static const struct pci_device_id rc_pci_devids[] = { 532 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), 533 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 534 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E), 535 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 536 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L), 537 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 538 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G), 539 .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, 540 { 0, }, 541 }; 542 543 if (pci_is_root_bus(bus)) 544 bridge = dev; 545 546 /* look for the host bridge */ 547 while (!pci_is_root_bus(bus)) { 548 bridge = bus->self; 549 bus = bus->parent; 550 } 551 552 if (!bridge) 553 return; 554 555 /* 556 * Keystone PCI controller has a h/w limitation of 557 * 256 bytes maximum read request size. It can't handle 558 * anything higher than this. So force this limit on 559 * all downstream devices. 560 */ 561 if (pci_match_id(rc_pci_devids, bridge)) { 562 if (pcie_get_readrq(dev) > 256) { 563 dev_info(&dev->dev, "limiting MRRS to 256\n"); 564 pcie_set_readrq(dev, 256); 565 } 566 } 567} 568DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); 569 570static void ks_pcie_msi_irq_handler(struct irq_desc *desc) 571{ 572 unsigned int irq = desc->irq_data.hwirq; 573 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 574 u32 offset = irq - ks_pcie->msi_host_irq; 575 struct dw_pcie *pci = ks_pcie->pci; 576 struct dw_pcie_rp *pp = &pci->pp; 577 struct device *dev = pci->dev; 578 struct irq_chip *chip = irq_desc_get_chip(desc); 579 u32 vector, reg, pos; 580 581 dev_dbg(dev, "%s, irq %d\n", __func__, irq); 582 583 /* 584 * The chained irq handler installation would have replaced normal 585 * interrupt driver handler so we need to take care of mask/unmask and 586 * ack operation. 587 */ 588 chained_irq_enter(chip, desc); 589 590 reg = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); 591 /* 592 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit 593 * shows 1, 9, 17, 25 and so forth 594 */ 595 for (pos = 0; pos < 4; pos++) { 596 if (!(reg & BIT(pos))) 597 continue; 598 599 vector = offset + (pos << 3); 600 dev_dbg(dev, "irq: bit %d, vector %d\n", pos, vector); 601 generic_handle_domain_irq(pp->irq_domain, vector); 602 } 603 604 chained_irq_exit(chip, desc); 605} 606 607/** 608 * ks_pcie_legacy_irq_handler() - Handle legacy interrupt 609 * @desc: Pointer to irq descriptor 610 * 611 * Traverse through pending legacy interrupts and invoke handler for each. Also 612 * takes care of interrupt controller level mask/ack operation. 613 */ 614static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) 615{ 616 unsigned int irq = irq_desc_get_irq(desc); 617 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 618 struct dw_pcie *pci = ks_pcie->pci; 619 struct device *dev = pci->dev; 620 u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0]; 621 struct irq_chip *chip = irq_desc_get_chip(desc); 622 623 dev_dbg(dev, ": Handling legacy irq %d\n", irq); 624 625 /* 626 * The chained irq handler installation would have replaced normal 627 * interrupt driver handler so we need to take care of mask/unmask and 628 * ack operation. 629 */ 630 chained_irq_enter(chip, desc); 631 ks_pcie_handle_legacy_irq(ks_pcie, irq_offset); 632 chained_irq_exit(chip, desc); 633} 634 635static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) 636{ 637 struct device *dev = ks_pcie->pci->dev; 638 struct device_node *np = ks_pcie->np; 639 struct device_node *intc_np; 640 struct irq_data *irq_data; 641 int irq_count, irq, ret, i; 642 643 if (!IS_ENABLED(CONFIG_PCI_MSI)) 644 return 0; 645 646 intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); 647 if (!intc_np) { 648 if (ks_pcie->is_am6) 649 return 0; 650 dev_warn(dev, "msi-interrupt-controller node is absent\n"); 651 return -EINVAL; 652 } 653 654 irq_count = of_irq_count(intc_np); 655 if (!irq_count) { 656 dev_err(dev, "No IRQ entries in msi-interrupt-controller\n"); 657 ret = -EINVAL; 658 goto err; 659 } 660 661 for (i = 0; i < irq_count; i++) { 662 irq = irq_of_parse_and_map(intc_np, i); 663 if (!irq) { 664 ret = -EINVAL; 665 goto err; 666 } 667 668 if (!ks_pcie->msi_host_irq) { 669 irq_data = irq_get_irq_data(irq); 670 if (!irq_data) { 671 ret = -EINVAL; 672 goto err; 673 } 674 ks_pcie->msi_host_irq = irq_data->hwirq; 675 } 676 677 irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler, 678 ks_pcie); 679 } 680 681 of_node_put(intc_np); 682 return 0; 683 684err: 685 of_node_put(intc_np); 686 return ret; 687} 688 689static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) 690{ 691 struct device *dev = ks_pcie->pci->dev; 692 struct irq_domain *legacy_irq_domain; 693 struct device_node *np = ks_pcie->np; 694 struct device_node *intc_np; 695 int irq_count, irq, ret = 0, i; 696 697 intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); 698 if (!intc_np) { 699 /* 700 * Since legacy interrupts are modeled as edge-interrupts in 701 * AM6, keep it disabled for now. 702 */ 703 if (ks_pcie->is_am6) 704 return 0; 705 dev_warn(dev, "legacy-interrupt-controller node is absent\n"); 706 return -EINVAL; 707 } 708 709 irq_count = of_irq_count(intc_np); 710 if (!irq_count) { 711 dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n"); 712 ret = -EINVAL; 713 goto err; 714 } 715 716 for (i = 0; i < irq_count; i++) { 717 irq = irq_of_parse_and_map(intc_np, i); 718 if (!irq) { 719 ret = -EINVAL; 720 goto err; 721 } 722 ks_pcie->legacy_host_irqs[i] = irq; 723 724 irq_set_chained_handler_and_data(irq, 725 ks_pcie_legacy_irq_handler, 726 ks_pcie); 727 } 728 729 legacy_irq_domain = 730 irq_domain_add_linear(intc_np, PCI_NUM_INTX, 731 &ks_pcie_legacy_irq_domain_ops, NULL); 732 if (!legacy_irq_domain) { 733 dev_err(dev, "Failed to add irq domain for legacy irqs\n"); 734 ret = -EINVAL; 735 goto err; 736 } 737 ks_pcie->legacy_irq_domain = legacy_irq_domain; 738 739 for (i = 0; i < PCI_NUM_INTX; i++) 740 ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN); 741 742err: 743 of_node_put(intc_np); 744 return ret; 745} 746 747#ifdef CONFIG_ARM 748/* 749 * When a PCI device does not exist during config cycles, keystone host 750 * gets a bus error instead of returning 0xffffffff (PCI_ERROR_RESPONSE). 751 * This handler always returns 0 for this kind of fault. 752 */ 753static int ks_pcie_fault(unsigned long addr, unsigned int fsr, 754 struct pt_regs *regs) 755{ 756 unsigned long instr = *(unsigned long *) instruction_pointer(regs); 757 758 if ((instr & 0x0e100090) == 0x00100090) { 759 int reg = (instr >> 12) & 15; 760 761 regs->uregs[reg] = -1; 762 regs->ARM_pc += 4; 763 } 764 765 return 0; 766} 767#endif 768 769static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) 770{ 771 int ret; 772 unsigned int id; 773 struct regmap *devctrl_regs; 774 struct dw_pcie *pci = ks_pcie->pci; 775 struct device *dev = pci->dev; 776 struct device_node *np = dev->of_node; 777 struct of_phandle_args args; 778 unsigned int offset = 0; 779 780 devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id"); 781 if (IS_ERR(devctrl_regs)) 782 return PTR_ERR(devctrl_regs); 783 784 /* Do not error out to maintain old DT compatibility */ 785 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-id", 1, 0, &args); 786 if (!ret) 787 offset = args.args[0]; 788 789 ret = regmap_read(devctrl_regs, offset, &id); 790 if (ret) 791 return ret; 792 793 dw_pcie_dbi_ro_wr_en(pci); 794 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); 795 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); 796 dw_pcie_dbi_ro_wr_dis(pci); 797 798 return 0; 799} 800 801static int __init ks_pcie_host_init(struct dw_pcie_rp *pp) 802{ 803 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 804 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 805 int ret; 806 807 pp->bridge->ops = &ks_pcie_ops; 808 if (!ks_pcie->is_am6) 809 pp->bridge->child_ops = &ks_child_pcie_ops; 810 811 ret = ks_pcie_config_legacy_irq(ks_pcie); 812 if (ret) 813 return ret; 814 815 ret = ks_pcie_config_msi_irq(ks_pcie); 816 if (ret) 817 return ret; 818 819 ks_pcie_stop_link(pci); 820 ks_pcie_setup_rc_app_regs(ks_pcie); 821 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), 822 pci->dbi_base + PCI_IO_BASE); 823 824 ret = ks_pcie_init_id(ks_pcie); 825 if (ret < 0) 826 return ret; 827 828#ifdef CONFIG_ARM 829 /* 830 * PCIe access errors that result into OCP errors are caught by ARM as 831 * "External aborts" 832 */ 833 hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, 834 "Asynchronous external abort"); 835#endif 836 837 return 0; 838} 839 840static const struct dw_pcie_host_ops ks_pcie_host_ops = { 841 .host_init = ks_pcie_host_init, 842 .msi_host_init = ks_pcie_msi_host_init, 843}; 844 845static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { 846 .host_init = ks_pcie_host_init, 847}; 848 849static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) 850{ 851 struct keystone_pcie *ks_pcie = priv; 852 853 return ks_pcie_handle_error_irq(ks_pcie); 854} 855 856static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, 857 u32 reg, size_t size, u32 val) 858{ 859 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 860 861 ks_pcie_set_dbi_mode(ks_pcie); 862 dw_pcie_write(base + reg, size, val); 863 ks_pcie_clear_dbi_mode(ks_pcie); 864} 865 866static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { 867 .start_link = ks_pcie_start_link, 868 .stop_link = ks_pcie_stop_link, 869 .link_up = ks_pcie_link_up, 870 .write_dbi2 = ks_pcie_am654_write_dbi2, 871}; 872 873static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep) 874{ 875 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 876 int flags; 877 878 ep->page_size = AM654_WIN_SIZE; 879 flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32; 880 dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); 881 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags); 882} 883 884static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie) 885{ 886 struct dw_pcie *pci = ks_pcie->pci; 887 u8 int_pin; 888 889 int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN); 890 if (int_pin == 0 || int_pin > 4) 891 return; 892 893 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin), 894 INT_ENABLE); 895 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE); 896 mdelay(1); 897 ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE); 898 ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin), 899 INT_ENABLE); 900} 901 902static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 903 enum pci_epc_irq_type type, 904 u16 interrupt_num) 905{ 906 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 907 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); 908 909 switch (type) { 910 case PCI_EPC_IRQ_LEGACY: 911 ks_pcie_am654_raise_legacy_irq(ks_pcie); 912 break; 913 case PCI_EPC_IRQ_MSI: 914 dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 915 break; 916 case PCI_EPC_IRQ_MSIX: 917 dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); 918 break; 919 default: 920 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 921 return -EINVAL; 922 } 923 924 return 0; 925} 926 927static const struct pci_epc_features ks_pcie_am654_epc_features = { 928 .linkup_notifier = false, 929 .msi_capable = true, 930 .msix_capable = true, 931 .reserved_bar = 1 << BAR_0 | 1 << BAR_1, 932 .bar_fixed_64bit = 1 << BAR_0, 933 .bar_fixed_size[2] = SZ_1M, 934 .bar_fixed_size[3] = SZ_64K, 935 .bar_fixed_size[4] = 256, 936 .bar_fixed_size[5] = SZ_1M, 937 .align = SZ_1M, 938}; 939 940static const struct pci_epc_features* 941ks_pcie_am654_get_features(struct dw_pcie_ep *ep) 942{ 943 return &ks_pcie_am654_epc_features; 944} 945 946static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = { 947 .ep_init = ks_pcie_am654_ep_init, 948 .raise_irq = ks_pcie_am654_raise_irq, 949 .get_features = &ks_pcie_am654_get_features, 950}; 951 952static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) 953{ 954 int num_lanes = ks_pcie->num_lanes; 955 956 while (num_lanes--) { 957 phy_power_off(ks_pcie->phy[num_lanes]); 958 phy_exit(ks_pcie->phy[num_lanes]); 959 } 960} 961 962static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) 963{ 964 int i; 965 int ret; 966 int num_lanes = ks_pcie->num_lanes; 967 968 for (i = 0; i < num_lanes; i++) { 969 ret = phy_reset(ks_pcie->phy[i]); 970 if (ret < 0) 971 goto err_phy; 972 973 ret = phy_init(ks_pcie->phy[i]); 974 if (ret < 0) 975 goto err_phy; 976 977 ret = phy_power_on(ks_pcie->phy[i]); 978 if (ret < 0) { 979 phy_exit(ks_pcie->phy[i]); 980 goto err_phy; 981 } 982 } 983 984 return 0; 985 986err_phy: 987 while (--i >= 0) { 988 phy_power_off(ks_pcie->phy[i]); 989 phy_exit(ks_pcie->phy[i]); 990 } 991 992 return ret; 993} 994 995static int ks_pcie_set_mode(struct device *dev) 996{ 997 struct device_node *np = dev->of_node; 998 struct of_phandle_args args; 999 unsigned int offset = 0; 1000 struct regmap *syscon; 1001 u32 val; 1002 u32 mask; 1003 int ret = 0; 1004 1005 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 1006 if (IS_ERR(syscon)) 1007 return 0; 1008 1009 /* Do not error out to maintain old DT compatibility */ 1010 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); 1011 if (!ret) 1012 offset = args.args[0]; 1013 1014 mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN; 1015 val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; 1016 1017 ret = regmap_update_bits(syscon, offset, mask, val); 1018 if (ret) { 1019 dev_err(dev, "failed to set pcie mode\n"); 1020 return ret; 1021 } 1022 1023 return 0; 1024} 1025 1026static int ks_pcie_am654_set_mode(struct device *dev, 1027 enum dw_pcie_device_mode mode) 1028{ 1029 struct device_node *np = dev->of_node; 1030 struct of_phandle_args args; 1031 unsigned int offset = 0; 1032 struct regmap *syscon; 1033 u32 val; 1034 u32 mask; 1035 int ret = 0; 1036 1037 syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); 1038 if (IS_ERR(syscon)) 1039 return 0; 1040 1041 /* Do not error out to maintain old DT compatibility */ 1042 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-pcie-mode", 1, 0, &args); 1043 if (!ret) 1044 offset = args.args[0]; 1045 1046 mask = AM654_PCIE_DEV_TYPE_MASK; 1047 1048 switch (mode) { 1049 case DW_PCIE_RC_TYPE: 1050 val = RC; 1051 break; 1052 case DW_PCIE_EP_TYPE: 1053 val = EP; 1054 break; 1055 default: 1056 dev_err(dev, "INVALID device type %d\n", mode); 1057 return -EINVAL; 1058 } 1059 1060 ret = regmap_update_bits(syscon, offset, mask, val); 1061 if (ret) { 1062 dev_err(dev, "failed to set pcie mode\n"); 1063 return ret; 1064 } 1065 1066 return 0; 1067} 1068 1069static const struct ks_pcie_of_data ks_pcie_rc_of_data = { 1070 .host_ops = &ks_pcie_host_ops, 1071 .version = DW_PCIE_VER_365A, 1072}; 1073 1074static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { 1075 .host_ops = &ks_pcie_am654_host_ops, 1076 .mode = DW_PCIE_RC_TYPE, 1077 .version = DW_PCIE_VER_490A, 1078}; 1079 1080static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = { 1081 .ep_ops = &ks_pcie_am654_ep_ops, 1082 .mode = DW_PCIE_EP_TYPE, 1083 .version = DW_PCIE_VER_490A, 1084}; 1085 1086static const struct of_device_id ks_pcie_of_match[] = { 1087 { 1088 .type = "pci", 1089 .data = &ks_pcie_rc_of_data, 1090 .compatible = "ti,keystone-pcie", 1091 }, 1092 { 1093 .data = &ks_pcie_am654_rc_of_data, 1094 .compatible = "ti,am654-pcie-rc", 1095 }, 1096 { 1097 .data = &ks_pcie_am654_ep_of_data, 1098 .compatible = "ti,am654-pcie-ep", 1099 }, 1100 { }, 1101}; 1102 1103static int ks_pcie_probe(struct platform_device *pdev) 1104{ 1105 const struct dw_pcie_host_ops *host_ops; 1106 const struct dw_pcie_ep_ops *ep_ops; 1107 struct device *dev = &pdev->dev; 1108 struct device_node *np = dev->of_node; 1109 const struct ks_pcie_of_data *data; 1110 enum dw_pcie_device_mode mode; 1111 struct dw_pcie *pci; 1112 struct keystone_pcie *ks_pcie; 1113 struct device_link **link; 1114 struct gpio_desc *gpiod; 1115 struct resource *res; 1116 void __iomem *base; 1117 u32 num_viewport; 1118 struct phy **phy; 1119 u32 num_lanes; 1120 char name[10]; 1121 u32 version; 1122 int ret; 1123 int irq; 1124 int i; 1125 1126 data = of_device_get_match_data(dev); 1127 if (!data) 1128 return -EINVAL; 1129 1130 version = data->version; 1131 host_ops = data->host_ops; 1132 ep_ops = data->ep_ops; 1133 mode = data->mode; 1134 1135 ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); 1136 if (!ks_pcie) 1137 return -ENOMEM; 1138 1139 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1140 if (!pci) 1141 return -ENOMEM; 1142 1143 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); 1144 ks_pcie->va_app_base = devm_ioremap_resource(dev, res); 1145 if (IS_ERR(ks_pcie->va_app_base)) 1146 return PTR_ERR(ks_pcie->va_app_base); 1147 1148 ks_pcie->app = *res; 1149 1150 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); 1151 base = devm_pci_remap_cfg_resource(dev, res); 1152 if (IS_ERR(base)) 1153 return PTR_ERR(base); 1154 1155 if (of_device_is_compatible(np, "ti,am654-pcie-rc")) 1156 ks_pcie->is_am6 = true; 1157 1158 pci->dbi_base = base; 1159 pci->dbi_base2 = base; 1160 pci->dev = dev; 1161 pci->ops = &ks_pcie_dw_pcie_ops; 1162 pci->version = version; 1163 1164 irq = platform_get_irq(pdev, 0); 1165 if (irq < 0) 1166 return irq; 1167 1168 ret = request_irq(irq, ks_pcie_err_irq_handler, IRQF_SHARED, 1169 "ks-pcie-error-irq", ks_pcie); 1170 if (ret < 0) { 1171 dev_err(dev, "failed to request error IRQ %d\n", 1172 irq); 1173 return ret; 1174 } 1175 1176 ret = of_property_read_u32(np, "num-lanes", &num_lanes); 1177 if (ret) 1178 num_lanes = 1; 1179 1180 phy = devm_kzalloc(dev, sizeof(*phy) * num_lanes, GFP_KERNEL); 1181 if (!phy) 1182 return -ENOMEM; 1183 1184 link = devm_kzalloc(dev, sizeof(*link) * num_lanes, GFP_KERNEL); 1185 if (!link) 1186 return -ENOMEM; 1187 1188 for (i = 0; i < num_lanes; i++) { 1189 snprintf(name, sizeof(name), "pcie-phy%d", i); 1190 phy[i] = devm_phy_optional_get(dev, name); 1191 if (IS_ERR(phy[i])) { 1192 ret = PTR_ERR(phy[i]); 1193 goto err_link; 1194 } 1195 1196 if (!phy[i]) 1197 continue; 1198 1199 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); 1200 if (!link[i]) { 1201 ret = -EINVAL; 1202 goto err_link; 1203 } 1204 } 1205 1206 ks_pcie->np = np; 1207 ks_pcie->pci = pci; 1208 ks_pcie->link = link; 1209 ks_pcie->num_lanes = num_lanes; 1210 ks_pcie->phy = phy; 1211 1212 gpiod = devm_gpiod_get_optional(dev, "reset", 1213 GPIOD_OUT_LOW); 1214 if (IS_ERR(gpiod)) { 1215 ret = PTR_ERR(gpiod); 1216 if (ret != -EPROBE_DEFER) 1217 dev_err(dev, "Failed to get reset GPIO\n"); 1218 goto err_link; 1219 } 1220 1221 /* Obtain references to the PHYs */ 1222 for (i = 0; i < num_lanes; i++) 1223 phy_pm_runtime_get_sync(ks_pcie->phy[i]); 1224 1225 ret = ks_pcie_enable_phy(ks_pcie); 1226 1227 /* Release references to the PHYs */ 1228 for (i = 0; i < num_lanes; i++) 1229 phy_pm_runtime_put_sync(ks_pcie->phy[i]); 1230 1231 if (ret) { 1232 dev_err(dev, "failed to enable phy\n"); 1233 goto err_link; 1234 } 1235 1236 platform_set_drvdata(pdev, ks_pcie); 1237 pm_runtime_enable(dev); 1238 ret = pm_runtime_get_sync(dev); 1239 if (ret < 0) { 1240 dev_err(dev, "pm_runtime_get_sync failed\n"); 1241 goto err_get_sync; 1242 } 1243 1244 if (dw_pcie_ver_is_ge(pci, 480A)) 1245 ret = ks_pcie_am654_set_mode(dev, mode); 1246 else 1247 ret = ks_pcie_set_mode(dev); 1248 if (ret < 0) 1249 goto err_get_sync; 1250 1251 switch (mode) { 1252 case DW_PCIE_RC_TYPE: 1253 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { 1254 ret = -ENODEV; 1255 goto err_get_sync; 1256 } 1257 1258 ret = of_property_read_u32(np, "num-viewport", &num_viewport); 1259 if (ret < 0) { 1260 dev_err(dev, "unable to read *num-viewport* property\n"); 1261 goto err_get_sync; 1262 } 1263 1264 /* 1265 * "Power Sequencing and Reset Signal Timings" table in 1266 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 1267 * indicates PERST# should be deasserted after minimum of 100us 1268 * once REFCLK is stable. The REFCLK to the connector in RC 1269 * mode is selected while enabling the PHY. So deassert PERST# 1270 * after 100 us. 1271 */ 1272 if (gpiod) { 1273 usleep_range(100, 200); 1274 gpiod_set_value_cansleep(gpiod, 1); 1275 } 1276 1277 ks_pcie->num_viewport = num_viewport; 1278 pci->pp.ops = host_ops; 1279 ret = dw_pcie_host_init(&pci->pp); 1280 if (ret < 0) 1281 goto err_get_sync; 1282 break; 1283 case DW_PCIE_EP_TYPE: 1284 if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) { 1285 ret = -ENODEV; 1286 goto err_get_sync; 1287 } 1288 1289 pci->ep.ops = ep_ops; 1290 ret = dw_pcie_ep_init(&pci->ep); 1291 if (ret < 0) 1292 goto err_get_sync; 1293 break; 1294 default: 1295 dev_err(dev, "INVALID device type %d\n", mode); 1296 } 1297 1298 ks_pcie_enable_error_irq(ks_pcie); 1299 1300 return 0; 1301 1302err_get_sync: 1303 pm_runtime_put(dev); 1304 pm_runtime_disable(dev); 1305 ks_pcie_disable_phy(ks_pcie); 1306 1307err_link: 1308 while (--i >= 0 && link[i]) 1309 device_link_del(link[i]); 1310 1311 return ret; 1312} 1313 1314static int ks_pcie_remove(struct platform_device *pdev) 1315{ 1316 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); 1317 struct device_link **link = ks_pcie->link; 1318 int num_lanes = ks_pcie->num_lanes; 1319 struct device *dev = &pdev->dev; 1320 1321 pm_runtime_put(dev); 1322 pm_runtime_disable(dev); 1323 ks_pcie_disable_phy(ks_pcie); 1324 while (num_lanes--) 1325 device_link_del(link[num_lanes]); 1326 1327 return 0; 1328} 1329 1330static struct platform_driver ks_pcie_driver = { 1331 .probe = ks_pcie_probe, 1332 .remove = ks_pcie_remove, 1333 .driver = { 1334 .name = "keystone-pcie", 1335 .of_match_table = ks_pcie_of_match, 1336 }, 1337}; 1338builtin_platform_driver(ks_pcie_driver); 1339