162306a36Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0 262306a36Sopenharmony_ci# 362306a36Sopenharmony_ci# PCI configuration 462306a36Sopenharmony_ci# 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci# select this to offer the PCI prompt 762306a36Sopenharmony_ciconfig HAVE_PCI 862306a36Sopenharmony_ci bool 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci# select this to unconditionally force on PCI support 1162306a36Sopenharmony_ciconfig FORCE_PCI 1262306a36Sopenharmony_ci bool 1362306a36Sopenharmony_ci select HAVE_PCI 1462306a36Sopenharmony_ci select PCI 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_cimenuconfig PCI 1762306a36Sopenharmony_ci bool "PCI support" 1862306a36Sopenharmony_ci depends on HAVE_PCI 1962306a36Sopenharmony_ci help 2062306a36Sopenharmony_ci This option enables support for the PCI local bus, including 2162306a36Sopenharmony_ci support for PCI-X and the foundations for PCI Express support. 2262306a36Sopenharmony_ci Say 'Y' here unless you know what you are doing. 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ciif PCI 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ciconfig PCI_DOMAINS 2762306a36Sopenharmony_ci bool 2862306a36Sopenharmony_ci depends on PCI 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ciconfig PCI_DOMAINS_GENERIC 3162306a36Sopenharmony_ci bool 3262306a36Sopenharmony_ci select PCI_DOMAINS 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ciconfig PCI_SYSCALL 3562306a36Sopenharmony_ci bool 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_cisource "drivers/pci/pcie/Kconfig" 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ciconfig PCI_MSI 4062306a36Sopenharmony_ci bool "Message Signaled Interrupts (MSI and MSI-X)" 4162306a36Sopenharmony_ci select GENERIC_MSI_IRQ 4262306a36Sopenharmony_ci help 4362306a36Sopenharmony_ci This allows device drivers to enable MSI (Message Signaled 4462306a36Sopenharmony_ci Interrupts). Message Signaled Interrupts enable a device to 4562306a36Sopenharmony_ci generate an interrupt using an inbound Memory Write on its 4662306a36Sopenharmony_ci PCI bus instead of asserting a device IRQ pin. 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_ci Use of PCI MSI interrupts can be disabled at kernel boot time 4962306a36Sopenharmony_ci by using the 'pci=nomsi' option. This disables MSI for the 5062306a36Sopenharmony_ci entire system. 5162306a36Sopenharmony_ci 5262306a36Sopenharmony_ci If you don't know what to do here, say Y. 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ciconfig PCI_MSI_ARCH_FALLBACKS 5562306a36Sopenharmony_ci bool 5662306a36Sopenharmony_ci 5762306a36Sopenharmony_ciconfig PCI_QUIRKS 5862306a36Sopenharmony_ci default y 5962306a36Sopenharmony_ci bool "Enable PCI quirk workarounds" if EXPERT 6062306a36Sopenharmony_ci help 6162306a36Sopenharmony_ci This enables workarounds for various PCI chipset bugs/quirks. 6262306a36Sopenharmony_ci Disable this only if your target machine is unaffected by PCI 6362306a36Sopenharmony_ci quirks. 6462306a36Sopenharmony_ci 6562306a36Sopenharmony_ciconfig PCI_DEBUG 6662306a36Sopenharmony_ci bool "PCI Debugging" 6762306a36Sopenharmony_ci depends on DEBUG_KERNEL 6862306a36Sopenharmony_ci help 6962306a36Sopenharmony_ci Say Y here if you want the PCI core to produce a bunch of debug 7062306a36Sopenharmony_ci messages to the system log. Select this if you are having a 7162306a36Sopenharmony_ci problem with PCI support and want to see more of what is going on. 7262306a36Sopenharmony_ci 7362306a36Sopenharmony_ci When in doubt, say N. 7462306a36Sopenharmony_ci 7562306a36Sopenharmony_ciconfig PCI_REALLOC_ENABLE_AUTO 7662306a36Sopenharmony_ci bool "Enable PCI resource re-allocation detection" 7762306a36Sopenharmony_ci depends on PCI_IOV 7862306a36Sopenharmony_ci help 7962306a36Sopenharmony_ci Say Y here if you want the PCI core to detect if PCI resource 8062306a36Sopenharmony_ci re-allocation needs to be enabled. You can always use pci=realloc=on 8162306a36Sopenharmony_ci or pci=realloc=off to override it. It will automatically 8262306a36Sopenharmony_ci re-allocate PCI resources if SR-IOV BARs have not been allocated by 8362306a36Sopenharmony_ci the BIOS. 8462306a36Sopenharmony_ci 8562306a36Sopenharmony_ci When in doubt, say N. 8662306a36Sopenharmony_ci 8762306a36Sopenharmony_ciconfig PCI_STUB 8862306a36Sopenharmony_ci tristate "PCI Stub driver" 8962306a36Sopenharmony_ci help 9062306a36Sopenharmony_ci Say Y or M here if you want be able to reserve a PCI device 9162306a36Sopenharmony_ci when it is going to be assigned to a guest operating system. 9262306a36Sopenharmony_ci 9362306a36Sopenharmony_ci When in doubt, say N. 9462306a36Sopenharmony_ci 9562306a36Sopenharmony_ciconfig PCI_PF_STUB 9662306a36Sopenharmony_ci tristate "PCI PF Stub driver" 9762306a36Sopenharmony_ci depends on PCI_IOV 9862306a36Sopenharmony_ci help 9962306a36Sopenharmony_ci Say Y or M here if you want to enable support for devices that 10062306a36Sopenharmony_ci require SR-IOV support, while at the same time the PF (Physical 10162306a36Sopenharmony_ci Function) itself is not providing any actual services on the 10262306a36Sopenharmony_ci host itself such as storage or networking. 10362306a36Sopenharmony_ci 10462306a36Sopenharmony_ci When in doubt, say N. 10562306a36Sopenharmony_ci 10662306a36Sopenharmony_ciconfig XEN_PCIDEV_FRONTEND 10762306a36Sopenharmony_ci tristate "Xen PCI Frontend" 10862306a36Sopenharmony_ci depends on XEN_PV 10962306a36Sopenharmony_ci select PCI_XEN 11062306a36Sopenharmony_ci select XEN_XENBUS_FRONTEND 11162306a36Sopenharmony_ci default y 11262306a36Sopenharmony_ci help 11362306a36Sopenharmony_ci The PCI device frontend driver allows the kernel to import arbitrary 11462306a36Sopenharmony_ci PCI devices from a PCI backend to support PCI driver domains. 11562306a36Sopenharmony_ci 11662306a36Sopenharmony_ciconfig PCI_ATS 11762306a36Sopenharmony_ci bool 11862306a36Sopenharmony_ci 11962306a36Sopenharmony_ciconfig PCI_DOE 12062306a36Sopenharmony_ci bool 12162306a36Sopenharmony_ci 12262306a36Sopenharmony_ciconfig PCI_ECAM 12362306a36Sopenharmony_ci bool 12462306a36Sopenharmony_ci 12562306a36Sopenharmony_ciconfig PCI_LOCKLESS_CONFIG 12662306a36Sopenharmony_ci bool 12762306a36Sopenharmony_ci 12862306a36Sopenharmony_ciconfig PCI_BRIDGE_EMUL 12962306a36Sopenharmony_ci bool 13062306a36Sopenharmony_ci 13162306a36Sopenharmony_ciconfig PCI_IOV 13262306a36Sopenharmony_ci bool "PCI IOV support" 13362306a36Sopenharmony_ci select PCI_ATS 13462306a36Sopenharmony_ci help 13562306a36Sopenharmony_ci I/O Virtualization is a PCI feature supported by some devices 13662306a36Sopenharmony_ci which allows them to create virtual devices which share their 13762306a36Sopenharmony_ci physical resources. 13862306a36Sopenharmony_ci 13962306a36Sopenharmony_ci If unsure, say N. 14062306a36Sopenharmony_ci 14162306a36Sopenharmony_ciconfig PCI_PRI 14262306a36Sopenharmony_ci bool "PCI PRI support" 14362306a36Sopenharmony_ci select PCI_ATS 14462306a36Sopenharmony_ci help 14562306a36Sopenharmony_ci PRI is the PCI Page Request Interface. It allows PCI devices that are 14662306a36Sopenharmony_ci behind an IOMMU to recover from page faults. 14762306a36Sopenharmony_ci 14862306a36Sopenharmony_ci If unsure, say N. 14962306a36Sopenharmony_ci 15062306a36Sopenharmony_ciconfig PCI_PASID 15162306a36Sopenharmony_ci bool "PCI PASID support" 15262306a36Sopenharmony_ci select PCI_ATS 15362306a36Sopenharmony_ci help 15462306a36Sopenharmony_ci Process Address Space Identifiers (PASIDs) can be used by PCI devices 15562306a36Sopenharmony_ci to access more than one IO address space at the same time. To make 15662306a36Sopenharmony_ci use of this feature an IOMMU is required which also supports PASIDs. 15762306a36Sopenharmony_ci Select this option if you have such an IOMMU and want to compile the 15862306a36Sopenharmony_ci driver for it into your kernel. 15962306a36Sopenharmony_ci 16062306a36Sopenharmony_ci If unsure, say N. 16162306a36Sopenharmony_ci 16262306a36Sopenharmony_ciconfig PCI_P2PDMA 16362306a36Sopenharmony_ci bool "PCI peer-to-peer transfer support" 16462306a36Sopenharmony_ci depends on ZONE_DEVICE 16562306a36Sopenharmony_ci # 16662306a36Sopenharmony_ci # The need for the scatterlist DMA bus address flag means PCI P2PDMA 16762306a36Sopenharmony_ci # requires 64bit 16862306a36Sopenharmony_ci # 16962306a36Sopenharmony_ci depends on 64BIT 17062306a36Sopenharmony_ci select GENERIC_ALLOCATOR 17162306a36Sopenharmony_ci select NEED_SG_DMA_FLAGS 17262306a36Sopenharmony_ci help 17362306a36Sopenharmony_ci Enableѕ drivers to do PCI peer-to-peer transactions to and from 17462306a36Sopenharmony_ci BARs that are exposed in other devices that are the part of 17562306a36Sopenharmony_ci the hierarchy where peer-to-peer DMA is guaranteed by the PCI 17662306a36Sopenharmony_ci specification to work (ie. anything below a single PCI bridge). 17762306a36Sopenharmony_ci 17862306a36Sopenharmony_ci Many PCIe root complexes do not support P2P transactions and 17962306a36Sopenharmony_ci it's hard to tell which support it at all, so at this time, 18062306a36Sopenharmony_ci P2P DMA transactions must be between devices behind the same root 18162306a36Sopenharmony_ci port. 18262306a36Sopenharmony_ci 18362306a36Sopenharmony_ci If unsure, say N. 18462306a36Sopenharmony_ci 18562306a36Sopenharmony_ciconfig PCI_LABEL 18662306a36Sopenharmony_ci def_bool y if (DMI || ACPI) 18762306a36Sopenharmony_ci select NLS 18862306a36Sopenharmony_ci 18962306a36Sopenharmony_ciconfig PCI_HYPERV 19062306a36Sopenharmony_ci tristate "Hyper-V PCI Frontend" 19162306a36Sopenharmony_ci depends on ((X86 && X86_64) || ARM64) && HYPERV && PCI_MSI && SYSFS 19262306a36Sopenharmony_ci select PCI_HYPERV_INTERFACE 19362306a36Sopenharmony_ci help 19462306a36Sopenharmony_ci The PCI device frontend driver allows the kernel to import arbitrary 19562306a36Sopenharmony_ci PCI devices from a PCI backend to support PCI driver domains. 19662306a36Sopenharmony_ci 19762306a36Sopenharmony_ciconfig PCI_DYNAMIC_OF_NODES 19862306a36Sopenharmony_ci bool "Create Device tree nodes for PCI devices" 19962306a36Sopenharmony_ci depends on OF_IRQ 20062306a36Sopenharmony_ci select OF_DYNAMIC 20162306a36Sopenharmony_ci help 20262306a36Sopenharmony_ci This option enables support for generating device tree nodes for some 20362306a36Sopenharmony_ci PCI devices. Thus, the driver of this kind can load and overlay 20462306a36Sopenharmony_ci flattened device tree for its downstream devices. 20562306a36Sopenharmony_ci 20662306a36Sopenharmony_ci Once this option is selected, the device tree nodes will be generated 20762306a36Sopenharmony_ci for all PCI bridges. 20862306a36Sopenharmony_ci 20962306a36Sopenharmony_cichoice 21062306a36Sopenharmony_ci prompt "PCI Express hierarchy optimization setting" 21162306a36Sopenharmony_ci default PCIE_BUS_DEFAULT 21262306a36Sopenharmony_ci depends on PCI && EXPERT 21362306a36Sopenharmony_ci help 21462306a36Sopenharmony_ci MPS (Max Payload Size) and MRRS (Max Read Request Size) are PCIe 21562306a36Sopenharmony_ci device parameters that affect performance and the ability to 21662306a36Sopenharmony_ci support hotplug and peer-to-peer DMA. 21762306a36Sopenharmony_ci 21862306a36Sopenharmony_ci The following choices set the MPS and MRRS optimization strategy 21962306a36Sopenharmony_ci at compile-time. The choices are the same as those offered for 22062306a36Sopenharmony_ci the kernel command-line parameter 'pci', i.e., 22162306a36Sopenharmony_ci 'pci=pcie_bus_tune_off', 'pci=pcie_bus_safe', 22262306a36Sopenharmony_ci 'pci=pcie_bus_perf', and 'pci=pcie_bus_peer2peer'. 22362306a36Sopenharmony_ci 22462306a36Sopenharmony_ci This is a compile-time setting and can be overridden by the above 22562306a36Sopenharmony_ci command-line parameters. If unsure, choose PCIE_BUS_DEFAULT. 22662306a36Sopenharmony_ci 22762306a36Sopenharmony_ciconfig PCIE_BUS_TUNE_OFF 22862306a36Sopenharmony_ci bool "Tune Off" 22962306a36Sopenharmony_ci depends on PCI 23062306a36Sopenharmony_ci help 23162306a36Sopenharmony_ci Use the BIOS defaults; don't touch MPS at all. This is the same 23262306a36Sopenharmony_ci as booting with 'pci=pcie_bus_tune_off'. 23362306a36Sopenharmony_ci 23462306a36Sopenharmony_ciconfig PCIE_BUS_DEFAULT 23562306a36Sopenharmony_ci bool "Default" 23662306a36Sopenharmony_ci depends on PCI 23762306a36Sopenharmony_ci help 23862306a36Sopenharmony_ci Default choice; ensure that the MPS matches upstream bridge. 23962306a36Sopenharmony_ci 24062306a36Sopenharmony_ciconfig PCIE_BUS_SAFE 24162306a36Sopenharmony_ci bool "Safe" 24262306a36Sopenharmony_ci depends on PCI 24362306a36Sopenharmony_ci help 24462306a36Sopenharmony_ci Use largest MPS that boot-time devices support. If you have a 24562306a36Sopenharmony_ci closed system with no possibility of adding new devices, this 24662306a36Sopenharmony_ci will use the largest MPS that's supported by all devices. This 24762306a36Sopenharmony_ci is the same as booting with 'pci=pcie_bus_safe'. 24862306a36Sopenharmony_ci 24962306a36Sopenharmony_ciconfig PCIE_BUS_PERFORMANCE 25062306a36Sopenharmony_ci bool "Performance" 25162306a36Sopenharmony_ci depends on PCI 25262306a36Sopenharmony_ci help 25362306a36Sopenharmony_ci Use MPS and MRRS for best performance. Ensure that a given 25462306a36Sopenharmony_ci device's MPS is no larger than its parent MPS, which allows us to 25562306a36Sopenharmony_ci keep all switches/bridges to the max MPS supported by their 25662306a36Sopenharmony_ci parent. This is the same as booting with 'pci=pcie_bus_perf'. 25762306a36Sopenharmony_ci 25862306a36Sopenharmony_ciconfig PCIE_BUS_PEER2PEER 25962306a36Sopenharmony_ci bool "Peer2peer" 26062306a36Sopenharmony_ci depends on PCI 26162306a36Sopenharmony_ci help 26262306a36Sopenharmony_ci Set MPS = 128 for all devices. MPS configuration effected by the 26362306a36Sopenharmony_ci other options could cause the MPS on one root port to be 26462306a36Sopenharmony_ci different than that of the MPS on another, which may cause 26562306a36Sopenharmony_ci hot-added devices or peer-to-peer DMA to fail. Set MPS to the 26662306a36Sopenharmony_ci smallest possible value (128B) system-wide to avoid these issues. 26762306a36Sopenharmony_ci This is the same as booting with 'pci=pcie_bus_peer2peer'. 26862306a36Sopenharmony_ci 26962306a36Sopenharmony_ciendchoice 27062306a36Sopenharmony_ci 27162306a36Sopenharmony_ciconfig VGA_ARB 27262306a36Sopenharmony_ci bool "VGA Arbitration" if EXPERT 27362306a36Sopenharmony_ci default y 27462306a36Sopenharmony_ci depends on (PCI && !S390) 27562306a36Sopenharmony_ci help 27662306a36Sopenharmony_ci Some "legacy" VGA devices implemented on PCI typically have the same 27762306a36Sopenharmony_ci hard-decoded addresses as they did on ISA. When multiple PCI devices 27862306a36Sopenharmony_ci are accessed at same time they need some kind of coordination. Please 27962306a36Sopenharmony_ci see Documentation/gpu/vgaarbiter.rst for more details. Select this to 28062306a36Sopenharmony_ci enable VGA arbiter. 28162306a36Sopenharmony_ci 28262306a36Sopenharmony_ciconfig VGA_ARB_MAX_GPUS 28362306a36Sopenharmony_ci int "Maximum number of GPUs" 28462306a36Sopenharmony_ci default 16 28562306a36Sopenharmony_ci depends on VGA_ARB 28662306a36Sopenharmony_ci help 28762306a36Sopenharmony_ci Reserves space in the kernel to maintain resource locking for 28862306a36Sopenharmony_ci multiple GPUS. The overhead for each GPU is very small. 28962306a36Sopenharmony_ci 29062306a36Sopenharmony_cisource "drivers/pci/hotplug/Kconfig" 29162306a36Sopenharmony_cisource "drivers/pci/controller/Kconfig" 29262306a36Sopenharmony_cisource "drivers/pci/endpoint/Kconfig" 29362306a36Sopenharmony_cisource "drivers/pci/switch/Kconfig" 29462306a36Sopenharmony_ci 29562306a36Sopenharmony_ciendif 296