1// SPDX-License-Identifier: GPL-2.0
2/*
3 * STM32 Factory-programmed memory read access driver
4 *
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com> for STMicroelectronics.
7 */
8
9#include <linux/arm-smccc.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/nvmem-provider.h>
13#include <linux/of_device.h>
14#include <linux/tee_drv.h>
15
16#include "stm32-bsec-optee-ta.h"
17
18/* BSEC secure service access from non-secure */
19#define STM32_SMC_BSEC			0x82001003
20#define STM32_SMC_READ_SHADOW		0x01
21#define STM32_SMC_PROG_OTP		0x02
22#define STM32_SMC_WRITE_SHADOW		0x03
23#define STM32_SMC_READ_OTP		0x04
24
25/* shadow registers offset */
26#define STM32MP15_BSEC_DATA0		0x200
27
28struct stm32_romem_cfg {
29	int size;
30	u8 lower;
31	bool ta;
32};
33
34struct stm32_romem_priv {
35	void __iomem *base;
36	struct nvmem_config cfg;
37	u8 lower;
38	struct tee_context *ctx;
39};
40
41static int stm32_romem_read(void *context, unsigned int offset, void *buf,
42			    size_t bytes)
43{
44	struct stm32_romem_priv *priv = context;
45	u8 *buf8 = buf;
46	int i;
47
48	for (i = offset; i < offset + bytes; i++)
49		*buf8++ = readb_relaxed(priv->base + i);
50
51	return 0;
52}
53
54static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result)
55{
56#if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC)
57	struct arm_smccc_res res;
58
59	arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res);
60	if (res.a0)
61		return -EIO;
62
63	if (result)
64		*result = (u32)res.a1;
65
66	return 0;
67#else
68	return -ENXIO;
69#endif
70}
71
72static int stm32_bsec_read(void *context, unsigned int offset, void *buf,
73			   size_t bytes)
74{
75	struct stm32_romem_priv *priv = context;
76	struct device *dev = priv->cfg.dev;
77	u32 roffset, rbytes, val;
78	u8 *buf8 = buf, *val8 = (u8 *)&val;
79	int i, j = 0, ret, skip_bytes, size;
80
81	/* Round unaligned access to 32-bits */
82	roffset = rounddown(offset, 4);
83	skip_bytes = offset & 0x3;
84	rbytes = roundup(bytes + skip_bytes, 4);
85
86	if (roffset + rbytes > priv->cfg.size)
87		return -EINVAL;
88
89	for (i = roffset; (i < roffset + rbytes); i += 4) {
90		u32 otp = i >> 2;
91
92		if (otp < priv->lower) {
93			/* read lower data from shadow registers */
94			val = readl_relaxed(
95				priv->base + STM32MP15_BSEC_DATA0 + i);
96		} else {
97			ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, otp, 0,
98					     &val);
99			if (ret) {
100				dev_err(dev, "Can't read data%d (%d)\n", otp,
101					ret);
102				return ret;
103			}
104		}
105		/* skip first bytes in case of unaligned read */
106		if (skip_bytes)
107			size = min(bytes, (size_t)(4 - skip_bytes));
108		else
109			size = min(bytes, (size_t)4);
110		memcpy(&buf8[j], &val8[skip_bytes], size);
111		bytes -= size;
112		j += size;
113		skip_bytes = 0;
114	}
115
116	return 0;
117}
118
119static int stm32_bsec_write(void *context, unsigned int offset, void *buf,
120			    size_t bytes)
121{
122	struct stm32_romem_priv *priv = context;
123	struct device *dev = priv->cfg.dev;
124	u32 *buf32 = buf;
125	int ret, i;
126
127	/* Allow only writing complete 32-bits aligned words */
128	if ((bytes % 4) || (offset % 4))
129		return -EINVAL;
130
131	for (i = offset; i < offset + bytes; i += 4) {
132		ret = stm32_bsec_smc(STM32_SMC_PROG_OTP, i >> 2, *buf32++,
133				     NULL);
134		if (ret) {
135			dev_err(dev, "Can't write data%d (%d)\n", i >> 2, ret);
136			return ret;
137		}
138	}
139
140	if (offset + bytes >= priv->lower * 4)
141		dev_warn(dev, "Update of upper OTPs with ECC protection (word programming, only once)\n");
142
143	return 0;
144}
145
146static int stm32_bsec_pta_read(void *context, unsigned int offset, void *buf,
147			       size_t bytes)
148{
149	struct stm32_romem_priv *priv = context;
150
151	return stm32_bsec_optee_ta_read(priv->ctx, offset, buf, bytes);
152}
153
154static int stm32_bsec_pta_write(void *context, unsigned int offset, void *buf,
155				size_t bytes)
156{
157	struct stm32_romem_priv *priv = context;
158
159	return stm32_bsec_optee_ta_write(priv->ctx, priv->lower, offset, buf, bytes);
160}
161
162static bool stm32_bsec_smc_check(void)
163{
164	u32 val;
165	int ret;
166
167	/* check that the OP-TEE support the BSEC SMC (legacy mode) */
168	ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, 0, 0, &val);
169
170	return !ret;
171}
172
173static bool optee_presence_check(void)
174{
175	struct device_node *np;
176	bool tee_detected = false;
177
178	/* check that the OP-TEE node is present and available. */
179	np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");
180	if (np && of_device_is_available(np))
181		tee_detected = true;
182	of_node_put(np);
183
184	return tee_detected;
185}
186
187static int stm32_romem_probe(struct platform_device *pdev)
188{
189	const struct stm32_romem_cfg *cfg;
190	struct device *dev = &pdev->dev;
191	struct stm32_romem_priv *priv;
192	struct resource *res;
193	int rc;
194
195	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
196	if (!priv)
197		return -ENOMEM;
198
199	priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
200	if (IS_ERR(priv->base))
201		return PTR_ERR(priv->base);
202
203	priv->cfg.name = "stm32-romem";
204	priv->cfg.word_size = 1;
205	priv->cfg.stride = 1;
206	priv->cfg.dev = dev;
207	priv->cfg.priv = priv;
208	priv->cfg.owner = THIS_MODULE;
209	priv->cfg.type = NVMEM_TYPE_OTP;
210
211	priv->lower = 0;
212
213	cfg = (const struct stm32_romem_cfg *)
214		of_match_device(dev->driver->of_match_table, dev)->data;
215	if (!cfg) {
216		priv->cfg.read_only = true;
217		priv->cfg.size = resource_size(res);
218		priv->cfg.reg_read = stm32_romem_read;
219	} else {
220		priv->cfg.size = cfg->size;
221		priv->lower = cfg->lower;
222		if (cfg->ta || optee_presence_check()) {
223			rc = stm32_bsec_optee_ta_open(&priv->ctx);
224			if (rc) {
225				/* wait for OP-TEE client driver to be up and ready */
226				if (rc == -EPROBE_DEFER)
227					return -EPROBE_DEFER;
228				/* BSEC PTA is required or SMC not supported */
229				if (cfg->ta || !stm32_bsec_smc_check())
230					return rc;
231			}
232		}
233		if (priv->ctx) {
234			rc = devm_add_action_or_reset(dev, stm32_bsec_optee_ta_close, priv->ctx);
235			if (rc) {
236				dev_err(dev, "devm_add_action_or_reset() failed (%d)\n", rc);
237				return rc;
238			}
239			priv->cfg.reg_read = stm32_bsec_pta_read;
240			priv->cfg.reg_write = stm32_bsec_pta_write;
241		} else {
242			priv->cfg.reg_read = stm32_bsec_read;
243			priv->cfg.reg_write = stm32_bsec_write;
244		}
245	}
246
247	return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg));
248}
249
250/*
251 * STM32MP15/13 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits)
252 * => 96 x 32-bits data words
253 * - Lower: 1K bits, 2:1 redundancy, incremental bit programming
254 *   => 32 (x 32-bits) lower shadow registers = words 0 to 31
255 * - Upper: 2K bits, ECC protection, word programming only
256 *   => 64 (x 32-bits) = words 32 to 95
257 */
258static const struct stm32_romem_cfg stm32mp15_bsec_cfg = {
259	.size = 384,
260	.lower = 32,
261	.ta = false,
262};
263
264static const struct stm32_romem_cfg stm32mp13_bsec_cfg = {
265	.size = 384,
266	.lower = 32,
267	.ta = true,
268};
269
270static const struct of_device_id stm32_romem_of_match[] __maybe_unused = {
271	{ .compatible = "st,stm32f4-otp", }, {
272		.compatible = "st,stm32mp15-bsec",
273		.data = (void *)&stm32mp15_bsec_cfg,
274	}, {
275		.compatible = "st,stm32mp13-bsec",
276		.data = (void *)&stm32mp13_bsec_cfg,
277	},
278	{ /* sentinel */ },
279};
280MODULE_DEVICE_TABLE(of, stm32_romem_of_match);
281
282static struct platform_driver stm32_romem_driver = {
283	.probe = stm32_romem_probe,
284	.driver = {
285		.name = "stm32-romem",
286		.of_match_table = of_match_ptr(stm32_romem_of_match),
287	},
288};
289module_platform_driver(stm32_romem_driver);
290
291MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
292MODULE_DESCRIPTION("STMicroelectronics STM32 RO-MEM");
293MODULE_ALIAS("platform:nvmem-stm32-romem");
294MODULE_LICENSE("GPL v2");
295