162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only 262306a36Sopenharmony_ci * 362306a36Sopenharmony_ci * Copyright (c) 2021, MediaTek Inc. 462306a36Sopenharmony_ci * Copyright (c) 2021-2022, Intel Corporation. 562306a36Sopenharmony_ci * 662306a36Sopenharmony_ci * Authors: 762306a36Sopenharmony_ci * Haijun Liu <haijun.liu@mediatek.com> 862306a36Sopenharmony_ci * Sreehari Kancharla <sreehari.kancharla@intel.com> 962306a36Sopenharmony_ci * 1062306a36Sopenharmony_ci * Contributors: 1162306a36Sopenharmony_ci * Moises Veleta <moises.veleta@intel.com> 1262306a36Sopenharmony_ci * Ricardo Martinez <ricardo.martinez@linux.intel.com> 1362306a36Sopenharmony_ci */ 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci#ifndef __T7XX_PCIE_MAC_H__ 1662306a36Sopenharmony_ci#define __T7XX_PCIE_MAC_H__ 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci#include "t7xx_pci.h" 1962306a36Sopenharmony_ci#include "t7xx_reg.h" 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci#define IREG_BASE(t7xx_dev) ((t7xx_dev)->base_addr.pcie_mac_ireg_base) 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_civoid t7xx_pcie_mac_interrupts_en(struct t7xx_pci_dev *t7xx_dev); 2462306a36Sopenharmony_civoid t7xx_pcie_mac_interrupts_dis(struct t7xx_pci_dev *t7xx_dev); 2562306a36Sopenharmony_civoid t7xx_pcie_mac_atr_init(struct t7xx_pci_dev *t7xx_dev); 2662306a36Sopenharmony_civoid t7xx_pcie_mac_clear_int(struct t7xx_pci_dev *t7xx_dev, enum t7xx_int int_type); 2762306a36Sopenharmony_civoid t7xx_pcie_mac_set_int(struct t7xx_pci_dev *t7xx_dev, enum t7xx_int int_type); 2862306a36Sopenharmony_civoid t7xx_pcie_mac_clear_int_status(struct t7xx_pci_dev *t7xx_dev, enum t7xx_int int_type); 2962306a36Sopenharmony_civoid t7xx_pcie_set_mac_msix_cfg(struct t7xx_pci_dev *t7xx_dev, unsigned int irq_count); 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ci#endif /* __T7XX_PCIE_MAC_H__ */ 32