162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only 262306a36Sopenharmony_ci * 362306a36Sopenharmony_ci * Copyright (C) 2020-21 Intel Corporation. 462306a36Sopenharmony_ci */ 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci#ifndef IOSM_IPC_MMIO_H 762306a36Sopenharmony_ci#define IOSM_IPC_MMIO_H 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci/* Minimal IOSM CP VERSION which has valid CP_CAPABILITIES field */ 1062306a36Sopenharmony_ci#define IOSM_CP_VERSION 0x0100UL 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci/* DL dir Aggregation support mask */ 1362306a36Sopenharmony_ci#define DL_AGGR BIT(9) 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci/* UL dir Aggregation support mask */ 1662306a36Sopenharmony_ci#define UL_AGGR BIT(8) 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci/* UL flow credit support mask */ 1962306a36Sopenharmony_ci#define UL_FLOW_CREDIT BIT(21) 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci/* Possible states of the IPC finite state machine. */ 2262306a36Sopenharmony_cienum ipc_mem_device_ipc_state { 2362306a36Sopenharmony_ci IPC_MEM_DEVICE_IPC_UNINIT, 2462306a36Sopenharmony_ci IPC_MEM_DEVICE_IPC_INIT, 2562306a36Sopenharmony_ci IPC_MEM_DEVICE_IPC_RUNNING, 2662306a36Sopenharmony_ci IPC_MEM_DEVICE_IPC_RECOVERY, 2762306a36Sopenharmony_ci IPC_MEM_DEVICE_IPC_ERROR, 2862306a36Sopenharmony_ci IPC_MEM_DEVICE_IPC_DONT_CARE, 2962306a36Sopenharmony_ci IPC_MEM_DEVICE_IPC_INVALID = -1 3062306a36Sopenharmony_ci}; 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci/* Boot ROM exit status. */ 3362306a36Sopenharmony_cienum rom_exit_code { 3462306a36Sopenharmony_ci IMEM_ROM_EXIT_OPEN_EXT = 0x01, 3562306a36Sopenharmony_ci IMEM_ROM_EXIT_OPEN_MEM = 0x02, 3662306a36Sopenharmony_ci IMEM_ROM_EXIT_CERT_EXT = 0x10, 3762306a36Sopenharmony_ci IMEM_ROM_EXIT_CERT_MEM = 0x20, 3862306a36Sopenharmony_ci IMEM_ROM_EXIT_FAIL = 0xFF 3962306a36Sopenharmony_ci}; 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ci/* Boot stages */ 4262306a36Sopenharmony_cienum ipc_mem_exec_stage { 4362306a36Sopenharmony_ci IPC_MEM_EXEC_STAGE_RUN = 0x600DF00D, 4462306a36Sopenharmony_ci IPC_MEM_EXEC_STAGE_CRASH = 0x8BADF00D, 4562306a36Sopenharmony_ci IPC_MEM_EXEC_STAGE_CD_READY = 0xBADC0DED, 4662306a36Sopenharmony_ci IPC_MEM_EXEC_STAGE_BOOT = 0xFEEDB007, 4762306a36Sopenharmony_ci IPC_MEM_EXEC_STAGE_PSI = 0xFEEDBEEF, 4862306a36Sopenharmony_ci IPC_MEM_EXEC_STAGE_EBL = 0xFEEDCAFE, 4962306a36Sopenharmony_ci IPC_MEM_EXEC_STAGE_INVALID = 0xFFFFFFFF 5062306a36Sopenharmony_ci}; 5162306a36Sopenharmony_ci 5262306a36Sopenharmony_ci/* mmio scratchpad info */ 5362306a36Sopenharmony_cistruct mmio_offset { 5462306a36Sopenharmony_ci int exec_stage; 5562306a36Sopenharmony_ci int chip_info; 5662306a36Sopenharmony_ci int rom_exit_code; 5762306a36Sopenharmony_ci int psi_address; 5862306a36Sopenharmony_ci int psi_size; 5962306a36Sopenharmony_ci int ipc_status; 6062306a36Sopenharmony_ci int context_info; 6162306a36Sopenharmony_ci int ap_win_base; 6262306a36Sopenharmony_ci int ap_win_end; 6362306a36Sopenharmony_ci int cp_version; 6462306a36Sopenharmony_ci int cp_capability; 6562306a36Sopenharmony_ci}; 6662306a36Sopenharmony_ci 6762306a36Sopenharmony_ci/** 6862306a36Sopenharmony_ci * struct iosm_mmio - MMIO region mapped to the doorbell scratchpad. 6962306a36Sopenharmony_ci * @base: Base address of MMIO region 7062306a36Sopenharmony_ci * @dev: Pointer to device structure 7162306a36Sopenharmony_ci * @offset: Start offset 7262306a36Sopenharmony_ci * @context_info_addr: Physical base address of context info structure 7362306a36Sopenharmony_ci * @chip_info_version: Version of chip info structure 7462306a36Sopenharmony_ci * @chip_info_size: Size of chip info structure 7562306a36Sopenharmony_ci * @mux_protocol: mux protocol 7662306a36Sopenharmony_ci * @has_ul_flow_credit: Ul flow credit support 7762306a36Sopenharmony_ci * @has_slp_no_prot: Device sleep no protocol support 7862306a36Sopenharmony_ci * @has_mcr_support: Usage of mcr support 7962306a36Sopenharmony_ci */ 8062306a36Sopenharmony_cistruct iosm_mmio { 8162306a36Sopenharmony_ci unsigned char __iomem *base; 8262306a36Sopenharmony_ci struct device *dev; 8362306a36Sopenharmony_ci struct mmio_offset offset; 8462306a36Sopenharmony_ci phys_addr_t context_info_addr; 8562306a36Sopenharmony_ci unsigned int chip_info_version; 8662306a36Sopenharmony_ci unsigned int chip_info_size; 8762306a36Sopenharmony_ci u32 mux_protocol; 8862306a36Sopenharmony_ci u8 has_ul_flow_credit:1, 8962306a36Sopenharmony_ci has_slp_no_prot:1, 9062306a36Sopenharmony_ci has_mcr_support:1; 9162306a36Sopenharmony_ci}; 9262306a36Sopenharmony_ci 9362306a36Sopenharmony_ci/** 9462306a36Sopenharmony_ci * ipc_mmio_init - Allocate mmio instance data 9562306a36Sopenharmony_ci * @mmio_addr: Mapped AP base address of the MMIO area. 9662306a36Sopenharmony_ci * @dev: Pointer to device structure 9762306a36Sopenharmony_ci * 9862306a36Sopenharmony_ci * Returns: address of mmio instance data or NULL if fails. 9962306a36Sopenharmony_ci */ 10062306a36Sopenharmony_cistruct iosm_mmio *ipc_mmio_init(void __iomem *mmio_addr, struct device *dev); 10162306a36Sopenharmony_ci 10262306a36Sopenharmony_ci/** 10362306a36Sopenharmony_ci * ipc_mmio_set_psi_addr_and_size - Set start address and size of the 10462306a36Sopenharmony_ci * primary system image (PSI) for the 10562306a36Sopenharmony_ci * FW dowload. 10662306a36Sopenharmony_ci * @ipc_mmio: Pointer to mmio instance 10762306a36Sopenharmony_ci * @addr: PSI address 10862306a36Sopenharmony_ci * @size: PSI immage size 10962306a36Sopenharmony_ci */ 11062306a36Sopenharmony_civoid ipc_mmio_set_psi_addr_and_size(struct iosm_mmio *ipc_mmio, dma_addr_t addr, 11162306a36Sopenharmony_ci u32 size); 11262306a36Sopenharmony_ci 11362306a36Sopenharmony_ci/** 11462306a36Sopenharmony_ci * ipc_mmio_set_contex_info_addr - Stores the Context Info Address in 11562306a36Sopenharmony_ci * MMIO instance to share it with CP during 11662306a36Sopenharmony_ci * mmio_init. 11762306a36Sopenharmony_ci * @ipc_mmio: Pointer to mmio instance 11862306a36Sopenharmony_ci * @addr: 64-bit address of AP context information. 11962306a36Sopenharmony_ci */ 12062306a36Sopenharmony_civoid ipc_mmio_set_contex_info_addr(struct iosm_mmio *ipc_mmio, 12162306a36Sopenharmony_ci phys_addr_t addr); 12262306a36Sopenharmony_ci 12362306a36Sopenharmony_ci/** 12462306a36Sopenharmony_ci * ipc_mmio_get_cp_version - Get the CP IPC version 12562306a36Sopenharmony_ci * @ipc_mmio: Pointer to mmio instance 12662306a36Sopenharmony_ci * 12762306a36Sopenharmony_ci * Returns: version number on success and failure value on error. 12862306a36Sopenharmony_ci */ 12962306a36Sopenharmony_ciint ipc_mmio_get_cp_version(struct iosm_mmio *ipc_mmio); 13062306a36Sopenharmony_ci 13162306a36Sopenharmony_ci/** 13262306a36Sopenharmony_ci * ipc_mmio_get_rom_exit_code - Get exit code from CP boot rom download app 13362306a36Sopenharmony_ci * @ipc_mmio: Pointer to mmio instance 13462306a36Sopenharmony_ci * 13562306a36Sopenharmony_ci * Returns: exit code from CP boot rom download APP 13662306a36Sopenharmony_ci */ 13762306a36Sopenharmony_cienum rom_exit_code ipc_mmio_get_rom_exit_code(struct iosm_mmio *ipc_mmio); 13862306a36Sopenharmony_ci 13962306a36Sopenharmony_ci/** 14062306a36Sopenharmony_ci * ipc_mmio_get_exec_stage - Query CP execution stage 14162306a36Sopenharmony_ci * @ipc_mmio: Pointer to mmio instance 14262306a36Sopenharmony_ci * 14362306a36Sopenharmony_ci * Returns: CP execution stage 14462306a36Sopenharmony_ci */ 14562306a36Sopenharmony_cienum ipc_mem_exec_stage ipc_mmio_get_exec_stage(struct iosm_mmio *ipc_mmio); 14662306a36Sopenharmony_ci 14762306a36Sopenharmony_ci/** 14862306a36Sopenharmony_ci * ipc_mmio_get_ipc_state - Query CP IPC state 14962306a36Sopenharmony_ci * @ipc_mmio: Pointer to mmio instance 15062306a36Sopenharmony_ci * 15162306a36Sopenharmony_ci * Returns: CP IPC state 15262306a36Sopenharmony_ci */ 15362306a36Sopenharmony_cienum ipc_mem_device_ipc_state 15462306a36Sopenharmony_ciipc_mmio_get_ipc_state(struct iosm_mmio *ipc_mmio); 15562306a36Sopenharmony_ci 15662306a36Sopenharmony_ci/** 15762306a36Sopenharmony_ci * ipc_mmio_copy_chip_info - Copy size bytes of CP chip info structure 15862306a36Sopenharmony_ci * into caller provided buffer 15962306a36Sopenharmony_ci * @ipc_mmio: Pointer to mmio instance 16062306a36Sopenharmony_ci * @dest: Pointer to caller provided buff 16162306a36Sopenharmony_ci * @size: Number of bytes to copy 16262306a36Sopenharmony_ci */ 16362306a36Sopenharmony_civoid ipc_mmio_copy_chip_info(struct iosm_mmio *ipc_mmio, void *dest, 16462306a36Sopenharmony_ci size_t size); 16562306a36Sopenharmony_ci 16662306a36Sopenharmony_ci/** 16762306a36Sopenharmony_ci * ipc_mmio_config - Write context info and AP memory range addresses. 16862306a36Sopenharmony_ci * This needs to be called when CP is in 16962306a36Sopenharmony_ci * IPC_MEM_DEVICE_IPC_INIT state 17062306a36Sopenharmony_ci * 17162306a36Sopenharmony_ci * @ipc_mmio: Pointer to mmio instance 17262306a36Sopenharmony_ci */ 17362306a36Sopenharmony_civoid ipc_mmio_config(struct iosm_mmio *ipc_mmio); 17462306a36Sopenharmony_ci 17562306a36Sopenharmony_ci/** 17662306a36Sopenharmony_ci * ipc_mmio_update_cp_capability - Read and update modem capability, from mmio 17762306a36Sopenharmony_ci * capability offset 17862306a36Sopenharmony_ci * 17962306a36Sopenharmony_ci * @ipc_mmio: Pointer to mmio instance 18062306a36Sopenharmony_ci */ 18162306a36Sopenharmony_civoid ipc_mmio_update_cp_capability(struct iosm_mmio *ipc_mmio); 18262306a36Sopenharmony_ci 18362306a36Sopenharmony_ci#endif 184