1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5#include "coex.h" 6#include "debug.h" 7#include "fw.h" 8#include "mac.h" 9#include "phy.h" 10#include "reg.h" 11#include "rtw8852c.h" 12#include "rtw8852c_rfk.h" 13#include "rtw8852c_table.h" 14#include "util.h" 15 16#define RTW8852C_FW_FORMAT_MAX 0 17#define RTW8852C_FW_BASENAME "rtw89/rtw8852c_fw" 18#define RTW8852C_MODULE_FIRMWARE \ 19 RTW8852C_FW_BASENAME ".bin" 20 21static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = { 22 {13, 1614, grp_0}, /* ACH 0 */ 23 {13, 1614, grp_0}, /* ACH 1 */ 24 {13, 1614, grp_0}, /* ACH 2 */ 25 {13, 1614, grp_0}, /* ACH 3 */ 26 {13, 1614, grp_1}, /* ACH 4 */ 27 {13, 1614, grp_1}, /* ACH 5 */ 28 {13, 1614, grp_1}, /* ACH 6 */ 29 {13, 1614, grp_1}, /* ACH 7 */ 30 {13, 1614, grp_0}, /* B0MGQ */ 31 {13, 1614, grp_0}, /* B0HIQ */ 32 {13, 1614, grp_1}, /* B1MGQ */ 33 {13, 1614, grp_1}, /* B1HIQ */ 34 {40, 0, 0} /* FWCMDQ */ 35}; 36 37static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_pcie = { 38 1614, /* Group 0 */ 39 1614, /* Group 1 */ 40 3228, /* Public Max */ 41 0 /* WP threshold */ 42}; 43 44static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_pcie[] = { 45 [RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_pcie, &rtw8852c_hfc_pubcfg_pcie, 46 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 47 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 48 RTW89_HCIFC_POH}, 49 [RTW89_QTA_INVALID] = {NULL}, 50}; 51 52static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = { 53 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19, 54 &rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18, 55 &rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46, 56 &rtw89_mac_size.ple_qt47}, 57 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18, 58 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17, 59 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44, 60 &rtw89_mac_size.ple_qt45}, 61 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 62 NULL}, 63}; 64 65static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = { 66 R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1, 67 R_AX_H2CREG_DATA3_V1 68}; 69 70static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = { 71 R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1, 72 R_AX_C2HREG_DATA3_V1 73}; 74 75static const struct rtw89_page_regs rtw8852c_page_regs = { 76 .hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1, 77 .ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1, 78 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL_V1, 79 .ach_page_info = R_AX_ACH0_PAGE_INFO_V1, 80 .pub_page_info3 = R_AX_PUB_PAGE_INFO3_V1, 81 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1_V1, 82 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2_V1, 83 .pub_page_info1 = R_AX_PUB_PAGE_INFO1_V1, 84 .pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1, 85 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1_V1, 86 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2_V1, 87 .wp_page_info1 = R_AX_WP_PAGE_INFO1_V1, 88}; 89 90static const struct rtw89_reg_def rtw8852c_dcfo_comp = { 91 R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK 92}; 93 94static const struct rtw89_imr_info rtw8852c_imr_info = { 95 .wdrls_imr_set = B_AX_WDRLS_IMR_SET_V1, 96 .wsec_imr_reg = R_AX_SEC_ERROR_FLAG_IMR, 97 .wsec_imr_set = B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR, 98 .mpdu_tx_imr_set = B_AX_MPDU_TX_IMR_SET_V1, 99 .mpdu_rx_imr_set = B_AX_MPDU_RX_IMR_SET_V1, 100 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 101 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_B0_ERRFLAG_IMR, 102 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR_V1, 103 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET_V1, 104 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_B1_ERRFLAG_IMR, 105 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR_V1, 106 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET_V1, 107 .wde_imr_clr = B_AX_WDE_IMR_CLR_V1, 108 .wde_imr_set = B_AX_WDE_IMR_SET_V1, 109 .ple_imr_clr = B_AX_PLE_IMR_CLR_V1, 110 .ple_imr_set = B_AX_PLE_IMR_SET_V1, 111 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR_V1, 112 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V1, 113 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR_V1, 114 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET_V1, 115 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR_V1, 116 .other_disp_imr_set = B_AX_OTHER_DISP_IMR_SET_V1, 117 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR, 118 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR, 119 .bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1, 120 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR, 121 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_V1, 122 .ptcl_imr_set = B_AX_PTCL_IMR_SET_V1, 123 .cdma_imr_0_reg = R_AX_RX_ERR_FLAG_IMR, 124 .cdma_imr_0_clr = B_AX_RX_ERR_IMR_CLR_V1, 125 .cdma_imr_0_set = B_AX_RX_ERR_IMR_SET_V1, 126 .cdma_imr_1_reg = R_AX_TX_ERR_FLAG_IMR, 127 .cdma_imr_1_clr = B_AX_TX_ERR_IMR_CLR_V1, 128 .cdma_imr_1_set = B_AX_TX_ERR_IMR_SET_V1, 129 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR_V1, 130 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_CLR_V1, 131 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET_V1, 132 .rmac_imr_reg = R_AX_RX_ERR_IMR, 133 .rmac_imr_clr = B_AX_RMAC_IMR_CLR_V1, 134 .rmac_imr_set = B_AX_RMAC_IMR_SET_V1, 135 .tmac_imr_reg = R_AX_TRXPTCL_ERROR_INDICA_MASK, 136 .tmac_imr_clr = B_AX_TMAC_IMR_CLR_V1, 137 .tmac_imr_set = B_AX_TMAC_IMR_SET_V1, 138}; 139 140static const struct rtw89_rrsr_cfgs rtw8852c_rrsr_cfgs = { 141 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 142 .rsc = {R_AX_PTCL_RRSR1, B_AX_RSC_MASK, 2}, 143}; 144 145static const struct rtw89_dig_regs rtw8852c_dig_regs = { 146 .seg0_pd_reg = R_SEG0R_PD, 147 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 148 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 149 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 150 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 151 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 152 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 153 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 154 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 155 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 156 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 157 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 158 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 159 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1, 160 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 161 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1, 162 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 163 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1, 164 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 165 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1, 166 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 167}; 168 169static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg); 170static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 171 enum rtw89_mac_idx mac_idx); 172 173static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev) 174{ 175 u32 val32; 176 u32 ret; 177 178 val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK); 179 if (val32 == MAC_AX_HCI_SEL_PCIE_USB) 180 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L); 181 182 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 183 B_AX_AFSM_PCIE_SUS_EN); 184 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 185 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 186 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 187 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 188 189 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 190 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 191 if (ret) 192 return ret; 193 194 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 195 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 196 197 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 198 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 199 if (ret) 200 return ret; 201 202 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 203 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 204 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 205 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 206 207 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 208 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 209 210 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN); 211 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP); 212 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN | 213 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 214 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 215 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 216 B_AX_R_SYM_WLCMAC1_PC_EN); 217 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 218 219 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 220 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 221 if (ret) 222 return ret; 223 224 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 225 226 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 227 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 228 if (ret) 229 return ret; 230 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 231 XTAL_SI_OFF_WEI); 232 if (ret) 233 return ret; 234 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 235 XTAL_SI_OFF_EI); 236 if (ret) 237 return ret; 238 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 239 if (ret) 240 return ret; 241 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 242 XTAL_SI_PON_WEI); 243 if (ret) 244 return ret; 245 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 246 XTAL_SI_PON_EI); 247 if (ret) 248 return ret; 249 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 250 if (ret) 251 return ret; 252 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS); 253 if (ret) 254 return ret; 255 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 256 if (ret) 257 return ret; 258 259 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 260 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 261 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 262 263 fsleep(1000); 264 265 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 266 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 267 rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN, 268 B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN | 269 B_AX_LED1_PULL_LOW_EN); 270 271 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 272 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 273 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 274 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 275 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 276 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 277 B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN); 278 279 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 280 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 281 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | 282 B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | 283 B_AX_TMAC_EN | B_AX_RMAC_EN); 284 285 rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK, 286 PINMUX_EESK_FUNC_SEL_BT_LOG); 287 288 return 0; 289} 290 291static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev) 292{ 293 u32 val32; 294 u32 ret; 295 296 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 297 XTAL_SI_RFC2RF); 298 if (ret) 299 return ret; 300 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 301 if (ret) 302 return ret; 303 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 304 if (ret) 305 return ret; 306 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 307 if (ret) 308 return ret; 309 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 310 if (ret) 311 return ret; 312 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 313 XTAL_SI_SRAM2RFC); 314 if (ret) 315 return ret; 316 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 317 if (ret) 318 return ret; 319 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 320 if (ret) 321 return ret; 322 323 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 324 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 325 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 326 B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1); 327 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 328 329 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 330 if (ret) 331 return ret; 332 333 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 334 335 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 336 if (ret) 337 return ret; 338 339 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 340 341 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 342 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 343 if (ret) 344 return ret; 345 346 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, 0x0001A0B0); 347 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE); 348 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 349 350 return 0; 351} 352 353static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse, 354 struct rtw8852c_efuse *map) 355{ 356 ether_addr_copy(efuse->addr, map->e.mac_addr); 357 efuse->rfe_type = map->rfe_type; 358 efuse->xtal_cap = map->xtal_k; 359} 360 361static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 362 struct rtw8852c_efuse *map) 363{ 364 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 365 struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 366 u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b}; 367 u8 i, j; 368 369 tssi->thermal[RF_PATH_A] = map->path_a_therm; 370 tssi->thermal[RF_PATH_B] = map->path_b_therm; 371 372 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 373 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 374 sizeof(ofst[i]->cck_tssi)); 375 376 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 377 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 378 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 379 i, j, tssi->tssi_cck[i][j]); 380 381 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 382 sizeof(ofst[i]->bw40_tssi)); 383 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 384 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 385 memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i], 386 sizeof(tssi->tssi_6g_mcs[i])); 387 388 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 389 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 390 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 391 i, j, tssi->tssi_mcs[i][j]); 392 } 393} 394 395static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 396{ 397 if (high) 398 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); 399 if (low) 400 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); 401 402 return data != 0xff; 403} 404 405static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 406 struct rtw8852c_efuse *map) 407{ 408 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 409 bool valid = false; 410 411 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 412 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 413 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); 414 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 415 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 416 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); 417 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 418 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 419 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); 420 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 421 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 422 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); 423 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 424 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 425 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); 426 427 gain->offset_valid = valid; 428} 429 430static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) 431{ 432 struct rtw89_efuse *efuse = &rtwdev->efuse; 433 struct rtw8852c_efuse *map; 434 435 map = (struct rtw8852c_efuse *)log_map; 436 437 efuse->country_code[0] = map->country_code[0]; 438 efuse->country_code[1] = map->country_code[1]; 439 rtw8852c_efuse_parsing_tssi(rtwdev, map); 440 rtw8852c_efuse_parsing_gain_offset(rtwdev, map); 441 442 switch (rtwdev->hci.type) { 443 case RTW89_HCI_TYPE_PCIE: 444 rtw8852c_e_efuse_parsing(efuse, map); 445 break; 446 default: 447 return -ENOTSUPP; 448 } 449 450 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 451 452 return 0; 453} 454 455static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 456{ 457 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 458 static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB}; 459 static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3}; 460 u32 addr = rtwdev->chip->phycap_addr; 461 bool pg = false; 462 u32 ofst; 463 u8 i, j; 464 465 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 466 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 467 /* addrs are in decreasing order */ 468 ofst = tssi_trim_addr[i] - addr - j; 469 tssi->tssi_trim[i][j] = phycap_map[ofst]; 470 471 if (phycap_map[ofst] != 0xff) 472 pg = true; 473 } 474 475 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) { 476 /* addrs are in decreasing order */ 477 ofst = tssi_trim_addr_6g[i] - addr - j; 478 tssi->tssi_trim_6g[i][j] = phycap_map[ofst]; 479 480 if (phycap_map[ofst] != 0xff) 481 pg = true; 482 } 483 } 484 485 if (!pg) { 486 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 487 memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g)); 488 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 489 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 490 } 491 492 for (i = 0; i < RF_PATH_NUM_8852C; i++) 493 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 494 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 495 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 496 i, j, tssi->tssi_trim[i][j], 497 tssi_trim_addr[i] - j); 498} 499 500static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 501 u8 *phycap_map) 502{ 503 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 504 static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC}; 505 u32 addr = rtwdev->chip->phycap_addr; 506 u8 i; 507 508 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 509 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 510 511 rtw89_debug(rtwdev, RTW89_DBG_RFK, 512 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 513 i, info->thermal_trim[i]); 514 515 if (info->thermal_trim[i] != 0xff) 516 info->pg_thermal_trim = true; 517 } 518} 519 520static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev) 521{ 522#define __thm_setting(raw) \ 523({ \ 524 u8 __v = (raw); \ 525 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 526}) 527 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 528 u8 i, val; 529 530 if (!info->pg_thermal_trim) { 531 rtw89_debug(rtwdev, RTW89_DBG_RFK, 532 "[THERMAL][TRIM] no PG, do nothing\n"); 533 534 return; 535 } 536 537 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 538 val = __thm_setting(info->thermal_trim[i]); 539 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 540 541 rtw89_debug(rtwdev, RTW89_DBG_RFK, 542 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 543 i, val); 544 } 545#undef __thm_setting 546} 547 548static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 549 u8 *phycap_map) 550{ 551 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 552 static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB}; 553 u32 addr = rtwdev->chip->phycap_addr; 554 u8 i; 555 556 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 557 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 558 559 rtw89_debug(rtwdev, RTW89_DBG_RFK, 560 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 561 i, info->pa_bias_trim[i]); 562 563 if (info->pa_bias_trim[i] != 0xff) 564 info->pg_pa_bias_trim = true; 565 } 566} 567 568static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev) 569{ 570 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 571 u8 pabias_2g, pabias_5g; 572 u8 i; 573 574 if (!info->pg_pa_bias_trim) { 575 rtw89_debug(rtwdev, RTW89_DBG_RFK, 576 "[PA_BIAS][TRIM] no PG, do nothing\n"); 577 578 return; 579 } 580 581 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 582 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 583 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 584 585 rtw89_debug(rtwdev, RTW89_DBG_RFK, 586 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 587 i, pabias_2g, pabias_5g); 588 589 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 590 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 591 } 592} 593 594static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 595{ 596 rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map); 597 rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map); 598 rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 599 600 return 0; 601} 602 603static void rtw8852c_power_trim(struct rtw89_dev *rtwdev) 604{ 605 rtw8852c_thermal_trim(rtwdev); 606 rtw8852c_pa_bias_trim(rtwdev); 607} 608 609static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev, 610 const struct rtw89_chan *chan, 611 u8 mac_idx) 612{ 613 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 614 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 615 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 616 u8 txsc20 = 0, txsc40 = 0, txsc80 = 0; 617 u8 rf_mod_val = 0, chk_rate_mask = 0; 618 u32 txsc; 619 620 switch (chan->band_width) { 621 case RTW89_CHANNEL_WIDTH_160: 622 txsc80 = rtw89_phy_get_txsc(rtwdev, chan, 623 RTW89_CHANNEL_WIDTH_80); 624 fallthrough; 625 case RTW89_CHANNEL_WIDTH_80: 626 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 627 RTW89_CHANNEL_WIDTH_40); 628 fallthrough; 629 case RTW89_CHANNEL_WIDTH_40: 630 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 631 RTW89_CHANNEL_WIDTH_20); 632 break; 633 default: 634 break; 635 } 636 637 switch (chan->band_width) { 638 case RTW89_CHANNEL_WIDTH_160: 639 rf_mod_val = AX_WMAC_RFMOD_160M; 640 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 641 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40) | 642 FIELD_PREP(B_AX_TXSC_80M_MASK, txsc80); 643 break; 644 case RTW89_CHANNEL_WIDTH_80: 645 rf_mod_val = AX_WMAC_RFMOD_80M; 646 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 647 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40); 648 break; 649 case RTW89_CHANNEL_WIDTH_40: 650 rf_mod_val = AX_WMAC_RFMOD_40M; 651 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20); 652 break; 653 case RTW89_CHANNEL_WIDTH_20: 654 default: 655 rf_mod_val = AX_WMAC_RFMOD_20M; 656 txsc = 0; 657 break; 658 } 659 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val); 660 rtw89_write32(rtwdev, sub_carr, txsc); 661 662 switch (chan->band_type) { 663 case RTW89_BAND_2G: 664 chk_rate_mask = B_AX_BAND_MODE; 665 break; 666 case RTW89_BAND_5G: 667 case RTW89_BAND_6G: 668 chk_rate_mask = B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6; 669 break; 670 default: 671 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type); 672 return; 673 } 674 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN | 675 B_AX_RTS_LIMIT_IN_OFDM6); 676 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask); 677} 678 679static const u32 rtw8852c_sco_barker_threshold[14] = { 680 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6, 681 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a 682}; 683 684static const u32 rtw8852c_sco_cck_threshold[14] = { 685 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db, 686 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e 687}; 688 689static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 690 u8 primary_ch, enum rtw89_bandwidth bw) 691{ 692 u8 ch_element; 693 694 if (bw == RTW89_CHANNEL_WIDTH_20) { 695 ch_element = central_ch - 1; 696 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 697 if (primary_ch == 1) 698 ch_element = central_ch - 1 + 2; 699 else 700 ch_element = central_ch - 1 - 2; 701 } else { 702 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 703 return -EINVAL; 704 } 705 rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1, 706 rtw8852c_sco_barker_threshold[ch_element]); 707 rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1, 708 rtw8852c_sco_cck_threshold[ch_element]); 709 710 return 0; 711} 712 713struct rtw8852c_bb_gain { 714 u32 gain_g[BB_PATH_NUM_8852C]; 715 u32 gain_a[BB_PATH_NUM_8852C]; 716 u32 gain_mask; 717}; 718 719static const struct rtw8852c_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 720 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 721 .gain_mask = 0x00ff0000 }, 722 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 723 .gain_mask = 0xff000000 }, 724 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 725 .gain_mask = 0x000000ff }, 726 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 727 .gain_mask = 0x0000ff00 }, 728 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 729 .gain_mask = 0x00ff0000 }, 730 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 731 .gain_mask = 0xff000000 }, 732 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 733 .gain_mask = 0x000000ff }, 734}; 735 736static const struct rtw8852c_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 737 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 738 .gain_mask = 0x00ff0000 }, 739 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 740 .gain_mask = 0xff000000 }, 741}; 742 743struct rtw8852c_bb_gain_bypass { 744 u32 gain_g[BB_PATH_NUM_8852C]; 745 u32 gain_a[BB_PATH_NUM_8852C]; 746 u32 gain_mask_g; 747 u32 gain_mask_a; 748}; 749 750static 751const struct rtw8852c_bb_gain_bypass bb_gain_bypass_lna[LNA_GAIN_NUM] = { 752 { .gain_g = {0x4BB8, 0x4C7C}, .gain_a = {0x4BB4, 0x4C78}, 753 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 754 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 755 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 756 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 757 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 758 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 759 .gain_mask_g = 0xff0000, .gain_mask_a = 0xff000000}, 760 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB8, 0x4C7C}, 761 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 762 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 763 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 764 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 765 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 766}; 767 768struct rtw8852c_bb_gain_op1db { 769 struct { 770 u32 lna[BB_PATH_NUM_8852C]; 771 u32 tia_lna[BB_PATH_NUM_8852C]; 772 u32 mask; 773 } reg[LNA_GAIN_NUM]; 774 u32 reg_tia0_lna6[BB_PATH_NUM_8852C]; 775 u32 mask_tia0_lna6; 776}; 777 778static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = { 779 .reg = { 780 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 781 .mask = 0xff}, 782 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 783 .mask = 0xff00}, 784 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 785 .mask = 0xff0000}, 786 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 787 .mask = 0xff000000}, 788 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 789 .mask = 0xff}, 790 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 791 .mask = 0xff00}, 792 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 793 .mask = 0xff0000}, 794 }, 795 .reg_tia0_lna6 = {0x4674, 0x4758}, 796 .mask_tia0_lna6 = 0xff000000, 797}; 798 799static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev, 800 enum rtw89_subband subband, 801 enum rtw89_rf_path path) 802{ 803 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 804 u8 gain_band = rtw89_subband_to_bb_gain_band(subband); 805 s32 val; 806 u32 reg; 807 u32 mask; 808 int i; 809 810 for (i = 0; i < LNA_GAIN_NUM; i++) { 811 if (subband == RTW89_CH_2G) 812 reg = bb_gain_lna[i].gain_g[path]; 813 else 814 reg = bb_gain_lna[i].gain_a[path]; 815 816 mask = bb_gain_lna[i].gain_mask; 817 val = gain->lna_gain[gain_band][path][i]; 818 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 819 820 if (subband == RTW89_CH_2G) { 821 reg = bb_gain_bypass_lna[i].gain_g[path]; 822 mask = bb_gain_bypass_lna[i].gain_mask_g; 823 } else { 824 reg = bb_gain_bypass_lna[i].gain_a[path]; 825 mask = bb_gain_bypass_lna[i].gain_mask_a; 826 } 827 828 val = gain->lna_gain_bypass[gain_band][path][i]; 829 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 830 831 if (subband != RTW89_CH_2G) { 832 reg = bb_gain_op1db_a.reg[i].lna[path]; 833 mask = bb_gain_op1db_a.reg[i].mask; 834 val = gain->lna_op1db[gain_band][path][i]; 835 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 836 837 reg = bb_gain_op1db_a.reg[i].tia_lna[path]; 838 mask = bb_gain_op1db_a.reg[i].mask; 839 val = gain->tia_lna_op1db[gain_band][path][i]; 840 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 841 } 842 } 843 844 if (subband != RTW89_CH_2G) { 845 reg = bb_gain_op1db_a.reg_tia0_lna6[path]; 846 mask = bb_gain_op1db_a.mask_tia0_lna6; 847 val = gain->tia_lna_op1db[gain_band][path][7]; 848 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 849 } 850 851 for (i = 0; i < TIA_GAIN_NUM; i++) { 852 if (subband == RTW89_CH_2G) 853 reg = bb_gain_tia[i].gain_g[path]; 854 else 855 reg = bb_gain_tia[i].gain_a[path]; 856 857 mask = bb_gain_tia[i].gain_mask; 858 val = gain->tia_gain[gain_band][path][i]; 859 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 860 } 861} 862 863static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev, 864 const struct rtw89_chan *chan, 865 enum rtw89_phy_idx phy_idx, 866 enum rtw89_rf_path path) 867{ 868 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA0_LNA6_OP1DB_V1, 869 R_PATH1_G_TIA0_LNA6_OP1DB_V1}; 870 static const u32 rpl_mask[2] = {B_RPL_PATHA_MASK, B_RPL_PATHB_MASK}; 871 static const u32 rpl_tb_mask[2] = {B_RSSI_M_PATHA_MASK, B_RSSI_M_PATHB_MASK}; 872 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 873 enum rtw89_gain_offset gain_band; 874 s32 offset_q0, offset_base_q4; 875 s32 tmp = 0; 876 877 if (!efuse_gain->offset_valid) 878 return; 879 880 if (rtwdev->dbcc_en && path == RF_PATH_B) 881 phy_idx = RTW89_PHY_1; 882 883 if (chan->band_type == RTW89_BAND_2G) { 884 offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK]; 885 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 886 887 tmp = clamp_t(s32, (-offset_q0 << 3) + (offset_base_q4 >> 1), 888 S8_MIN >> 1, S8_MAX >> 1); 889 rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f); 890 } 891 892 gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type); 893 894 offset_q0 = -efuse_gain->offset[path][gain_band]; 895 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 896 897 tmp = (offset_q0 << 2) + (offset_base_q4 >> 2); 898 tmp = clamp_t(s32, -tmp, S8_MIN, S8_MAX); 899 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff); 900 901 tmp = clamp_t(s32, offset_q0 << 4, S8_MIN, S8_MAX); 902 rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx); 903 rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx); 904} 905 906static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev, 907 const struct rtw89_chan *chan, 908 enum rtw89_phy_idx phy_idx) 909{ 910 u8 sco; 911 u16 central_freq = chan->freq; 912 u8 central_ch = chan->channel; 913 u8 band = chan->band_type; 914 u8 subband = chan->subband_type; 915 bool is_2g = band == RTW89_BAND_2G; 916 u8 chan_idx; 917 918 if (!central_freq) { 919 rtw89_warn(rtwdev, "Invalid central_freq\n"); 920 return; 921 } 922 923 if (phy_idx == RTW89_PHY_0) { 924 /* Path A */ 925 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A); 926 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_A); 927 928 if (is_2g) 929 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 930 B_PATH0_BAND_SEL_MSK_V1, 1, 931 phy_idx); 932 else 933 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 934 B_PATH0_BAND_SEL_MSK_V1, 0, 935 phy_idx); 936 /* Path B */ 937 if (!rtwdev->dbcc_en) { 938 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 939 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 940 941 if (is_2g) 942 rtw89_phy_write32_idx(rtwdev, 943 R_PATH1_BAND_SEL_V1, 944 B_PATH1_BAND_SEL_MSK_V1, 945 1, phy_idx); 946 else 947 rtw89_phy_write32_idx(rtwdev, 948 R_PATH1_BAND_SEL_V1, 949 B_PATH1_BAND_SEL_MSK_V1, 950 0, phy_idx); 951 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 952 } else { 953 if (is_2g) 954 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 955 else 956 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 957 } 958 /* SCO compensate FC setting */ 959 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 960 central_freq, phy_idx); 961 /* round_up((1/fc0)*pow(2,18)) */ 962 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 963 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 964 phy_idx); 965 } else { 966 /* Path B */ 967 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 968 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 969 970 if (is_2g) 971 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 972 B_PATH1_BAND_SEL_MSK_V1, 973 1, phy_idx); 974 else 975 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 976 B_PATH1_BAND_SEL_MSK_V1, 977 0, phy_idx); 978 /* SCO compensate FC setting */ 979 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 980 central_freq, phy_idx); 981 /* round_up((1/fc0)*pow(2,18)) */ 982 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 983 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 984 phy_idx); 985 } 986 /* CCK parameters */ 987 if (band == RTW89_BAND_2G) { 988 if (central_ch == 14) { 989 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 990 B_PCOEFF01_MSK_V1, 0x3b13ff); 991 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 992 B_PCOEFF23_MSK_V1, 0x1c42de); 993 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 994 B_PCOEFF45_MSK_V1, 0xfdb0ad); 995 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 996 B_PCOEFF67_MSK_V1, 0xf60f6e); 997 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 998 B_PCOEFF89_MSK_V1, 0xfd8f92); 999 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1000 B_PCOEFFAB_MSK_V1, 0x2d011); 1001 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1002 B_PCOEFFCD_MSK_V1, 0x1c02c); 1003 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1004 B_PCOEFFEF_MSK_V1, 0xfff00a); 1005 } else { 1006 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1007 B_PCOEFF01_MSK_V1, 0x3d23ff); 1008 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1009 B_PCOEFF23_MSK_V1, 0x29b354); 1010 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1011 B_PCOEFF45_MSK_V1, 0xfc1c8); 1012 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1013 B_PCOEFF67_MSK_V1, 0xfdb053); 1014 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1015 B_PCOEFF89_MSK_V1, 0xf86f9a); 1016 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1017 B_PCOEFFAB_MSK_V1, 0xfaef92); 1018 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1019 B_PCOEFFCD_MSK_V1, 0xfe5fcc); 1020 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1021 B_PCOEFFEF_MSK_V1, 0xffdff5); 1022 } 1023 } 1024 1025 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); 1026 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx); 1027} 1028 1029static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 1030{ 1031 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; 1032 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 1033 1034 switch (bw) { 1035 case RTW89_CHANNEL_WIDTH_5: 1036 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 1037 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 1038 break; 1039 case RTW89_CHANNEL_WIDTH_10: 1040 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 1041 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 1042 break; 1043 case RTW89_CHANNEL_WIDTH_20: 1044 case RTW89_CHANNEL_WIDTH_40: 1045 case RTW89_CHANNEL_WIDTH_80: 1046 case RTW89_CHANNEL_WIDTH_160: 1047 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1048 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1049 break; 1050 default: 1051 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1052 } 1053} 1054 1055static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw, 1056 enum rtw89_phy_idx phy_idx) 1057{ 1058 if (bw == RTW89_CHANNEL_WIDTH_20) { 1059 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx); 1060 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1061 } else { 1062 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx); 1063 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1064 } 1065} 1066 1067static void 1068rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1069 enum rtw89_phy_idx phy_idx) 1070{ 1071 u8 mod_sbw = 0; 1072 1073 switch (bw) { 1074 case RTW89_CHANNEL_WIDTH_5: 1075 case RTW89_CHANNEL_WIDTH_10: 1076 case RTW89_CHANNEL_WIDTH_20: 1077 if (bw == RTW89_CHANNEL_WIDTH_5) 1078 mod_sbw = 0x1; 1079 else if (bw == RTW89_CHANNEL_WIDTH_10) 1080 mod_sbw = 0x2; 1081 else if (bw == RTW89_CHANNEL_WIDTH_20) 1082 mod_sbw = 0x0; 1083 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1084 phy_idx); 1085 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 1086 mod_sbw, phy_idx); 1087 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0, 1088 phy_idx); 1089 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1090 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1091 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1092 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1093 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1094 B_PATH0_BW_SEL_MSK_V1, 0xf); 1095 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1096 B_PATH1_BW_SEL_MSK_V1, 0xf); 1097 break; 1098 case RTW89_CHANNEL_WIDTH_40: 1099 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1100 phy_idx); 1101 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1102 phy_idx); 1103 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1104 pri_ch, 1105 phy_idx); 1106 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1107 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1108 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1109 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1110 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1111 B_PATH0_BW_SEL_MSK_V1, 0xf); 1112 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1113 B_PATH1_BW_SEL_MSK_V1, 0xf); 1114 break; 1115 case RTW89_CHANNEL_WIDTH_80: 1116 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1117 phy_idx); 1118 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1119 phy_idx); 1120 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1121 pri_ch, 1122 phy_idx); 1123 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1124 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2); 1125 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1126 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2); 1127 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1128 B_PATH0_BW_SEL_MSK_V1, 0xd); 1129 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1130 B_PATH1_BW_SEL_MSK_V1, 0xd); 1131 break; 1132 case RTW89_CHANNEL_WIDTH_160: 1133 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3, 1134 phy_idx); 1135 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1136 phy_idx); 1137 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1138 pri_ch, 1139 phy_idx); 1140 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1141 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x1); 1142 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1143 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x1); 1144 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1145 B_PATH0_BW_SEL_MSK_V1, 0xb); 1146 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1147 B_PATH1_BW_SEL_MSK_V1, 0xb); 1148 break; 1149 default: 1150 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1151 pri_ch); 1152 } 1153 1154 if (bw == RTW89_CHANNEL_WIDTH_40) { 1155 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1156 B_RX_BW40_2XFFT_EN_MSK_V1, 0x1, phy_idx); 1157 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx); 1158 } else { 1159 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1160 B_RX_BW40_2XFFT_EN_MSK_V1, 0x0, phy_idx); 1161 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx); 1162 } 1163 1164 if (phy_idx == RTW89_PHY_0) { 1165 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A); 1166 if (!rtwdev->dbcc_en) 1167 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1168 } else { 1169 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1170 } 1171 1172 rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx); 1173} 1174 1175static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev, 1176 const struct rtw89_chan *chan) 1177{ 1178 u8 center_chan = chan->channel; 1179 u8 bw = chan->band_width; 1180 1181 switch (chan->band_type) { 1182 case RTW89_BAND_2G: 1183 if (bw == RTW89_CHANNEL_WIDTH_20) { 1184 if (center_chan >= 5 && center_chan <= 8) 1185 return 2440; 1186 if (center_chan == 13) 1187 return 2480; 1188 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 1189 if (center_chan >= 3 && center_chan <= 10) 1190 return 2440; 1191 } 1192 break; 1193 case RTW89_BAND_5G: 1194 if (center_chan == 151 || center_chan == 153 || 1195 center_chan == 155 || center_chan == 163) 1196 return 5760; 1197 break; 1198 case RTW89_BAND_6G: 1199 if (center_chan == 195 || center_chan == 197 || 1200 center_chan == 199 || center_chan == 207) 1201 return 6920; 1202 break; 1203 default: 1204 break; 1205 } 1206 1207 return 0; 1208} 1209 1210#define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */ 1211#define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */ 1212#define MAX_TONE_NUM 2048 1213 1214static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev, 1215 const struct rtw89_chan *chan, 1216 enum rtw89_phy_idx phy_idx) 1217{ 1218 u32 spur_freq; 1219 s32 freq_diff, csi_idx, csi_tone_idx; 1220 1221 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1222 if (spur_freq == 0) { 1223 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx); 1224 return; 1225 } 1226 1227 freq_diff = (spur_freq - chan->freq) * 1000000; 1228 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125); 1229 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx); 1230 1231 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx); 1232 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx); 1233} 1234 1235static const struct rtw89_nbi_reg_def rtw8852c_nbi_reg_def[] = { 1236 [RF_PATH_A] = { 1237 .notch1_idx = {0x4C14, 0xFF}, 1238 .notch1_frac_idx = {0x4C14, 0xC00}, 1239 .notch1_en = {0x4C14, 0x1000}, 1240 .notch2_idx = {0x4C20, 0xFF}, 1241 .notch2_frac_idx = {0x4C20, 0xC00}, 1242 .notch2_en = {0x4C20, 0x1000}, 1243 }, 1244 [RF_PATH_B] = { 1245 .notch1_idx = {0x4CD8, 0xFF}, 1246 .notch1_frac_idx = {0x4CD8, 0xC00}, 1247 .notch1_en = {0x4CD8, 0x1000}, 1248 .notch2_idx = {0x4CE4, 0xFF}, 1249 .notch2_frac_idx = {0x4CE4, 0xC00}, 1250 .notch2_en = {0x4CE4, 0x1000}, 1251 }, 1252}; 1253 1254static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev, 1255 const struct rtw89_chan *chan, 1256 enum rtw89_rf_path path) 1257{ 1258 const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path]; 1259 u32 spur_freq, fc; 1260 s32 freq_diff; 1261 s32 nbi_idx, nbi_tone_idx; 1262 s32 nbi_frac_idx, nbi_frac_tone_idx; 1263 bool notch2_chk = false; 1264 1265 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1266 if (spur_freq == 0) { 1267 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1268 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1269 return; 1270 } 1271 1272 fc = chan->freq; 1273 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) { 1274 fc = (spur_freq > fc) ? fc + 40 : fc - 40; 1275 if ((fc > spur_freq && 1276 chan->channel < chan->primary_channel) || 1277 (fc < spur_freq && 1278 chan->channel > chan->primary_channel)) 1279 notch2_chk = true; 1280 } 1281 1282 freq_diff = (spur_freq - fc) * 1000000; 1283 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, &nbi_frac_idx); 1284 1285 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) { 1286 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx); 1287 } else { 1288 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ? 1289 128 : 256; 1290 1291 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx); 1292 } 1293 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125); 1294 1295 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) { 1296 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr, 1297 nbi->notch2_idx.mask, nbi_tone_idx); 1298 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr, 1299 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx); 1300 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1301 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1); 1302 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1303 } else { 1304 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr, 1305 nbi->notch1_idx.mask, nbi_tone_idx); 1306 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr, 1307 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx); 1308 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1309 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1); 1310 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1311 } 1312} 1313 1314static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val, 1315 enum rtw89_phy_idx phy_idx) 1316{ 1317 u32 notch; 1318 u32 notch2; 1319 1320 if (phy_idx == RTW89_PHY_0) { 1321 notch = R_PATH0_NOTCH; 1322 notch2 = R_PATH0_NOTCH2; 1323 } else { 1324 notch = R_PATH1_NOTCH; 1325 notch2 = R_PATH1_NOTCH2; 1326 } 1327 1328 rtw89_phy_write32_mask(rtwdev, notch, 1329 B_PATH0_NOTCH_VAL | B_PATH0_NOTCH_EN, val); 1330 rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN); 1331 rtw89_phy_write32_mask(rtwdev, notch2, 1332 B_PATH0_NOTCH2_VAL | B_PATH0_NOTCH2_EN, val); 1333 rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN); 1334} 1335 1336static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev, 1337 const struct rtw89_chan *chan, 1338 u8 pri_ch_idx, 1339 enum rtw89_phy_idx phy_idx) 1340{ 1341 rtw8852c_set_csi_tone_idx(rtwdev, chan, phy_idx); 1342 1343 if (phy_idx == RTW89_PHY_0) { 1344 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1345 (pri_ch_idx == RTW89_SC_20_LOWER || 1346 pri_ch_idx == RTW89_SC_20_UP3X)) { 1347 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0); 1348 if (!rtwdev->dbcc_en) 1349 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1350 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1351 (pri_ch_idx == RTW89_SC_20_UPPER || 1352 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1353 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0); 1354 if (!rtwdev->dbcc_en) 1355 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1356 } else { 1357 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A); 1358 if (!rtwdev->dbcc_en) 1359 rtw8852c_set_nbi_tone_idx(rtwdev, chan, 1360 RF_PATH_B); 1361 } 1362 } else { 1363 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1364 (pri_ch_idx == RTW89_SC_20_LOWER || 1365 pri_ch_idx == RTW89_SC_20_UP3X)) { 1366 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1367 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1368 (pri_ch_idx == RTW89_SC_20_UPPER || 1369 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1370 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1371 } else { 1372 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B); 1373 } 1374 } 1375 1376 if (pri_ch_idx == RTW89_SC_20_UP3X || pri_ch_idx == RTW89_SC_20_LOW3X) 1377 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx); 1378 else 1379 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx); 1380} 1381 1382static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev, 1383 const struct rtw89_chan *chan, 1384 enum rtw89_phy_idx phy_idx) 1385{ 1386 u8 pri_ch = chan->pri_ch_idx; 1387 bool mask_5m_low; 1388 bool mask_5m_en; 1389 1390 switch (chan->band_width) { 1391 case RTW89_CHANNEL_WIDTH_40: 1392 mask_5m_en = true; 1393 mask_5m_low = pri_ch == RTW89_SC_20_LOWER; 1394 break; 1395 case RTW89_CHANNEL_WIDTH_80: 1396 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || 1397 pri_ch == RTW89_SC_20_LOWEST; 1398 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; 1399 break; 1400 default: 1401 mask_5m_en = false; 1402 mask_5m_low = false; 1403 break; 1404 } 1405 1406 if (!mask_5m_en) { 1407 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0); 1408 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0); 1409 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, 1410 B_ASSIGN_SBD_OPT_EN, 0x0, phy_idx); 1411 } else { 1412 if (mask_5m_low) { 1413 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1414 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1415 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0); 1416 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1); 1417 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1418 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1419 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0); 1420 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1); 1421 } else { 1422 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1423 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1424 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1); 1425 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0); 1426 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1427 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1428 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1); 1429 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0); 1430 } 1431 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx); 1432 } 1433} 1434 1435static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev, 1436 enum rtw89_phy_idx phy_idx) 1437{ 1438 /*HW SI reset*/ 1439 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1440 0x7); 1441 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1442 0x7); 1443 1444 udelay(1); 1445 1446 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1447 phy_idx); 1448 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1449 phy_idx); 1450 /*HW SI reset*/ 1451 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1452 0x0); 1453 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1454 0x0); 1455 1456 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1457 phy_idx); 1458} 1459 1460static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 1461 enum rtw89_phy_idx phy_idx, bool en) 1462{ 1463 if (en) { 1464 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1465 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1466 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1467 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1468 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1469 phy_idx); 1470 if (band == RTW89_BAND_2G) 1471 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0); 1472 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 1473 } else { 1474 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1); 1475 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 1476 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1477 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1478 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1479 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1480 fsleep(1); 1481 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1482 phy_idx); 1483 } 1484} 1485 1486static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev, 1487 enum rtw89_phy_idx phy_idx) 1488{ 1489 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1490} 1491 1492static 1493void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1494 u8 tx_path_en, u8 trsw_tx, 1495 u8 trsw_rx, u8 trsw, u8 trsw_b) 1496{ 1497 static const u32 path_cr_bases[] = {0x5868, 0x7868}; 1498 u32 mask_ofst = 16; 1499 u32 cr; 1500 u32 val; 1501 1502 if (path >= ARRAY_SIZE(path_cr_bases)) 1503 return; 1504 1505 cr = path_cr_bases[path]; 1506 1507 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2; 1508 val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b); 1509 1510 rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val); 1511} 1512 1513enum rtw8852c_rfe_src { 1514 PAPE_RFM, 1515 TRSW_RFM, 1516 LNAON_RFM, 1517}; 1518 1519static 1520void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1521 enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl, 1522 u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val) 1523{ 1524 static const u32 path_cr_bases[] = {0x5894, 0x7894}; 1525 static const u32 masks[] = {0, 8, 16}; 1526 u32 mask, mask_ofst; 1527 u32 cr; 1528 u32 val; 1529 1530 if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases)) 1531 return; 1532 1533 mask_ofst = masks[src]; 1534 cr = path_cr_bases[path]; 1535 1536 val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) | 1537 FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) | 1538 FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) | 1539 FIELD_PREP(B_P0_RFM_OUT, rfm_output_val); 1540 mask = 0xff << mask_ofst; 1541 1542 rtw89_phy_write32_mask(rtwdev, cr, mask, val); 1543} 1544 1545static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev) 1546{ 1547 static const u32 cr_bases[] = {0x5800, 0x7800}; 1548 u32 addr; 1549 u8 i; 1550 1551 for (i = 0; i < ARRAY_SIZE(cr_bases); i++) { 1552 addr = cr_bases[i]; 1553 rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A); 1554 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X); 1555 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2); 1556 rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777); 1557 rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777); 1558 } 1559 1560 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff); 1561 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0); 1562 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0); 1563 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0); 1564 1565 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1); 1566 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0); 1567 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0); 1568 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0); 1569 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1); 1570 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0); 1571 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0); 1572 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0); 1573 1574 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1); 1575 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0); 1576 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0); 1577 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0); 1578 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1); 1579 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0); 1580 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0); 1581 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0); 1582 1583 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0); 1584 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4); 1585 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8); 1586 1587 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0); 1588 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4); 1589 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8); 1590} 1591 1592static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1593 enum rtw89_phy_idx phy_idx) 1594{ 1595 u32 addr; 1596 1597 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1598 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1599 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1600} 1601 1602static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev) 1603{ 1604 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1605 1606 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT, 1607 B_DBCC_80P80_SEL_EVM_RPT_EN); 1608 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2, 1609 B_DBCC_80P80_SEL_EVM_RPT2_EN); 1610 1611 rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1612 rtw8852c_bb_gpio_init(rtwdev); 1613 1614 /* read these registers after loading BB parameters */ 1615 gain->offset_base[RTW89_PHY_0] = 1616 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK); 1617 gain->offset_base[RTW89_PHY_1] = 1618 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK); 1619} 1620 1621static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev, 1622 const struct rtw89_chan *chan, 1623 enum rtw89_phy_idx phy_idx) 1624{ 1625 static const u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0, 1626 B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1}; 1627 struct rtw89_hal *hal = &rtwdev->hal; 1628 bool cck_en = chan->band_type == RTW89_BAND_2G; 1629 u8 pri_ch_idx = chan->pri_ch_idx; 1630 u32 mask, reg; 1631 u8 ntx_path; 1632 1633 if (chan->band_type == RTW89_BAND_2G) 1634 rtw8852c_ctrl_sco_cck(rtwdev, chan->channel, 1635 chan->primary_channel, 1636 chan->band_width); 1637 1638 rtw8852c_ctrl_ch(rtwdev, chan, phy_idx); 1639 rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1640 if (cck_en) { 1641 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1642 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0); 1643 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1644 B_PD_ARBITER_OFF, 0x0, phy_idx); 1645 } else { 1646 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1647 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1); 1648 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1649 B_PD_ARBITER_OFF, 0x1, phy_idx); 1650 } 1651 1652 rtw8852c_spur_elimination(rtwdev, chan, pri_ch_idx, phy_idx); 1653 rtw8852c_ctrl_btg(rtwdev, chan->band_type == RTW89_BAND_2G); 1654 rtw8852c_5m_mask(rtwdev, chan, phy_idx); 1655 1656 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1657 rtwdev->hal.cv != CHIP_CAV) { 1658 rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ, 1659 B_P80_AT_HIGH_FREQ, 0x0, phy_idx); 1660 reg = rtw89_mac_reg_by_idx(rtwdev, R_P80_AT_HIGH_FREQ_BB_WRP, phy_idx); 1661 if (chan->primary_channel > chan->channel) { 1662 rtw89_phy_write32_mask(rtwdev, 1663 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1664 ru_alloc_msk[phy_idx], 1); 1665 rtw89_write32_mask(rtwdev, reg, 1666 B_P80_AT_HIGH_FREQ_BB_WRP, 1); 1667 } else { 1668 rtw89_phy_write32_mask(rtwdev, 1669 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1670 ru_alloc_msk[phy_idx], 0); 1671 rtw89_write32_mask(rtwdev, reg, 1672 B_P80_AT_HIGH_FREQ_BB_WRP, 0); 1673 } 1674 } 1675 1676 if (chan->band_type == RTW89_BAND_6G && 1677 chan->band_width == RTW89_CHANNEL_WIDTH_160) 1678 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1679 B_CDD_EVM_CHK_EN, 0, phy_idx); 1680 else 1681 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1682 B_CDD_EVM_CHK_EN, 1, phy_idx); 1683 1684 if (!rtwdev->dbcc_en) { 1685 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1686 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1687 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1688 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1689 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1690 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1691 } else { 1692 if (phy_idx == RTW89_PHY_0) { 1693 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1694 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1695 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1696 } else { 1697 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1698 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1699 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1700 } 1701 } 1702 1703 if (chan->band_type == RTW89_BAND_6G) 1704 rtw89_phy_write32_set(rtwdev, R_MUIC, B_MUIC_EN); 1705 else 1706 rtw89_phy_write32_clr(rtwdev, R_MUIC, B_MUIC_EN); 1707 1708 if (hal->antenna_tx) 1709 ntx_path = hal->antenna_tx; 1710 else 1711 ntx_path = chan->band_type == RTW89_BAND_6G ? RF_B : RF_AB; 1712 1713 rtw8852c_ctrl_tx_path_tmac(rtwdev, ntx_path, (enum rtw89_mac_idx)phy_idx); 1714 1715 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1716} 1717 1718static void rtw8852c_set_channel(struct rtw89_dev *rtwdev, 1719 const struct rtw89_chan *chan, 1720 enum rtw89_mac_idx mac_idx, 1721 enum rtw89_phy_idx phy_idx) 1722{ 1723 rtw8852c_set_channel_mac(rtwdev, chan, mac_idx); 1724 rtw8852c_set_channel_bb(rtwdev, chan, phy_idx); 1725 rtw8852c_set_channel_rf(rtwdev, chan, phy_idx); 1726} 1727 1728static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en) 1729{ 1730 if (en) 1731 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1732 else 1733 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1734} 1735 1736static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en) 1737{ 1738 if (en) 1739 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1740 0x0); 1741 else 1742 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1743 0xf); 1744} 1745 1746static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1747 struct rtw89_channel_help_params *p, 1748 const struct rtw89_chan *chan, 1749 enum rtw89_mac_idx mac_idx, 1750 enum rtw89_phy_idx phy_idx) 1751{ 1752 if (enter) { 1753 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1754 RTW89_SCH_TX_SEL_ALL); 1755 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1756 rtw8852c_dfs_en(rtwdev, false); 1757 rtw8852c_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1758 rtw8852c_adc_en(rtwdev, false); 1759 fsleep(40); 1760 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 1761 } else { 1762 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1763 rtw8852c_adc_en(rtwdev, true); 1764 rtw8852c_dfs_en(rtwdev, true); 1765 rtw8852c_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1766 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 1767 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1768 } 1769} 1770 1771static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev) 1772{ 1773 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc; 1774 1775 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1776 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1777 memset(rfk_mcc, 0, sizeof(*rfk_mcc)); 1778 rtw8852c_lck_init(rtwdev); 1779 1780 rtw8852c_rck(rtwdev); 1781 rtw8852c_dack(rtwdev); 1782 rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false); 1783} 1784 1785static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev) 1786{ 1787 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1788 1789 rtw8852c_mcc_get_ch_info(rtwdev, phy_idx); 1790 rtw8852c_rx_dck(rtwdev, phy_idx, false); 1791 rtw8852c_iqk(rtwdev, phy_idx); 1792 rtw8852c_tssi(rtwdev, phy_idx); 1793 rtw8852c_dpk(rtwdev, phy_idx); 1794 rtw89_fw_h2c_rf_ntfy_mcc(rtwdev); 1795} 1796 1797static void rtw8852c_rfk_band_changed(struct rtw89_dev *rtwdev, 1798 enum rtw89_phy_idx phy_idx) 1799{ 1800 rtw8852c_tssi_scan(rtwdev, phy_idx); 1801} 1802 1803static void rtw8852c_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1804{ 1805 rtw8852c_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1806} 1807 1808static void rtw8852c_rfk_track(struct rtw89_dev *rtwdev) 1809{ 1810 rtw8852c_dpk_track(rtwdev); 1811 rtw8852c_lck_track(rtwdev); 1812 rtw8852c_rx_dck_track(rtwdev); 1813} 1814 1815static u32 rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1816 enum rtw89_phy_idx phy_idx, s16 ref) 1817{ 1818 s8 ofst_int = 0; 1819 u8 base_cw_0db = 0x27; 1820 u16 tssi_16dbm_cw = 0x12c; 1821 s16 pwr_s10_3 = 0; 1822 s16 rf_pwr_cw = 0; 1823 u16 bb_pwr_cw = 0; 1824 u32 pwr_cw = 0; 1825 u32 tssi_ofst_cw = 0; 1826 1827 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1828 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1829 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1830 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1831 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1832 1833 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1834 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1835 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1836 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1837 1838 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1839} 1840 1841static 1842void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1843 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1844{ 1845 s8 pw_ofst_2tx; 1846 s8 val_1t; 1847 s8 val_2t; 1848 u32 reg; 1849 u8 i; 1850 1851 if (pw_ofst < -32 || pw_ofst > 31) { 1852 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1853 return; 1854 } 1855 val_1t = pw_ofst << 2; 1856 pw_ofst_2tx = max(pw_ofst - 3, -32); 1857 val_2t = pw_ofst_2tx << 2; 1858 1859 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t); 1860 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t); 1861 1862 for (i = 0; i < 4; i++) { 1863 /* 1TX */ 1864 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1865 rtw89_write32_mask(rtwdev, reg, 1866 B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i), 1867 val_1t); 1868 /* 2TX */ 1869 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1870 rtw89_write32_mask(rtwdev, reg, 1871 B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i), 1872 val_2t); 1873 } 1874} 1875 1876static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev, 1877 enum rtw89_phy_idx phy_idx) 1878{ 1879 static const u32 addr[RF_PATH_NUM_8852C] = {0x5800, 0x7800}; 1880 const u32 mask = 0x7FFFFFF; 1881 const u8 ofst_ofdm = 0x4; 1882 const u8 ofst_cck = 0x8; 1883 s16 ref_ofdm = 0; 1884 s16 ref_cck = 0; 1885 u32 val; 1886 u8 i; 1887 1888 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1889 1890 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1891 GENMASK(27, 10), 0x0); 1892 1893 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1894 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1895 1896 for (i = 0; i < RF_PATH_NUM_8852C; i++) 1897 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1898 phy_idx); 1899 1900 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1901 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1902 1903 for (i = 0; i < RF_PATH_NUM_8852C; i++) 1904 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1905 phy_idx); 1906} 1907 1908static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 1909 const struct rtw89_chan *chan, 1910 u8 tx_shape_idx, 1911 enum rtw89_phy_idx phy_idx) 1912{ 1913#define __DFIR_CFG_MASK 0xffffff 1914#define __DFIR_CFG_NR 8 1915#define __DECL_DFIR_VAR(_prefix, _name, _val...) \ 1916 static const u32 _prefix ## _ ## _name[] = {_val}; \ 1917 static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR) 1918#define __DECL_DFIR_PARAM(_name, _val...) __DECL_DFIR_VAR(param, _name, _val) 1919#define __DECL_DFIR_ADDR(_name, _val...) __DECL_DFIR_VAR(addr, _name, _val) 1920 1921 __DECL_DFIR_PARAM(flat, 1922 0x003D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 1923 0x00F86F9A, 0x00FAEF92, 0x00FE5FCC, 0x00FFDFF5); 1924 __DECL_DFIR_PARAM(sharp, 1925 0x003D83FF, 0x002C636A, 0x0013F204, 0x00008090, 1926 0x00F87FB0, 0x00F99F83, 0x00FDBFBA, 0x00003FF5); 1927 __DECL_DFIR_PARAM(sharp_14, 1928 0x003B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 1929 0x00FD8F92, 0x0002D011, 0x0001C02C, 0x00FFF00A); 1930 __DECL_DFIR_ADDR(filter, 1931 0x45BC, 0x45CC, 0x45D0, 0x45D4, 0x45D8, 0x45C0, 1932 0x45C4, 0x45C8); 1933 u8 ch = chan->channel; 1934 const u32 *param; 1935 int i; 1936 1937 if (ch > 14) { 1938 rtw89_warn(rtwdev, 1939 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 1940 return; 1941 } 1942 1943 if (ch == 14) 1944 param = param_sharp_14; 1945 else 1946 param = tx_shape_idx == 0 ? param_flat : param_sharp; 1947 1948 for (i = 0; i < __DFIR_CFG_NR; i++) { 1949 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1950 "set tx shape dfir: 0x%x: 0x%x\n", addr_filter[i], 1951 param[i]); 1952 rtw89_phy_write32_idx(rtwdev, addr_filter[i], __DFIR_CFG_MASK, 1953 param[i], phy_idx); 1954 } 1955 1956#undef __DECL_DFIR_ADDR 1957#undef __DECL_DFIR_PARAM 1958#undef __DECL_DFIR_VAR 1959#undef __DFIR_CFG_NR 1960#undef __DFIR_CFG_MASK 1961} 1962 1963static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev, 1964 const struct rtw89_chan *chan, 1965 enum rtw89_phy_idx phy_idx) 1966{ 1967 u8 band = chan->band_type; 1968 u8 regd = rtw89_regd_get(rtwdev, band); 1969 u8 tx_shape_cck = rtw89_8852c_tx_shape[band][RTW89_RS_CCK][regd]; 1970 u8 tx_shape_ofdm = rtw89_8852c_tx_shape[band][RTW89_RS_OFDM][regd]; 1971 1972 if (band == RTW89_BAND_2G) 1973 rtw8852c_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); 1974 1975 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 1976 (enum rtw89_mac_idx)phy_idx, 1977 tx_shape_ofdm); 1978} 1979 1980static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev, 1981 const struct rtw89_chan *chan, 1982 enum rtw89_phy_idx phy_idx) 1983{ 1984 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1985 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1986 rtw8852c_set_tx_shape(rtwdev, chan, phy_idx); 1987 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1988 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1989} 1990 1991static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1992 enum rtw89_phy_idx phy_idx) 1993{ 1994 rtw8852c_set_txpwr_ref(rtwdev, phy_idx); 1995} 1996 1997static void 1998rtw8852c_init_tssi_ctrl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1999{ 2000 static const struct rtw89_reg2_def ctrl_ini[] = { 2001 {0xD938, 0x00010100}, 2002 {0xD93C, 0x0500D500}, 2003 {0xD940, 0x00000500}, 2004 {0xD944, 0x00000005}, 2005 {0xD94C, 0x00220000}, 2006 {0xD950, 0x00030000}, 2007 }; 2008 u32 addr; 2009 int i; 2010 2011 for (addr = R_AX_TSSI_CTRL_HEAD; addr <= R_AX_TSSI_CTRL_TAIL; addr += 4) 2012 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 2013 2014 for (i = 0; i < ARRAY_SIZE(ctrl_ini); i++) 2015 rtw89_mac_txpwr_write32(rtwdev, phy_idx, ctrl_ini[i].addr, 2016 ctrl_ini[i].data); 2017 2018 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 2019 (enum rtw89_mac_idx)phy_idx, 2020 RTW89_TSSI_BANDEDGE_FLAT); 2021} 2022 2023static int 2024rtw8852c_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2025{ 2026 int ret; 2027 2028 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 2029 if (ret) 2030 return ret; 2031 2032 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 2033 if (ret) 2034 return ret; 2035 2036 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 2037 if (ret) 2038 return ret; 2039 2040 rtw8852c_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 2041 RTW89_MAC_1 : 2042 RTW89_MAC_0); 2043 rtw8852c_init_tssi_ctrl(rtwdev, phy_idx); 2044 2045 return 0; 2046} 2047 2048static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path) 2049{ 2050 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2051 u8 band = chan->band_type; 2052 u32 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 2053 u32 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 2054 2055 if (rtwdev->dbcc_en) { 2056 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1); 2057 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2, 2058 RTW89_PHY_1); 2059 2060 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2061 1); 2062 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2063 1); 2064 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2, 2065 RTW89_PHY_1); 2066 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2, 2067 RTW89_PHY_1); 2068 2069 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2070 B_RXHT_MCS_LIMIT, 0); 2071 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2072 B_RXVHT_MCS_LIMIT, 0); 2073 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2074 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2075 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2076 2077 rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT, 2078 B_RXHT_MCS_LIMIT, 0, RTW89_PHY_1); 2079 rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT, 2080 B_RXVHT_MCS_LIMIT, 0, RTW89_PHY_1); 2081 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1, 2082 RTW89_PHY_1); 2083 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0, 2084 RTW89_PHY_1); 2085 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0, 2086 RTW89_PHY_1); 2087 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 2088 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 2089 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 2090 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 2091 } else { 2092 if (rx_path == RF_PATH_A) { 2093 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2094 B_ANT_RX_SEG0, 1); 2095 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2096 B_ANT_RX_1RCCA_SEG0, 1); 2097 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2098 B_ANT_RX_1RCCA_SEG1, 1); 2099 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2100 B_RXHT_MCS_LIMIT, 0); 2101 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2102 B_RXVHT_MCS_LIMIT, 0); 2103 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2104 0); 2105 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2106 0); 2107 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2108 rst_mask0, 1); 2109 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2110 rst_mask0, 3); 2111 } else if (rx_path == RF_PATH_B) { 2112 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2113 B_ANT_RX_SEG0, 2); 2114 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2115 B_ANT_RX_1RCCA_SEG0, 2); 2116 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2117 B_ANT_RX_1RCCA_SEG1, 2); 2118 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2119 B_RXHT_MCS_LIMIT, 0); 2120 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2121 B_RXVHT_MCS_LIMIT, 0); 2122 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2123 0); 2124 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2125 0); 2126 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2127 rst_mask1, 1); 2128 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2129 rst_mask1, 3); 2130 } else { 2131 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2132 B_ANT_RX_SEG0, 3); 2133 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2134 B_ANT_RX_1RCCA_SEG0, 3); 2135 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2136 B_ANT_RX_1RCCA_SEG1, 3); 2137 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2138 B_RXHT_MCS_LIMIT, 1); 2139 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2140 B_RXVHT_MCS_LIMIT, 1); 2141 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2142 1); 2143 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2144 1); 2145 rtw8852c_ctrl_btg(rtwdev, band == RTW89_BAND_2G); 2146 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2147 rst_mask0, 1); 2148 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2149 rst_mask0, 3); 2150 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2151 rst_mask1, 1); 2152 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2153 rst_mask1, 3); 2154 } 2155 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2156 } 2157} 2158 2159static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 2160 enum rtw89_mac_idx mac_idx) 2161{ 2162 struct rtw89_reg2_def path_com[] = { 2163 {R_AX_PATH_COM0, AX_PATH_COM0_DFVAL}, 2164 {R_AX_PATH_COM1, AX_PATH_COM1_DFVAL}, 2165 {R_AX_PATH_COM2, AX_PATH_COM2_DFVAL}, 2166 {R_AX_PATH_COM3, AX_PATH_COM3_DFVAL}, 2167 {R_AX_PATH_COM4, AX_PATH_COM4_DFVAL}, 2168 {R_AX_PATH_COM5, AX_PATH_COM5_DFVAL}, 2169 {R_AX_PATH_COM6, AX_PATH_COM6_DFVAL}, 2170 {R_AX_PATH_COM7, AX_PATH_COM7_DFVAL}, 2171 {R_AX_PATH_COM8, AX_PATH_COM8_DFVAL}, 2172 {R_AX_PATH_COM9, AX_PATH_COM9_DFVAL}, 2173 {R_AX_PATH_COM10, AX_PATH_COM10_DFVAL}, 2174 {R_AX_PATH_COM11, AX_PATH_COM11_DFVAL}, 2175 }; 2176 u32 addr; 2177 u32 reg; 2178 u8 cr_size = ARRAY_SIZE(path_com); 2179 u8 i = 0; 2180 2181 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0); 2182 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1); 2183 2184 for (addr = R_AX_MACID_ANT_TABLE; 2185 addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) { 2186 reg = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); 2187 rtw89_write32(rtwdev, reg, 0); 2188 } 2189 2190 if (tx_path == RF_A) { 2191 path_com[0].data = AX_PATH_COM0_PATHA; 2192 path_com[1].data = AX_PATH_COM1_PATHA; 2193 path_com[2].data = AX_PATH_COM2_PATHA; 2194 path_com[7].data = AX_PATH_COM7_PATHA; 2195 path_com[8].data = AX_PATH_COM8_PATHA; 2196 } else if (tx_path == RF_B) { 2197 path_com[0].data = AX_PATH_COM0_PATHB; 2198 path_com[1].data = AX_PATH_COM1_PATHB; 2199 path_com[2].data = AX_PATH_COM2_PATHB; 2200 path_com[7].data = AX_PATH_COM7_PATHB; 2201 path_com[8].data = AX_PATH_COM8_PATHB; 2202 } else if (tx_path == RF_AB) { 2203 path_com[0].data = AX_PATH_COM0_PATHAB; 2204 path_com[1].data = AX_PATH_COM1_PATHAB; 2205 path_com[2].data = AX_PATH_COM2_PATHAB; 2206 path_com[7].data = AX_PATH_COM7_PATHAB; 2207 path_com[8].data = AX_PATH_COM8_PATHAB; 2208 } else { 2209 rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path); 2210 return; 2211 } 2212 2213 for (i = 0; i < cr_size; i++) { 2214 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n", 2215 path_com[i].addr, path_com[i].data); 2216 reg = rtw89_mac_reg_by_idx(rtwdev, path_com[i].addr, mac_idx); 2217 rtw89_write32(rtwdev, reg, path_com[i].data); 2218 } 2219} 2220 2221static void rtw8852c_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en) 2222{ 2223 if (bt_en) { 2224 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2225 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x3); 2226 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2227 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x3); 2228 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2229 B_PATH0_RXBB_MSK_V1, 0xf); 2230 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2231 B_PATH1_RXBB_MSK_V1, 0xf); 2232 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2233 B_PATH0_G_LNA6_OP1DB_V1, 0x80); 2234 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2235 B_PATH1_G_LNA6_OP1DB_V1, 0x80); 2236 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2237 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80); 2238 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2239 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x80); 2240 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2241 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x80); 2242 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2243 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x80); 2244 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2245 B_PATH0_BT_BACKOFF_V1, 0x780D1E); 2246 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2247 B_PATH1_BT_BACKOFF_V1, 0x780D1E); 2248 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2249 B_P0_BACKOFF_IBADC_V1, 0x34); 2250 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2251 B_P1_BACKOFF_IBADC_V1, 0x34); 2252 } else { 2253 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2254 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x0); 2255 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2256 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x0); 2257 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2258 B_PATH0_RXBB_MSK_V1, 0x60); 2259 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2260 B_PATH1_RXBB_MSK_V1, 0x60); 2261 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2262 B_PATH0_G_LNA6_OP1DB_V1, 0x1a); 2263 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2264 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2265 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2266 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2267 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2268 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2269 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2270 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2271 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2272 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2273 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2274 B_PATH0_BT_BACKOFF_V1, 0x79E99E); 2275 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2276 B_PATH1_BT_BACKOFF_V1, 0x79E99E); 2277 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2278 B_P0_BACKOFF_IBADC_V1, 0x26); 2279 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2280 B_P1_BACKOFF_IBADC_V1, 0x26); 2281 } 2282} 2283 2284static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 2285{ 2286 struct rtw89_hal *hal = &rtwdev->hal; 2287 2288 rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB); 2289 2290 if (hal->rx_nss == 1) { 2291 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2292 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2293 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2294 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2295 } else { 2296 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 2297 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 2298 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 2299 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 2300 } 2301} 2302 2303static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 2304{ 2305 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2306 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 2307 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2308 2309 fsleep(200); 2310 2311 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 2312} 2313 2314static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev) 2315{ 2316 struct rtw89_btc *btc = &rtwdev->btc; 2317 struct rtw89_btc_module *module = &btc->mdinfo; 2318 2319 module->rfe_type = rtwdev->efuse.rfe_type; 2320 module->cv = rtwdev->hal.cv; 2321 module->bt_solo = 0; 2322 module->switch_type = BTC_SWITCH_INTERNAL; 2323 2324 if (module->rfe_type > 0) 2325 module->ant.num = (module->rfe_type % 2 ? 2 : 3); 2326 else 2327 module->ant.num = 2; 2328 2329 module->ant.diversity = 0; 2330 module->ant.isolation = 10; 2331 2332 if (module->ant.num == 3) { 2333 module->ant.type = BTC_ANT_DEDICATED; 2334 module->bt_pos = BTC_BT_ALONE; 2335 } else { 2336 module->ant.type = BTC_ANT_SHARED; 2337 module->bt_pos = BTC_BT_BTG; 2338 } 2339} 2340 2341static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 2342{ 2343 if (btg) { 2344 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2345 B_PATH0_BT_SHARE_V1, 0x1); 2346 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2347 B_PATH0_BTG_PATH_V1, 0x0); 2348 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2349 B_PATH1_G_LNA6_OP1DB_V1, 0x20); 2350 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2351 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); 2352 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2353 B_PATH1_BT_SHARE_V1, 0x1); 2354 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2355 B_PATH1_BTG_PATH_V1, 0x1); 2356 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 2357 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1); 2358 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2); 2359 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2360 B_BT_DYN_DC_EST_EN_MSK, 0x1); 2361 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2362 0x1); 2363 } else { 2364 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2365 B_PATH0_BT_SHARE_V1, 0x0); 2366 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2367 B_PATH0_BTG_PATH_V1, 0x0); 2368 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2369 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2370 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2371 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2372 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2373 B_PATH1_BT_SHARE_V1, 0x0); 2374 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2375 B_PATH1_BTG_PATH_V1, 0x0); 2376 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 2377 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 2378 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0); 2379 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0); 2380 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2381 B_BT_DYN_DC_EST_EN_MSK, 0x0); 2382 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2383 0x0); 2384 } 2385} 2386 2387static 2388void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 2389{ 2390 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); 2391 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 2392 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 2393 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); 2394} 2395 2396static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev) 2397{ 2398 struct rtw89_btc *btc = &rtwdev->btc; 2399 struct rtw89_btc_module *module = &btc->mdinfo; 2400 const struct rtw89_chip_info *chip = rtwdev->chip; 2401 const struct rtw89_mac_ax_coex coex_params = { 2402 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 2403 .direction = RTW89_MAC_AX_COEX_INNER, 2404 }; 2405 2406 /* PTA init */ 2407 rtw89_mac_coex_init_v1(rtwdev, &coex_params); 2408 2409 /* set WL Tx response = Hi-Pri */ 2410 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 2411 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 2412 2413 /* set rf gnt debug off */ 2414 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); 2415 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); 2416 2417 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 2418 if (module->ant.type == BTC_ANT_SHARED) { 2419 rtw8852c_set_trx_mask(rtwdev, 2420 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 2421 rtw8852c_set_trx_mask(rtwdev, 2422 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 2423 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 2424 rtw8852c_set_trx_mask(rtwdev, 2425 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 2426 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 2427 rtw8852c_set_trx_mask(rtwdev, 2428 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 2429 rtw8852c_set_trx_mask(rtwdev, 2430 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 2431 } 2432 2433 /* set PTA break table */ 2434 rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM); 2435 2436 /* enable BT counter 0xda10[1:0] = 2b'11 */ 2437 rtw89_write32_set(rtwdev, 2438 R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN | 2439 B_AX_BT_CNT_RST_V1); 2440 btc->cx.wl.status.map.init_ok = true; 2441} 2442 2443static 2444void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 2445{ 2446 u32 bitmap = 0; 2447 u32 reg = 0; 2448 2449 switch (map) { 2450 case BTC_PRI_MASK_TX_RESP: 2451 reg = R_BTC_COEX_WL_REQ; 2452 bitmap = B_BTC_RSP_ACK_HI; 2453 break; 2454 case BTC_PRI_MASK_BEACON: 2455 reg = R_BTC_COEX_WL_REQ; 2456 bitmap = B_BTC_TX_BCN_HI; 2457 break; 2458 default: 2459 return; 2460 } 2461 2462 if (state) 2463 rtw89_write32_set(rtwdev, reg, bitmap); 2464 else 2465 rtw89_write32_clr(rtwdev, reg, bitmap); 2466} 2467 2468union rtw8852c_btc_wl_txpwr_ctrl { 2469 u32 txpwr_val; 2470 struct { 2471 union { 2472 u16 ctrl_all_time; 2473 struct { 2474 s16 data:9; 2475 u16 rsvd:6; 2476 u16 flag:1; 2477 } all_time; 2478 }; 2479 union { 2480 u16 ctrl_gnt_bt; 2481 struct { 2482 s16 data:9; 2483 u16 rsvd:7; 2484 } gnt_bt; 2485 }; 2486 }; 2487} __packed; 2488 2489static void 2490rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 2491{ 2492 union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 2493 s32 val; 2494 2495#define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 2496do { \ 2497 u32 _wrt = FIELD_PREP(_msk, _val); \ 2498 BUILD_BUG_ON((_msk & _en) != 0); \ 2499 if (_cond) \ 2500 _wrt |= _en; \ 2501 else \ 2502 _wrt &= ~_en; \ 2503 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 2504 _msk | _en, _wrt); \ 2505} while (0) 2506 2507 switch (arg.ctrl_all_time) { 2508 case 0xffff: 2509 val = 0; 2510 break; 2511 default: 2512 val = arg.all_time.data; 2513 break; 2514 } 2515 2516 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 2517 val, B_AX_FORCE_PWR_BY_RATE_EN, 2518 arg.ctrl_all_time != 0xffff); 2519 2520 switch (arg.ctrl_gnt_bt) { 2521 case 0xffff: 2522 val = 0; 2523 break; 2524 default: 2525 val = arg.gnt_bt.data; 2526 break; 2527 } 2528 2529 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 2530 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 2531 2532#undef __write_ctrl 2533} 2534 2535static 2536s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 2537{ 2538 /* +6 for compensate offset */ 2539 return clamp_t(s8, val + 6, -100, 0) + 100; 2540} 2541 2542static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_ul[] = { 2543 {255, 0, 0, 7}, /* 0 -> original */ 2544 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 2545 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2546 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2547 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2548 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2549 {6, 1, 0, 7}, 2550 {13, 1, 0, 7}, 2551 {13, 1, 0, 7} 2552}; 2553 2554static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_dl[] = { 2555 {255, 0, 0, 7}, /* 0 -> original */ 2556 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 2557 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2558 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2559 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2560 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2561 {255, 1, 0, 7}, 2562 {255, 1, 0, 7}, 2563 {255, 1, 0, 7} 2564}; 2565 2566static const u8 rtw89_btc_8852c_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 2567static const u8 rtw89_btc_8852c_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 2568 2569static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = { 2570 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda00), 2571 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda04), 2572 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 2573 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 2574 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 2575 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda38), 2576 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda44), 2577 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda48), 2578 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 2579 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 2580 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 2581 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 2582 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4aa4), 2583 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4778), 2584 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x476c), 2585}; 2586 2587static 2588void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2589{ 2590 /* Feature move to firmware */ 2591} 2592 2593static 2594void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2595{ 2596 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2597 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2598 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620); 2599 2600 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2601 if (state) 2602 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2603 RFREG_MASK, 0x179c); 2604 else 2605 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2606 RFREG_MASK, 0x208); 2607 2608 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2609} 2610 2611static void rtw8852c_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 2612{ 2613 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2614 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2615 * To improve BT ACI in co-rx 2616 */ 2617 2618 switch (level) { 2619 case 0: /* default */ 2620 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2621 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2622 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2623 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2624 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2625 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2626 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2627 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2628 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2629 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2630 break; 2631 case 1: /* Fix LNA2=5 */ 2632 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2633 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2634 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2635 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2636 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2637 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2638 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2639 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2640 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2641 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2642 break; 2643 } 2644} 2645 2646static void rtw8852c_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2647{ 2648 struct rtw89_btc *btc = &rtwdev->btc; 2649 2650 switch (level) { 2651 case 0: /* original */ 2652 default: 2653 rtw8852c_bb_ctrl_btc_preagc(rtwdev, false); 2654 btc->dm.wl_lna2 = 0; 2655 break; 2656 case 1: /* for FDD free-run */ 2657 rtw8852c_bb_ctrl_btc_preagc(rtwdev, true); 2658 btc->dm.wl_lna2 = 0; 2659 break; 2660 case 2: /* for BTG Co-Rx*/ 2661 rtw8852c_bb_ctrl_btc_preagc(rtwdev, false); 2662 btc->dm.wl_lna2 = 1; 2663 break; 2664 } 2665 2666 rtw8852c_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2667} 2668 2669static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2670 struct rtw89_rx_phy_ppdu *phy_ppdu, 2671 struct ieee80211_rx_status *status) 2672{ 2673 u8 chan_idx = phy_ppdu->chan_idx; 2674 enum nl80211_band band; 2675 u8 ch; 2676 2677 if (chan_idx == 0) 2678 return; 2679 2680 rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band); 2681 status->freq = ieee80211_channel_to_frequency(ch, band); 2682 status->band = band; 2683} 2684 2685static void rtw8852c_query_ppdu(struct rtw89_dev *rtwdev, 2686 struct rtw89_rx_phy_ppdu *phy_ppdu, 2687 struct ieee80211_rx_status *status) 2688{ 2689 u8 path; 2690 u8 *rx_power = phy_ppdu->rssi; 2691 2692 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2693 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2694 status->chains |= BIT(path); 2695 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2696 } 2697 if (phy_ppdu->valid) 2698 rtw8852c_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2699} 2700 2701static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2702{ 2703 int ret; 2704 2705 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2706 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2707 2708 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2709 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2710 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2711 2712 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1); 2713 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1); 2714 2715 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK); 2716 if (ret) 2717 return ret; 2718 2719 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK); 2720 if (ret) 2721 return ret; 2722 2723 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK); 2724 if (ret) 2725 return ret; 2726 2727 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK); 2728 if (ret) 2729 return ret; 2730 2731 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK); 2732 if (ret) 2733 return ret; 2734 2735 return 0; 2736} 2737 2738static int rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2739{ 2740 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2741 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2742 2743 return 0; 2744} 2745 2746#ifdef CONFIG_PM 2747static const struct wiphy_wowlan_support rtw_wowlan_stub_8852c = { 2748 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2749 .n_patterns = RTW89_MAX_PATTERN_NUM, 2750 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2751 .pattern_min_len = 1, 2752}; 2753#endif 2754 2755static const struct rtw89_chip_ops rtw8852c_chip_ops = { 2756 .enable_bb_rf = rtw8852c_mac_enable_bb_rf, 2757 .disable_bb_rf = rtw8852c_mac_disable_bb_rf, 2758 .bb_reset = rtw8852c_bb_reset, 2759 .bb_sethw = rtw8852c_bb_sethw, 2760 .read_rf = rtw89_phy_read_rf_v1, 2761 .write_rf = rtw89_phy_write_rf_v1, 2762 .set_channel = rtw8852c_set_channel, 2763 .set_channel_help = rtw8852c_set_channel_help, 2764 .read_efuse = rtw8852c_read_efuse, 2765 .read_phycap = rtw8852c_read_phycap, 2766 .fem_setup = NULL, 2767 .rfe_gpio = NULL, 2768 .rfk_init = rtw8852c_rfk_init, 2769 .rfk_channel = rtw8852c_rfk_channel, 2770 .rfk_band_changed = rtw8852c_rfk_band_changed, 2771 .rfk_scan = rtw8852c_rfk_scan, 2772 .rfk_track = rtw8852c_rfk_track, 2773 .power_trim = rtw8852c_power_trim, 2774 .set_txpwr = rtw8852c_set_txpwr, 2775 .set_txpwr_ctrl = rtw8852c_set_txpwr_ctrl, 2776 .init_txpwr_unit = rtw8852c_init_txpwr_unit, 2777 .get_thermal = rtw8852c_get_thermal, 2778 .ctrl_btg = rtw8852c_ctrl_btg, 2779 .query_ppdu = rtw8852c_query_ppdu, 2780 .bb_ctrl_btc_preagc = rtw8852c_bb_ctrl_btc_preagc, 2781 .cfg_txrx_path = rtw8852c_bb_cfg_txrx_path, 2782 .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset, 2783 .pwr_on_func = rtw8852c_pwr_on_func, 2784 .pwr_off_func = rtw8852c_pwr_off_func, 2785 .query_rxdesc = rtw89_core_query_rxdesc, 2786 .fill_txdesc = rtw89_core_fill_txdesc_v1, 2787 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1, 2788 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1, 2789 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v1, 2790 .stop_sch_tx = rtw89_mac_stop_sch_tx_v1, 2791 .resume_sch_tx = rtw89_mac_resume_sch_tx_v1, 2792 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v1, 2793 2794 .btc_set_rfe = rtw8852c_btc_set_rfe, 2795 .btc_init_cfg = rtw8852c_btc_init_cfg, 2796 .btc_set_wl_pri = rtw8852c_btc_set_wl_pri, 2797 .btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl, 2798 .btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi, 2799 .btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt, 2800 .btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby, 2801 .btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain, 2802 .btc_set_policy = rtw89_btc_set_policy_v1, 2803}; 2804 2805const struct rtw89_chip_info rtw8852c_chip_info = { 2806 .chip_id = RTL8852C, 2807 .chip_gen = RTW89_CHIP_AX, 2808 .ops = &rtw8852c_chip_ops, 2809 .mac_def = &rtw89_mac_gen_ax, 2810 .phy_def = &rtw89_phy_gen_ax, 2811 .fw_basename = RTW8852C_FW_BASENAME, 2812 .fw_format_max = RTW8852C_FW_FORMAT_MAX, 2813 .try_ce_fw = false, 2814 .needed_fw_elms = 0, 2815 .fifo_size = 458752, 2816 .small_fifo_size = false, 2817 .dle_scc_rsvd_size = 0, 2818 .max_amsdu_limit = 8000, 2819 .dis_2g_40m_ul_ofdma = false, 2820 .rsvd_ple_ofst = 0x6f800, 2821 .hfc_param_ini = rtw8852c_hfc_param_ini_pcie, 2822 .dle_mem = rtw8852c_dle_mem_pcie, 2823 .wde_qempty_acq_num = 16, 2824 .wde_qempty_mgq_sel = 16, 2825 .rf_base_addr = {0xe000, 0xf000}, 2826 .pwr_on_seq = NULL, 2827 .pwr_off_seq = NULL, 2828 .bb_table = &rtw89_8852c_phy_bb_table, 2829 .bb_gain_table = &rtw89_8852c_phy_bb_gain_table, 2830 .rf_table = {&rtw89_8852c_phy_radiob_table, 2831 &rtw89_8852c_phy_radioa_table,}, 2832 .nctl_table = &rtw89_8852c_phy_nctl_table, 2833 .nctl_post_table = NULL, 2834 .byr_table = &rtw89_8852c_byr_table, 2835 .dflt_parms = &rtw89_8852c_dflt_parms, 2836 .rfe_parms_conf = NULL, 2837 .txpwr_factor_rf = 2, 2838 .txpwr_factor_mac = 1, 2839 .dig_table = NULL, 2840 .dig_regs = &rtw8852c_dig_regs, 2841 .tssi_dbw_table = &rtw89_8852c_tssi_dbw_table, 2842 .support_chanctx_num = 1, 2843 .support_bands = BIT(NL80211_BAND_2GHZ) | 2844 BIT(NL80211_BAND_5GHZ) | 2845 BIT(NL80211_BAND_6GHZ), 2846 .support_bw160 = true, 2847 .support_unii4 = true, 2848 .support_ul_tb_ctrl = false, 2849 .hw_sec_hdr = true, 2850 .rf_path_num = 2, 2851 .tx_nss = 2, 2852 .rx_nss = 2, 2853 .acam_num = 128, 2854 .bcam_num = 20, 2855 .scam_num = 128, 2856 .bacam_num = 8, 2857 .bacam_dynamic_num = 8, 2858 .bacam_ver = RTW89_BACAM_V0_EXT, 2859 .sec_ctrl_efuse_size = 4, 2860 .physical_efuse_size = 1216, 2861 .logical_efuse_size = 2048, 2862 .limit_efuse_size = 1280, 2863 .dav_phy_efuse_size = 96, 2864 .dav_log_efuse_size = 16, 2865 .phycap_addr = 0x590, 2866 .phycap_size = 0x60, 2867 .para_ver = 0x1, 2868 .wlcx_desired = 0x06000000, 2869 .btcx_desired = 0x7, 2870 .scbd = 0x1, 2871 .mailbox = 0x1, 2872 2873 .afh_guard_ch = 6, 2874 .wl_rssi_thres = rtw89_btc_8852c_wl_rssi_thres, 2875 .bt_rssi_thres = rtw89_btc_8852c_bt_rssi_thres, 2876 .rssi_tol = 2, 2877 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852c_mon_reg), 2878 .mon_reg = rtw89_btc_8852c_mon_reg, 2879 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_ul), 2880 .rf_para_ulink = rtw89_btc_8852c_rf_ul, 2881 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_dl), 2882 .rf_para_dlink = rtw89_btc_8852c_rf_dl, 2883 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2884 BIT(RTW89_PS_MODE_CLK_GATED) | 2885 BIT(RTW89_PS_MODE_PWR_GATED), 2886 .low_power_hci_modes = BIT(RTW89_PS_MODE_CLK_GATED) | 2887 BIT(RTW89_PS_MODE_PWR_GATED), 2888 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_V1, 2889 .hci_func_en_addr = R_AX_HCI_FUNC_EN_V1, 2890 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short), 2891 .txwd_body_size = sizeof(struct rtw89_txwd_body_v1), 2892 .h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1, 2893 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2894 .h2c_regs = rtw8852c_h2c_regs, 2895 .c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1, 2896 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2897 .c2h_regs = rtw8852c_c2h_regs, 2898 .page_regs = &rtw8852c_page_regs, 2899 .cfo_src_fd = false, 2900 .cfo_hw_comp = false, 2901 .dcfo_comp = &rtw8852c_dcfo_comp, 2902 .dcfo_comp_sft = 12, 2903 .imr_info = &rtw8852c_imr_info, 2904 .rrsr_cfgs = &rtw8852c_rrsr_cfgs, 2905 .bss_clr_map_reg = R_BSS_CLR_MAP, 2906 .dma_ch_mask = 0, 2907 .edcca_lvl_reg = R_SEG0R_EDCCA_LVL, 2908#ifdef CONFIG_PM 2909 .wowlan_stub = &rtw_wowlan_stub_8852c, 2910#endif 2911 .xtal_info = NULL, 2912}; 2913EXPORT_SYMBOL(rtw8852c_chip_info); 2914 2915MODULE_FIRMWARE(RTW8852C_MODULE_FIRMWARE); 2916MODULE_AUTHOR("Realtek Corporation"); 2917MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver"); 2918MODULE_LICENSE("Dual BSD/GPL"); 2919