1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5#include "coex.h" 6#include "fw.h" 7#include "mac.h" 8#include "phy.h" 9#include "reg.h" 10#include "rtw8852b.h" 11#include "rtw8852b_rfk.h" 12#include "rtw8852b_table.h" 13#include "txrx.h" 14 15#define RTW8852B_FW_FORMAT_MAX 1 16#define RTW8852B_FW_BASENAME "rtw89/rtw8852b_fw" 17#define RTW8852B_MODULE_FIRMWARE \ 18 RTW8852B_FW_BASENAME "-" __stringify(RTW8852B_FW_FORMAT_MAX) ".bin" 19 20static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_pcie[] = { 21 {5, 341, grp_0}, /* ACH 0 */ 22 {5, 341, grp_0}, /* ACH 1 */ 23 {4, 342, grp_0}, /* ACH 2 */ 24 {4, 342, grp_0}, /* ACH 3 */ 25 {0, 0, grp_0}, /* ACH 4 */ 26 {0, 0, grp_0}, /* ACH 5 */ 27 {0, 0, grp_0}, /* ACH 6 */ 28 {0, 0, grp_0}, /* ACH 7 */ 29 {4, 342, grp_0}, /* B0MGQ */ 30 {4, 342, grp_0}, /* B0HIQ */ 31 {0, 0, grp_0}, /* B1MGQ */ 32 {0, 0, grp_0}, /* B1HIQ */ 33 {40, 0, 0} /* FWCMDQ */ 34}; 35 36static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_pcie = { 37 446, /* Group 0 */ 38 0, /* Group 1 */ 39 446, /* Public Max */ 40 0 /* WP threshold */ 41}; 42 43static const struct rtw89_hfc_param_ini rtw8852b_hfc_param_ini_pcie[] = { 44 [RTW89_QTA_SCC] = {rtw8852b_hfc_chcfg_pcie, &rtw8852b_hfc_pubcfg_pcie, 45 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 46 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 47 RTW89_HCIFC_POH}, 48 [RTW89_QTA_INVALID] = {NULL}, 49}; 50 51static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = { 52 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size7, 53 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7, 54 &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18, 55 &rtw89_mac_size.ple_qt58}, 56 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size7, 57 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7, 58 &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18, 59 &rtw89_mac_size.ple_qt_52b_wow}, 60 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9, 61 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4, 62 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 63 &rtw89_mac_size.ple_qt13}, 64 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 65 NULL}, 66}; 67 68static const struct rtw89_reg3_def rtw8852b_pmac_ht20_mcs7_tbl[] = { 69 {0x4580, 0x0000ffff, 0x0}, 70 {0x4580, 0xffff0000, 0x0}, 71 {0x4584, 0x0000ffff, 0x0}, 72 {0x4584, 0xffff0000, 0x0}, 73 {0x4580, 0x0000ffff, 0x1}, 74 {0x4578, 0x00ffffff, 0x2018b}, 75 {0x4570, 0x03ffffff, 0x7}, 76 {0x4574, 0x03ffffff, 0x32407}, 77 {0x45b8, 0x00000010, 0x0}, 78 {0x45b8, 0x00000100, 0x0}, 79 {0x45b8, 0x00000080, 0x0}, 80 {0x45b8, 0x00000008, 0x0}, 81 {0x45a0, 0x0000ff00, 0x0}, 82 {0x45a0, 0xff000000, 0x1}, 83 {0x45a4, 0x0000ff00, 0x2}, 84 {0x45a4, 0xff000000, 0x3}, 85 {0x45b8, 0x00000020, 0x0}, 86 {0x4568, 0xe0000000, 0x0}, 87 {0x45b8, 0x00000002, 0x1}, 88 {0x456c, 0xe0000000, 0x0}, 89 {0x45b4, 0x00006000, 0x0}, 90 {0x45b4, 0x00001800, 0x1}, 91 {0x45b8, 0x00000040, 0x0}, 92 {0x45b8, 0x00000004, 0x0}, 93 {0x45b8, 0x00000200, 0x0}, 94 {0x4598, 0xf8000000, 0x0}, 95 {0x45b8, 0x00100000, 0x0}, 96 {0x45a8, 0x00000fc0, 0x0}, 97 {0x45b8, 0x00200000, 0x0}, 98 {0x45b0, 0x00000038, 0x0}, 99 {0x45b0, 0x000001c0, 0x0}, 100 {0x45a0, 0x000000ff, 0x0}, 101 {0x45b8, 0x00400000, 0x0}, 102 {0x4590, 0x000007ff, 0x0}, 103 {0x45b0, 0x00000e00, 0x0}, 104 {0x45ac, 0x0000001f, 0x0}, 105 {0x45b8, 0x00800000, 0x0}, 106 {0x45a8, 0x0003f000, 0x0}, 107 {0x45b8, 0x01000000, 0x0}, 108 {0x45b0, 0x00007000, 0x0}, 109 {0x45b0, 0x00038000, 0x0}, 110 {0x45a0, 0x00ff0000, 0x0}, 111 {0x45b8, 0x02000000, 0x0}, 112 {0x4590, 0x003ff800, 0x0}, 113 {0x45b0, 0x001c0000, 0x0}, 114 {0x45ac, 0x000003e0, 0x0}, 115 {0x45b8, 0x04000000, 0x0}, 116 {0x45a8, 0x00fc0000, 0x0}, 117 {0x45b8, 0x08000000, 0x0}, 118 {0x45b0, 0x00e00000, 0x0}, 119 {0x45b0, 0x07000000, 0x0}, 120 {0x45a4, 0x000000ff, 0x0}, 121 {0x45b8, 0x10000000, 0x0}, 122 {0x4594, 0x000007ff, 0x0}, 123 {0x45b0, 0x38000000, 0x0}, 124 {0x45ac, 0x00007c00, 0x0}, 125 {0x45b8, 0x20000000, 0x0}, 126 {0x45a8, 0x3f000000, 0x0}, 127 {0x45b8, 0x40000000, 0x0}, 128 {0x45b4, 0x00000007, 0x0}, 129 {0x45b4, 0x00000038, 0x0}, 130 {0x45a4, 0x00ff0000, 0x0}, 131 {0x45b8, 0x80000000, 0x0}, 132 {0x4594, 0x003ff800, 0x0}, 133 {0x45b4, 0x000001c0, 0x0}, 134 {0x4598, 0xf8000000, 0x0}, 135 {0x45b8, 0x00100000, 0x0}, 136 {0x45a8, 0x00000fc0, 0x7}, 137 {0x45b8, 0x00200000, 0x0}, 138 {0x45b0, 0x00000038, 0x0}, 139 {0x45b0, 0x000001c0, 0x0}, 140 {0x45a0, 0x000000ff, 0x0}, 141 {0x45b4, 0x06000000, 0x0}, 142 {0x45b0, 0x00000007, 0x0}, 143 {0x45b8, 0x00080000, 0x0}, 144 {0x45a8, 0x0000003f, 0x0}, 145 {0x457c, 0xffe00000, 0x1}, 146 {0x4530, 0xffffffff, 0x0}, 147 {0x4588, 0x00003fff, 0x0}, 148 {0x4598, 0x000001ff, 0x0}, 149 {0x4534, 0xffffffff, 0x0}, 150 {0x4538, 0xffffffff, 0x0}, 151 {0x453c, 0xffffffff, 0x0}, 152 {0x4588, 0x0fffc000, 0x0}, 153 {0x4598, 0x0003fe00, 0x0}, 154 {0x4540, 0xffffffff, 0x0}, 155 {0x4544, 0xffffffff, 0x0}, 156 {0x4548, 0xffffffff, 0x0}, 157 {0x458c, 0x00003fff, 0x0}, 158 {0x4598, 0x07fc0000, 0x0}, 159 {0x454c, 0xffffffff, 0x0}, 160 {0x4550, 0xffffffff, 0x0}, 161 {0x4554, 0xffffffff, 0x0}, 162 {0x458c, 0x0fffc000, 0x0}, 163 {0x459c, 0x000001ff, 0x0}, 164 {0x4558, 0xffffffff, 0x0}, 165 {0x455c, 0xffffffff, 0x0}, 166 {0x4530, 0xffffffff, 0x4e790001}, 167 {0x4588, 0x00003fff, 0x0}, 168 {0x4598, 0x000001ff, 0x1}, 169 {0x4534, 0xffffffff, 0x0}, 170 {0x4538, 0xffffffff, 0x4b}, 171 {0x45ac, 0x38000000, 0x7}, 172 {0x4588, 0xf0000000, 0x0}, 173 {0x459c, 0x7e000000, 0x0}, 174 {0x45b8, 0x00040000, 0x0}, 175 {0x45b8, 0x00020000, 0x0}, 176 {0x4590, 0xffc00000, 0x0}, 177 {0x45b8, 0x00004000, 0x0}, 178 {0x4578, 0xff000000, 0x0}, 179 {0x45b8, 0x00000400, 0x0}, 180 {0x45b8, 0x00000800, 0x0}, 181 {0x45b8, 0x00001000, 0x0}, 182 {0x45b8, 0x00002000, 0x0}, 183 {0x45b4, 0x00018000, 0x0}, 184 {0x45ac, 0x07800000, 0x0}, 185 {0x45b4, 0x00000600, 0x2}, 186 {0x459c, 0x0001fe00, 0x80}, 187 {0x45ac, 0x00078000, 0x3}, 188 {0x459c, 0x01fe0000, 0x1}, 189}; 190 191static const struct rtw89_reg3_def rtw8852b_btc_preagc_en_defs[] = { 192 {0x46D0, GENMASK(1, 0), 0x3}, 193 {0x4790, GENMASK(1, 0), 0x3}, 194 {0x4AD4, GENMASK(31, 0), 0xf}, 195 {0x4AE0, GENMASK(31, 0), 0xf}, 196 {0x4688, GENMASK(31, 24), 0x80}, 197 {0x476C, GENMASK(31, 24), 0x80}, 198 {0x4694, GENMASK(7, 0), 0x80}, 199 {0x4694, GENMASK(15, 8), 0x80}, 200 {0x4778, GENMASK(7, 0), 0x80}, 201 {0x4778, GENMASK(15, 8), 0x80}, 202 {0x4AE4, GENMASK(23, 0), 0x780D1E}, 203 {0x4AEC, GENMASK(23, 0), 0x780D1E}, 204 {0x469C, GENMASK(31, 26), 0x34}, 205 {0x49F0, GENMASK(31, 26), 0x34}, 206}; 207 208static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_en_defs); 209 210static const struct rtw89_reg3_def rtw8852b_btc_preagc_dis_defs[] = { 211 {0x46D0, GENMASK(1, 0), 0x0}, 212 {0x4790, GENMASK(1, 0), 0x0}, 213 {0x4AD4, GENMASK(31, 0), 0x60}, 214 {0x4AE0, GENMASK(31, 0), 0x60}, 215 {0x4688, GENMASK(31, 24), 0x1a}, 216 {0x476C, GENMASK(31, 24), 0x1a}, 217 {0x4694, GENMASK(7, 0), 0x2a}, 218 {0x4694, GENMASK(15, 8), 0x2a}, 219 {0x4778, GENMASK(7, 0), 0x2a}, 220 {0x4778, GENMASK(15, 8), 0x2a}, 221 {0x4AE4, GENMASK(23, 0), 0x79E99E}, 222 {0x4AEC, GENMASK(23, 0), 0x79E99E}, 223 {0x469C, GENMASK(31, 26), 0x26}, 224 {0x49F0, GENMASK(31, 26), 0x26}, 225}; 226 227static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_dis_defs); 228 229static const u32 rtw8852b_h2c_regs[RTW89_H2CREG_MAX] = { 230 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 231 R_AX_H2CREG_DATA3 232}; 233 234static const u32 rtw8852b_c2h_regs[RTW89_C2HREG_MAX] = { 235 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 236 R_AX_C2HREG_DATA3 237}; 238 239static const struct rtw89_page_regs rtw8852b_page_regs = { 240 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 241 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 242 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 243 .ach_page_info = R_AX_ACH0_PAGE_INFO, 244 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 245 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 246 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 247 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 248 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 249 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 250 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 251 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 252}; 253 254static const struct rtw89_reg_def rtw8852b_dcfo_comp = { 255 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 256}; 257 258static const struct rtw89_imr_info rtw8852b_imr_info = { 259 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 260 .wsec_imr_reg = R_AX_SEC_DEBUG, 261 .wsec_imr_set = B_AX_IMR_ERROR, 262 .mpdu_tx_imr_set = 0, 263 .mpdu_rx_imr_set = 0, 264 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 265 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 266 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 267 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 268 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 269 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 270 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 271 .wde_imr_clr = B_AX_WDE_IMR_CLR, 272 .wde_imr_set = B_AX_WDE_IMR_SET, 273 .ple_imr_clr = B_AX_PLE_IMR_CLR, 274 .ple_imr_set = B_AX_PLE_IMR_SET, 275 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 276 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, 277 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 278 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 279 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 280 .other_disp_imr_set = 0, 281 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 282 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 283 .bbrpt_err_imr_set = 0, 284 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 285 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL, 286 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 287 .cdma_imr_0_reg = R_AX_DLE_CTRL, 288 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 289 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 290 .cdma_imr_1_reg = 0, 291 .cdma_imr_1_clr = 0, 292 .cdma_imr_1_set = 0, 293 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 294 .phy_intf_imr_clr = 0, 295 .phy_intf_imr_set = 0, 296 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 297 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 298 .rmac_imr_set = B_AX_RMAC_IMR_SET, 299 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 300 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 301 .tmac_imr_set = B_AX_TMAC_IMR_SET, 302}; 303 304static const struct rtw89_rrsr_cfgs rtw8852b_rrsr_cfgs = { 305 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 306 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 307}; 308 309static const struct rtw89_dig_regs rtw8852b_dig_regs = { 310 .seg0_pd_reg = R_SEG0R_PD_V1, 311 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 312 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1, 313 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 314 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 315 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 316 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 317 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 318 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 319 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 320 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 321 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 322 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 323 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2, 324 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 325 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2, 326 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 327 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2, 328 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 329 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2, 330 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 331}; 332 333static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_ul[] = { 334 {255, 0, 0, 7}, /* 0 -> original */ 335 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 336 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 337 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 338 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 339 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 340 {6, 1, 0, 7}, 341 {13, 1, 0, 7}, 342 {13, 1, 0, 7} 343}; 344 345static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_dl[] = { 346 {255, 0, 0, 7}, /* 0 -> original */ 347 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 348 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 349 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 350 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 351 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 352 {255, 1, 0, 7}, 353 {255, 1, 0, 7}, 354 {255, 1, 0, 7} 355}; 356 357static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852b_mon_reg[] = { 358 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 359 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 360 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 361 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 362 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 363 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 364 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 365 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 366 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 367 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 368 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 369 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 370 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 371 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738), 372 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688), 373 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694), 374}; 375 376static const u8 rtw89_btc_8852b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40}; 377static const u8 rtw89_btc_8852b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20}; 378 379static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev) 380{ 381 u32 val32; 382 u32 ret; 383 384 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 385 B_AX_AFSM_PCIE_SUS_EN); 386 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 387 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 388 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 389 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 390 391 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 392 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 393 if (ret) 394 return ret; 395 396 rtw89_write32_set(rtwdev, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN); 397 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_AON_OFF_PC_EN, 398 1000, 20000, false, rtwdev, R_AX_AFE_LDO_CTRL); 399 if (ret) 400 return ret; 401 402 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1); 403 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3); 404 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 405 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 406 407 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 408 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 409 if (ret) 410 return ret; 411 412 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 413 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 414 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 415 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 416 417 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 418 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 419 420 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 421 422 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 423 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 424 if (ret) 425 return ret; 426 427 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 428 429 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 430 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 431 if (ret) 432 return ret; 433 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 434 XTAL_SI_OFF_WEI); 435 if (ret) 436 return ret; 437 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 438 XTAL_SI_OFF_EI); 439 if (ret) 440 return ret; 441 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 442 if (ret) 443 return ret; 444 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 445 XTAL_SI_PON_WEI); 446 if (ret) 447 return ret; 448 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 449 XTAL_SI_PON_EI); 450 if (ret) 451 return ret; 452 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 453 if (ret) 454 return ret; 455 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS); 456 if (ret) 457 return ret; 458 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS); 459 if (ret) 460 return ret; 461 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 462 if (ret) 463 return ret; 464 465 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 466 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 467 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 468 469 fsleep(1000); 470 471 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 472 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 473 474 if (!rtwdev->efuse.valid || rtwdev->efuse.power_k_valid) 475 goto func_en; 476 477 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9); 478 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA); 479 480 if (rtwdev->hal.cv == CHIP_CBV) { 481 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 482 rtw89_write16_mask(rtwdev, R_AX_HCI_LDO_CTRL, B_AX_R_AX_VADJ_MASK, 0xA); 483 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 484 } 485 486func_en: 487 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 488 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 489 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 490 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 491 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 492 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 493 B_AX_DMACREG_GCKEN); 494 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 495 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 496 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | 497 B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN | 498 B_AX_RMAC_EN); 499 500 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK, 501 PINMUX_EESK_FUNC_SEL_BT_LOG); 502 503 return 0; 504} 505 506static int rtw8852b_pwr_off_func(struct rtw89_dev *rtwdev) 507{ 508 u32 val32; 509 u32 ret; 510 511 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 512 XTAL_SI_RFC2RF); 513 if (ret) 514 return ret; 515 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 516 if (ret) 517 return ret; 518 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 519 if (ret) 520 return ret; 521 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 522 if (ret) 523 return ret; 524 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 525 if (ret) 526 return ret; 527 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 528 XTAL_SI_SRAM2RFC); 529 if (ret) 530 return ret; 531 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 532 if (ret) 533 return ret; 534 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 535 if (ret) 536 return ret; 537 538 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 539 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 540 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 541 542 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 543 if (ret) 544 return ret; 545 546 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 547 548 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 549 if (ret) 550 return ret; 551 552 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 553 554 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 555 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 556 if (ret) 557 return ret; 558 559 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION); 560 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ); 561 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3); 562 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 563 564 return 0; 565} 566 567static void rtw8852be_efuse_parsing(struct rtw89_efuse *efuse, 568 struct rtw8852b_efuse *map) 569{ 570 ether_addr_copy(efuse->addr, map->e.mac_addr); 571 efuse->rfe_type = map->rfe_type; 572 efuse->xtal_cap = map->xtal_k; 573} 574 575static void rtw8852b_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 576 struct rtw8852b_efuse *map) 577{ 578 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 579 struct rtw8852b_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 580 u8 i, j; 581 582 tssi->thermal[RF_PATH_A] = map->path_a_therm; 583 tssi->thermal[RF_PATH_B] = map->path_b_therm; 584 585 for (i = 0; i < RF_PATH_NUM_8852B; i++) { 586 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 587 sizeof(ofst[i]->cck_tssi)); 588 589 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 590 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 591 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 592 i, j, tssi->tssi_cck[i][j]); 593 594 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 595 sizeof(ofst[i]->bw40_tssi)); 596 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 597 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 598 599 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 600 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 601 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 602 i, j, tssi->tssi_mcs[i][j]); 603 } 604} 605 606static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 607{ 608 if (high) 609 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); 610 if (low) 611 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); 612 613 return data != 0xff; 614} 615 616static void rtw8852b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 617 struct rtw8852b_efuse *map) 618{ 619 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 620 bool valid = false; 621 622 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 623 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 624 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); 625 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 626 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 627 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); 628 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 629 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 630 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); 631 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 632 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 633 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); 634 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 635 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 636 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); 637 638 gain->offset_valid = valid; 639} 640 641static int rtw8852b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) 642{ 643 struct rtw89_efuse *efuse = &rtwdev->efuse; 644 struct rtw8852b_efuse *map; 645 646 map = (struct rtw8852b_efuse *)log_map; 647 648 efuse->country_code[0] = map->country_code[0]; 649 efuse->country_code[1] = map->country_code[1]; 650 rtw8852b_efuse_parsing_tssi(rtwdev, map); 651 rtw8852b_efuse_parsing_gain_offset(rtwdev, map); 652 653 switch (rtwdev->hci.type) { 654 case RTW89_HCI_TYPE_PCIE: 655 rtw8852be_efuse_parsing(efuse, map); 656 break; 657 default: 658 return -EOPNOTSUPP; 659 } 660 661 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 662 663 return 0; 664} 665 666static void rtw8852b_phycap_parsing_power_cal(struct rtw89_dev *rtwdev, u8 *phycap_map) 667{ 668#define PWR_K_CHK_OFFSET 0x5E9 669#define PWR_K_CHK_VALUE 0xAA 670 u32 offset = PWR_K_CHK_OFFSET - rtwdev->chip->phycap_addr; 671 672 if (phycap_map[offset] == PWR_K_CHK_VALUE) 673 rtwdev->efuse.power_k_valid = true; 674} 675 676static void rtw8852b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 677{ 678 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 679 static const u32 tssi_trim_addr[RF_PATH_NUM_8852B] = {0x5D6, 0x5AB}; 680 u32 addr = rtwdev->chip->phycap_addr; 681 bool pg = false; 682 u32 ofst; 683 u8 i, j; 684 685 for (i = 0; i < RF_PATH_NUM_8852B; i++) { 686 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 687 /* addrs are in decreasing order */ 688 ofst = tssi_trim_addr[i] - addr - j; 689 tssi->tssi_trim[i][j] = phycap_map[ofst]; 690 691 if (phycap_map[ofst] != 0xff) 692 pg = true; 693 } 694 } 695 696 if (!pg) { 697 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 698 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 699 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 700 } 701 702 for (i = 0; i < RF_PATH_NUM_8852B; i++) 703 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 704 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 705 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 706 i, j, tssi->tssi_trim[i][j], 707 tssi_trim_addr[i] - j); 708} 709 710static void rtw8852b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 711 u8 *phycap_map) 712{ 713 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 714 static const u32 thm_trim_addr[RF_PATH_NUM_8852B] = {0x5DF, 0x5DC}; 715 u32 addr = rtwdev->chip->phycap_addr; 716 u8 i; 717 718 for (i = 0; i < RF_PATH_NUM_8852B; i++) { 719 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 720 721 rtw89_debug(rtwdev, RTW89_DBG_RFK, 722 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 723 i, info->thermal_trim[i]); 724 725 if (info->thermal_trim[i] != 0xff) 726 info->pg_thermal_trim = true; 727 } 728} 729 730static void rtw8852b_thermal_trim(struct rtw89_dev *rtwdev) 731{ 732#define __thm_setting(raw) \ 733({ \ 734 u8 __v = (raw); \ 735 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 736}) 737 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 738 u8 i, val; 739 740 if (!info->pg_thermal_trim) { 741 rtw89_debug(rtwdev, RTW89_DBG_RFK, 742 "[THERMAL][TRIM] no PG, do nothing\n"); 743 744 return; 745 } 746 747 for (i = 0; i < RF_PATH_NUM_8852B; i++) { 748 val = __thm_setting(info->thermal_trim[i]); 749 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 750 751 rtw89_debug(rtwdev, RTW89_DBG_RFK, 752 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 753 i, val); 754 } 755#undef __thm_setting 756} 757 758static void rtw8852b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 759 u8 *phycap_map) 760{ 761 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 762 static const u32 pabias_trim_addr[RF_PATH_NUM_8852B] = {0x5DE, 0x5DB}; 763 u32 addr = rtwdev->chip->phycap_addr; 764 u8 i; 765 766 for (i = 0; i < RF_PATH_NUM_8852B; i++) { 767 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 768 769 rtw89_debug(rtwdev, RTW89_DBG_RFK, 770 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 771 i, info->pa_bias_trim[i]); 772 773 if (info->pa_bias_trim[i] != 0xff) 774 info->pg_pa_bias_trim = true; 775 } 776} 777 778static void rtw8852b_pa_bias_trim(struct rtw89_dev *rtwdev) 779{ 780 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 781 u8 pabias_2g, pabias_5g; 782 u8 i; 783 784 if (!info->pg_pa_bias_trim) { 785 rtw89_debug(rtwdev, RTW89_DBG_RFK, 786 "[PA_BIAS][TRIM] no PG, do nothing\n"); 787 788 return; 789 } 790 791 for (i = 0; i < RF_PATH_NUM_8852B; i++) { 792 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 793 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 794 795 rtw89_debug(rtwdev, RTW89_DBG_RFK, 796 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 797 i, pabias_2g, pabias_5g); 798 799 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 800 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 801 } 802} 803 804static void rtw8852b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map) 805{ 806 static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = { 807 {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8}, 808 {0x590, 0x58F, 0, 0x58E, 0x58D}, 809 }; 810 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 811 u32 phycap_addr = rtwdev->chip->phycap_addr; 812 bool valid = false; 813 int path, i; 814 u8 data; 815 816 for (path = 0; path < 2; path++) 817 for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) { 818 if (comp_addrs[path][i] == 0) 819 continue; 820 821 data = phycap_map[comp_addrs[path][i] - phycap_addr]; 822 valid |= _decode_efuse_gain(data, NULL, 823 &gain->comp[path][i]); 824 } 825 826 gain->comp_valid = valid; 827} 828 829static int rtw8852b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 830{ 831 rtw8852b_phycap_parsing_power_cal(rtwdev, phycap_map); 832 rtw8852b_phycap_parsing_tssi(rtwdev, phycap_map); 833 rtw8852b_phycap_parsing_thermal_trim(rtwdev, phycap_map); 834 rtw8852b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 835 rtw8852b_phycap_parsing_gain_comp(rtwdev, phycap_map); 836 837 return 0; 838} 839 840static void rtw8852b_power_trim(struct rtw89_dev *rtwdev) 841{ 842 rtw8852b_thermal_trim(rtwdev); 843 rtw8852b_pa_bias_trim(rtwdev); 844} 845 846static void rtw8852b_set_channel_mac(struct rtw89_dev *rtwdev, 847 const struct rtw89_chan *chan, 848 u8 mac_idx) 849{ 850 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 851 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 852 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 853 u8 txsc20 = 0, txsc40 = 0; 854 855 switch (chan->band_width) { 856 case RTW89_CHANNEL_WIDTH_80: 857 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40); 858 fallthrough; 859 case RTW89_CHANNEL_WIDTH_40: 860 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20); 861 break; 862 default: 863 break; 864 } 865 866 switch (chan->band_width) { 867 case RTW89_CHANNEL_WIDTH_80: 868 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 869 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 870 break; 871 case RTW89_CHANNEL_WIDTH_40: 872 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 873 rtw89_write32(rtwdev, sub_carr, txsc20); 874 break; 875 case RTW89_CHANNEL_WIDTH_20: 876 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 877 rtw89_write32(rtwdev, sub_carr, 0); 878 break; 879 default: 880 break; 881 } 882 883 if (chan->channel > 14) { 884 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE); 885 rtw89_write8_set(rtwdev, chk_rate, 886 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 887 } else { 888 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE); 889 rtw89_write8_clr(rtwdev, chk_rate, 890 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 891 } 892} 893 894static const u32 rtw8852b_sco_barker_threshold[14] = { 895 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 896 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 897}; 898 899static const u32 rtw8852b_sco_cck_threshold[14] = { 900 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 901 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 902}; 903 904static void rtw8852b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch) 905{ 906 u8 ch_element = primary_ch - 1; 907 908 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 909 rtw8852b_sco_barker_threshold[ch_element]); 910 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 911 rtw8852b_sco_cck_threshold[ch_element]); 912} 913 914static u8 rtw8852b_sco_mapping(u8 central_ch) 915{ 916 if (central_ch == 1) 917 return 109; 918 else if (central_ch >= 2 && central_ch <= 6) 919 return 108; 920 else if (central_ch >= 7 && central_ch <= 10) 921 return 107; 922 else if (central_ch >= 11 && central_ch <= 14) 923 return 106; 924 else if (central_ch == 36 || central_ch == 38) 925 return 51; 926 else if (central_ch >= 40 && central_ch <= 58) 927 return 50; 928 else if (central_ch >= 60 && central_ch <= 64) 929 return 49; 930 else if (central_ch == 100 || central_ch == 102) 931 return 48; 932 else if (central_ch >= 104 && central_ch <= 126) 933 return 47; 934 else if (central_ch >= 128 && central_ch <= 151) 935 return 46; 936 else if (central_ch >= 153 && central_ch <= 177) 937 return 45; 938 else 939 return 0; 940} 941 942struct rtw8852b_bb_gain { 943 u32 gain_g[BB_PATH_NUM_8852B]; 944 u32 gain_a[BB_PATH_NUM_8852B]; 945 u32 gain_mask; 946}; 947 948static const struct rtw8852b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 949 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 950 .gain_mask = 0x00ff0000 }, 951 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 952 .gain_mask = 0xff000000 }, 953 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 954 .gain_mask = 0x000000ff }, 955 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 956 .gain_mask = 0x0000ff00 }, 957 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 958 .gain_mask = 0x00ff0000 }, 959 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 960 .gain_mask = 0xff000000 }, 961 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 962 .gain_mask = 0x000000ff }, 963}; 964 965static const struct rtw8852b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 966 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 967 .gain_mask = 0x00ff0000 }, 968 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 969 .gain_mask = 0xff000000 }, 970}; 971 972static void rtw8852b_set_gain_error(struct rtw89_dev *rtwdev, 973 enum rtw89_subband subband, 974 enum rtw89_rf_path path) 975{ 976 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 977 u8 gain_band = rtw89_subband_to_bb_gain_band(subband); 978 s32 val; 979 u32 reg; 980 u32 mask; 981 int i; 982 983 for (i = 0; i < LNA_GAIN_NUM; i++) { 984 if (subband == RTW89_CH_2G) 985 reg = bb_gain_lna[i].gain_g[path]; 986 else 987 reg = bb_gain_lna[i].gain_a[path]; 988 989 mask = bb_gain_lna[i].gain_mask; 990 val = gain->lna_gain[gain_band][path][i]; 991 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 992 } 993 994 for (i = 0; i < TIA_GAIN_NUM; i++) { 995 if (subband == RTW89_CH_2G) 996 reg = bb_gain_tia[i].gain_g[path]; 997 else 998 reg = bb_gain_tia[i].gain_a[path]; 999 1000 mask = bb_gain_tia[i].gain_mask; 1001 val = gain->tia_gain[gain_band][path][i]; 1002 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 1003 } 1004} 1005 1006static void rtw8852b_set_gain_offset(struct rtw89_dev *rtwdev, 1007 enum rtw89_subband subband, 1008 enum rtw89_phy_idx phy_idx) 1009{ 1010 static const u32 gain_err_addr[2] = {R_P0_AGC_RSVD, R_P1_AGC_RSVD}; 1011 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1, 1012 R_PATH1_G_TIA1_LNA6_OP1DB_V1}; 1013 struct rtw89_hal *hal = &rtwdev->hal; 1014 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 1015 enum rtw89_gain_offset gain_ofdm_band; 1016 s32 offset_a, offset_b; 1017 s32 offset_ofdm, offset_cck; 1018 s32 tmp; 1019 u8 path; 1020 1021 if (!efuse_gain->comp_valid) 1022 goto next; 1023 1024 for (path = RF_PATH_A; path < BB_PATH_NUM_8852B; path++) { 1025 tmp = efuse_gain->comp[path][subband]; 1026 tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX); 1027 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp); 1028 } 1029 1030next: 1031 if (!efuse_gain->offset_valid) 1032 return; 1033 1034 gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband); 1035 1036 offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; 1037 offset_b = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band]; 1038 1039 tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2)); 1040 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 1041 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp); 1042 1043 tmp = -((offset_b << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2)); 1044 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 1045 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_B], B_PATH0_R_G_OFST_MASK, tmp); 1046 1047 if (hal->antenna_rx == RF_B) { 1048 offset_ofdm = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band]; 1049 offset_cck = -efuse_gain->offset[RF_PATH_B][0]; 1050 } else { 1051 offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; 1052 offset_cck = -efuse_gain->offset[RF_PATH_A][0]; 1053 } 1054 1055 tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0]; 1056 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 1057 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx); 1058 1059 tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0]; 1060 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 1061 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx); 1062 1063 if (subband == RTW89_CH_2G) { 1064 tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1); 1065 tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1); 1066 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST, 1067 B_RX_RPL_OFST_CCK_MASK, tmp); 1068 } 1069} 1070 1071static 1072void rtw8852b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband) 1073{ 1074 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 1075 u8 band = rtw89_subband_to_bb_gain_band(subband); 1076 u32 val; 1077 1078 val = FIELD_PREP(B_P0_RPL1_20_MASK, (gain->rpl_ofst_20[band][RF_PATH_A] + 1079 gain->rpl_ofst_20[band][RF_PATH_B]) / 2) | 1080 FIELD_PREP(B_P0_RPL1_40_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][0] + 1081 gain->rpl_ofst_40[band][RF_PATH_B][0]) / 2) | 1082 FIELD_PREP(B_P0_RPL1_41_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][1] + 1083 gain->rpl_ofst_40[band][RF_PATH_B][1]) / 2); 1084 val >>= B_P0_RPL1_SHIFT; 1085 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val); 1086 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val); 1087 1088 val = FIELD_PREP(B_P0_RTL2_42_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][2] + 1089 gain->rpl_ofst_40[band][RF_PATH_B][2]) / 2) | 1090 FIELD_PREP(B_P0_RTL2_80_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][0] + 1091 gain->rpl_ofst_80[band][RF_PATH_B][0]) / 2) | 1092 FIELD_PREP(B_P0_RTL2_81_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][1] + 1093 gain->rpl_ofst_80[band][RF_PATH_B][1]) / 2) | 1094 FIELD_PREP(B_P0_RTL2_8A_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][10] + 1095 gain->rpl_ofst_80[band][RF_PATH_B][10]) / 2); 1096 rtw89_phy_write32(rtwdev, R_P0_RPL2, val); 1097 rtw89_phy_write32(rtwdev, R_P1_RPL2, val); 1098 1099 val = FIELD_PREP(B_P0_RTL3_82_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][2] + 1100 gain->rpl_ofst_80[band][RF_PATH_B][2]) / 2) | 1101 FIELD_PREP(B_P0_RTL3_83_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][3] + 1102 gain->rpl_ofst_80[band][RF_PATH_B][3]) / 2) | 1103 FIELD_PREP(B_P0_RTL3_84_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][4] + 1104 gain->rpl_ofst_80[band][RF_PATH_B][4]) / 2) | 1105 FIELD_PREP(B_P0_RTL3_89_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][9] + 1106 gain->rpl_ofst_80[band][RF_PATH_B][9]) / 2); 1107 rtw89_phy_write32(rtwdev, R_P0_RPL3, val); 1108 rtw89_phy_write32(rtwdev, R_P1_RPL3, val); 1109} 1110 1111static void rtw8852b_ctrl_ch(struct rtw89_dev *rtwdev, 1112 const struct rtw89_chan *chan, 1113 enum rtw89_phy_idx phy_idx) 1114{ 1115 u8 central_ch = chan->channel; 1116 u8 subband = chan->subband_type; 1117 u8 sco_comp; 1118 bool is_2g = central_ch <= 14; 1119 1120 /* Path A */ 1121 if (is_2g) 1122 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 1123 B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx); 1124 else 1125 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 1126 B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx); 1127 1128 /* Path B */ 1129 if (is_2g) 1130 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1131 B_PATH1_BAND_SEL_MSK_V1, 1, phy_idx); 1132 else 1133 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1134 B_PATH1_BAND_SEL_MSK_V1, 0, phy_idx); 1135 1136 /* SCO compensate FC setting */ 1137 sco_comp = rtw8852b_sco_mapping(central_ch); 1138 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx); 1139 1140 if (chan->band_type == RTW89_BAND_6G) 1141 return; 1142 1143 /* CCK parameters */ 1144 if (central_ch == 14) { 1145 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff); 1146 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de); 1147 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad); 1148 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e); 1149 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92); 1150 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 1151 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 1152 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a); 1153 } else { 1154 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff); 1155 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354); 1156 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 1157 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053); 1158 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a); 1159 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92); 1160 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc); 1161 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5); 1162 } 1163 1164 rtw8852b_set_gain_error(rtwdev, subband, RF_PATH_A); 1165 rtw8852b_set_gain_error(rtwdev, subband, RF_PATH_B); 1166 rtw8852b_set_gain_offset(rtwdev, subband, phy_idx); 1167 rtw8852b_set_rxsc_rpl_comp(rtwdev, subband); 1168} 1169 1170static void rtw8852b_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 1171{ 1172 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; 1173 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 1174 1175 switch (bw) { 1176 case RTW89_CHANNEL_WIDTH_5: 1177 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 1178 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 1179 break; 1180 case RTW89_CHANNEL_WIDTH_10: 1181 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 1182 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 1183 break; 1184 case RTW89_CHANNEL_WIDTH_20: 1185 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1186 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1187 break; 1188 case RTW89_CHANNEL_WIDTH_40: 1189 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1190 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1191 break; 1192 case RTW89_CHANNEL_WIDTH_80: 1193 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1194 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1195 break; 1196 default: 1197 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1198 } 1199} 1200 1201static void rtw8852b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1202 enum rtw89_phy_idx phy_idx) 1203{ 1204 u32 rx_path_0; 1205 1206 switch (bw) { 1207 case RTW89_CHANNEL_WIDTH_5: 1208 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 1209 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx); 1210 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 1211 1212 /*Set RF mode at 3 */ 1213 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 1214 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1215 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 1216 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1217 break; 1218 case RTW89_CHANNEL_WIDTH_10: 1219 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 1220 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx); 1221 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 1222 1223 /*Set RF mode at 3 */ 1224 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 1225 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1226 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 1227 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1228 break; 1229 case RTW89_CHANNEL_WIDTH_20: 1230 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 1231 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 1232 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 1233 1234 /*Set RF mode at 3 */ 1235 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 1236 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1237 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 1238 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1239 break; 1240 case RTW89_CHANNEL_WIDTH_40: 1241 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx); 1242 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 1243 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 1244 pri_ch, phy_idx); 1245 1246 /*Set RF mode at 3 */ 1247 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 1248 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1249 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 1250 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 1251 /*CCK primary channel */ 1252 if (pri_ch == RTW89_SC_20_UPPER) 1253 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 1254 else 1255 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 1256 1257 break; 1258 case RTW89_CHANNEL_WIDTH_80: 1259 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx); 1260 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 1261 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 1262 pri_ch, phy_idx); 1263 1264 /*Set RF mode at A */ 1265 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 1266 B_P0_RFMODE_ORI_RX_ALL, 0xaaa, phy_idx); 1267 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 1268 B_P1_RFMODE_ORI_RX_ALL, 0xaaa, phy_idx); 1269 break; 1270 default: 1271 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1272 pri_ch); 1273 } 1274 1275 rtw8852b_bw_setting(rtwdev, bw, RF_PATH_A); 1276 rtw8852b_bw_setting(rtwdev, bw, RF_PATH_B); 1277 1278 rx_path_0 = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1279 phy_idx); 1280 if (rx_path_0 == 0x1) 1281 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 1282 B_P1_RFMODE_ORI_RX_ALL, 0x111, phy_idx); 1283 else if (rx_path_0 == 0x2) 1284 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 1285 B_P0_RFMODE_ORI_RX_ALL, 0x111, phy_idx); 1286} 1287 1288static void rtw8852b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en) 1289{ 1290 if (cck_en) { 1291 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1292 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1293 } else { 1294 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1295 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1296 } 1297} 1298 1299static void rtw8852b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 1300 enum rtw89_phy_idx phy_idx) 1301{ 1302 u8 pri_ch = chan->pri_ch_idx; 1303 bool mask_5m_low; 1304 bool mask_5m_en; 1305 1306 switch (chan->band_width) { 1307 case RTW89_CHANNEL_WIDTH_40: 1308 /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */ 1309 mask_5m_en = true; 1310 mask_5m_low = pri_ch == RTW89_SC_20_LOWER; 1311 break; 1312 case RTW89_CHANNEL_WIDTH_80: 1313 /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */ 1314 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || 1315 pri_ch == RTW89_SC_20_LOWEST; 1316 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; 1317 break; 1318 default: 1319 mask_5m_en = false; 1320 break; 1321 } 1322 1323 if (!mask_5m_en) { 1324 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0); 1325 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x0); 1326 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, 1327 B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx); 1328 return; 1329 } 1330 1331 if (mask_5m_low) { 1332 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4); 1333 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1); 1334 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0); 1335 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1); 1336 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4); 1337 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1); 1338 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x0); 1339 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x1); 1340 } else { 1341 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4); 1342 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1); 1343 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1); 1344 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0); 1345 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4); 1346 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1); 1347 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x1); 1348 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x0); 1349 } 1350 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, 1351 B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx); 1352} 1353 1354static void rtw8852b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1355{ 1356 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1357 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1358 fsleep(1); 1359 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1360 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); 1361 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1362 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1363 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1364} 1365 1366static void rtw8852b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 1367 enum rtw89_phy_idx phy_idx, bool en) 1368{ 1369 if (en) { 1370 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1371 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1372 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1373 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1374 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1375 if (band == RTW89_BAND_2G) 1376 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0); 1377 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 1378 } else { 1379 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1); 1380 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 1381 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1382 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1383 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1384 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1385 fsleep(1); 1386 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); 1387 } 1388} 1389 1390static void rtw8852b_bb_reset(struct rtw89_dev *rtwdev, 1391 enum rtw89_phy_idx phy_idx) 1392{ 1393 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1394 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1395 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1396 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1397 rtw8852b_bb_reset_all(rtwdev, phy_idx); 1398 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1399 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1400 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1401 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1402} 1403 1404static void rtw8852b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1405 enum rtw89_phy_idx phy_idx) 1406{ 1407 u32 addr; 1408 1409 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1410 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1411 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1412} 1413 1414static void rtw8852b_bb_sethw(struct rtw89_dev *rtwdev) 1415{ 1416 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1417 1418 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1419 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1420 1421 rtw8852b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1422 1423 /* read these registers after loading BB parameters */ 1424 gain->offset_base[RTW89_PHY_0] = 1425 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK); 1426 gain->rssi_base[RTW89_PHY_0] = 1427 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK); 1428} 1429 1430static void rtw8852b_bb_set_pop(struct rtw89_dev *rtwdev) 1431{ 1432 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) 1433 rtw89_phy_write32_clr(rtwdev, R_PKT_CTRL, B_PKT_POP_EN); 1434} 1435 1436static void rtw8852b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 1437 enum rtw89_phy_idx phy_idx) 1438{ 1439 bool cck_en = chan->channel <= 14; 1440 u8 pri_ch_idx = chan->pri_ch_idx; 1441 u8 band = chan->band_type, chan_idx; 1442 1443 if (cck_en) 1444 rtw8852b_ctrl_sco_cck(rtwdev, chan->primary_channel); 1445 1446 rtw8852b_ctrl_ch(rtwdev, chan, phy_idx); 1447 rtw8852b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1448 rtw8852b_ctrl_cck_en(rtwdev, cck_en); 1449 if (chan->band_type == RTW89_BAND_5G) { 1450 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1451 B_PATH0_BT_SHARE_V1, 0x0); 1452 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1453 B_PATH0_BTG_PATH_V1, 0x0); 1454 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 1455 B_PATH1_BT_SHARE_V1, 0x0); 1456 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 1457 B_PATH1_BTG_PATH_V1, 0x0); 1458 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0); 1459 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0); 1460 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1461 B_BT_DYN_DC_EST_EN_MSK, 0x0); 1462 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0); 1463 } 1464 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); 1465 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx); 1466 rtw8852b_5m_mask(rtwdev, chan, phy_idx); 1467 rtw8852b_bb_set_pop(rtwdev); 1468 rtw8852b_bb_reset_all(rtwdev, phy_idx); 1469} 1470 1471static void rtw8852b_set_channel(struct rtw89_dev *rtwdev, 1472 const struct rtw89_chan *chan, 1473 enum rtw89_mac_idx mac_idx, 1474 enum rtw89_phy_idx phy_idx) 1475{ 1476 rtw8852b_set_channel_mac(rtwdev, chan, mac_idx); 1477 rtw8852b_set_channel_bb(rtwdev, chan, phy_idx); 1478 rtw8852b_set_channel_rf(rtwdev, chan, phy_idx); 1479} 1480 1481static void rtw8852b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1482 enum rtw89_rf_path path) 1483{ 1484 static const u32 tssi_trk[2] = {R_P0_TSSI_TRK, R_P1_TSSI_TRK}; 1485 static const u32 ctrl_bbrst[2] = {R_P0_TXPW_RSTB, R_P1_TXPW_RSTB}; 1486 1487 if (en) { 1488 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x0); 1489 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x0); 1490 } else { 1491 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x1); 1492 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x1); 1493 } 1494} 1495 1496static void rtw8852b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1497 u8 phy_idx) 1498{ 1499 if (!rtwdev->dbcc_en) { 1500 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A); 1501 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B); 1502 } else { 1503 if (phy_idx == RTW89_PHY_0) 1504 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A); 1505 else 1506 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B); 1507 } 1508} 1509 1510static void rtw8852b_adc_en(struct rtw89_dev *rtwdev, bool en) 1511{ 1512 if (en) 1513 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0); 1514 else 1515 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf); 1516} 1517 1518static void rtw8852b_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1519 struct rtw89_channel_help_params *p, 1520 const struct rtw89_chan *chan, 1521 enum rtw89_mac_idx mac_idx, 1522 enum rtw89_phy_idx phy_idx) 1523{ 1524 if (enter) { 1525 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL); 1526 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 1527 rtw8852b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0); 1528 rtw8852b_adc_en(rtwdev, false); 1529 fsleep(40); 1530 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 1531 } else { 1532 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 1533 rtw8852b_adc_en(rtwdev, true); 1534 rtw8852b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0); 1535 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 1536 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en); 1537 } 1538} 1539 1540static void rtw8852b_rfk_init(struct rtw89_dev *rtwdev) 1541{ 1542 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1543 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1544 1545 rtw8852b_dpk_init(rtwdev); 1546 rtw8852b_rck(rtwdev); 1547 rtw8852b_dack(rtwdev); 1548 rtw8852b_rx_dck(rtwdev, RTW89_PHY_0); 1549} 1550 1551static void rtw8852b_rfk_channel(struct rtw89_dev *rtwdev) 1552{ 1553 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1554 1555 rtw8852b_rx_dck(rtwdev, phy_idx); 1556 rtw8852b_iqk(rtwdev, phy_idx); 1557 rtw8852b_tssi(rtwdev, phy_idx, true); 1558 rtw8852b_dpk(rtwdev, phy_idx); 1559} 1560 1561static void rtw8852b_rfk_band_changed(struct rtw89_dev *rtwdev, 1562 enum rtw89_phy_idx phy_idx) 1563{ 1564 rtw8852b_tssi_scan(rtwdev, phy_idx); 1565} 1566 1567static void rtw8852b_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1568{ 1569 rtw8852b_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1570} 1571 1572static void rtw8852b_rfk_track(struct rtw89_dev *rtwdev) 1573{ 1574 rtw8852b_dpk_track(rtwdev); 1575} 1576 1577static u32 rtw8852b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1578 enum rtw89_phy_idx phy_idx, s16 ref) 1579{ 1580 const u16 tssi_16dbm_cw = 0x12c; 1581 const u8 base_cw_0db = 0x27; 1582 const s8 ofst_int = 0; 1583 s16 pwr_s10_3; 1584 s16 rf_pwr_cw; 1585 u16 bb_pwr_cw; 1586 u32 pwr_cw; 1587 u32 tssi_ofst_cw; 1588 1589 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1590 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1591 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1592 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1593 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1594 1595 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1596 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1597 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1598 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1599 1600 return FIELD_PREP(B_DPD_TSSI_CW, tssi_ofst_cw) | 1601 FIELD_PREP(B_DPD_PWR_CW, pwr_cw) | 1602 FIELD_PREP(B_DPD_REF, ref); 1603} 1604 1605static void rtw8852b_set_txpwr_ref(struct rtw89_dev *rtwdev, 1606 enum rtw89_phy_idx phy_idx) 1607{ 1608 static const u32 addr[RF_PATH_NUM_8852B] = {0x5800, 0x7800}; 1609 const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF; 1610 const u8 ofst_ofdm = 0x4; 1611 const u8 ofst_cck = 0x8; 1612 const s16 ref_ofdm = 0; 1613 const s16 ref_cck = 0; 1614 u32 val; 1615 u8 i; 1616 1617 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1618 1619 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1620 B_AX_PWR_REF, 0x0); 1621 1622 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1623 val = rtw8852b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1624 1625 for (i = 0; i < RF_PATH_NUM_8852B; i++) 1626 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1627 phy_idx); 1628 1629 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1630 val = rtw8852b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1631 1632 for (i = 0; i < RF_PATH_NUM_8852B; i++) 1633 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1634 phy_idx); 1635} 1636 1637static void rtw8852b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 1638 const struct rtw89_chan *chan, 1639 u8 tx_shape_idx, 1640 enum rtw89_phy_idx phy_idx) 1641{ 1642#define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2)) 1643#define __DFIR_CFG_MASK 0xffffffff 1644#define __DFIR_CFG_NR 8 1645#define __DECL_DFIR_PARAM(_name, _val...) \ 1646 static const u32 param_ ## _name[] = {_val}; \ 1647 static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR) 1648 1649 __DECL_DFIR_PARAM(flat, 1650 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 1651 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5); 1652 __DECL_DFIR_PARAM(sharp, 1653 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090, 1654 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5); 1655 __DECL_DFIR_PARAM(sharp_14, 1656 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 1657 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A); 1658 u8 ch = chan->channel; 1659 const u32 *param; 1660 u32 addr; 1661 int i; 1662 1663 if (ch > 14) { 1664 rtw89_warn(rtwdev, 1665 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 1666 return; 1667 } 1668 1669 if (ch == 14) 1670 param = param_sharp_14; 1671 else 1672 param = tx_shape_idx == 0 ? param_flat : param_sharp; 1673 1674 for (i = 0; i < __DFIR_CFG_NR; i++) { 1675 addr = __DFIR_CFG_ADDR(i); 1676 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1677 "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]); 1678 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i], 1679 phy_idx); 1680 } 1681 1682#undef __DECL_DFIR_PARAM 1683#undef __DFIR_CFG_NR 1684#undef __DFIR_CFG_MASK 1685#undef __DECL_CFG_ADDR 1686} 1687 1688static void rtw8852b_set_tx_shape(struct rtw89_dev *rtwdev, 1689 const struct rtw89_chan *chan, 1690 enum rtw89_phy_idx phy_idx) 1691{ 1692 u8 band = chan->band_type; 1693 u8 regd = rtw89_regd_get(rtwdev, band); 1694 u8 tx_shape_cck = rtw89_8852b_tx_shape[band][RTW89_RS_CCK][regd]; 1695 u8 tx_shape_ofdm = rtw89_8852b_tx_shape[band][RTW89_RS_OFDM][regd]; 1696 1697 if (band == RTW89_BAND_2G) 1698 rtw8852b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); 1699 1700 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG, 1701 tx_shape_ofdm); 1702} 1703 1704static void rtw8852b_set_txpwr(struct rtw89_dev *rtwdev, 1705 const struct rtw89_chan *chan, 1706 enum rtw89_phy_idx phy_idx) 1707{ 1708 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1709 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1710 rtw8852b_set_tx_shape(rtwdev, chan, phy_idx); 1711 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1712 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1713} 1714 1715static void rtw8852b_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1716 enum rtw89_phy_idx phy_idx) 1717{ 1718 rtw8852b_set_txpwr_ref(rtwdev, phy_idx); 1719} 1720 1721static 1722void rtw8852b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1723 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1724{ 1725 u32 reg; 1726 1727 if (pw_ofst < -16 || pw_ofst > 15) { 1728 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1729 return; 1730 } 1731 1732 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx); 1733 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1734 1735 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1736 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst); 1737 1738 pw_ofst = max_t(s8, pw_ofst - 3, -16); 1739 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1740 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst); 1741} 1742 1743static int 1744rtw8852b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1745{ 1746 int ret; 1747 1748 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1749 if (ret) 1750 return ret; 1751 1752 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 1753 if (ret) 1754 return ret; 1755 1756 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1757 if (ret) 1758 return ret; 1759 1760 rtw8852b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 1761 RTW89_MAC_1 : RTW89_MAC_0); 1762 1763 return 0; 1764} 1765 1766void rtw8852b_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1767{ 1768 const struct rtw89_reg3_def *def = rtw8852b_pmac_ht20_mcs7_tbl; 1769 u8 i; 1770 1771 for (i = 0; i < ARRAY_SIZE(rtw8852b_pmac_ht20_mcs7_tbl); i++, def++) 1772 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 1773} 1774 1775static void rtw8852b_stop_pmac_tx(struct rtw89_dev *rtwdev, 1776 struct rtw8852b_bb_pmac_info *tx_info, 1777 enum rtw89_phy_idx idx) 1778{ 1779 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1780 if (tx_info->mode == CONT_TX) 1781 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, idx); 1782 else if (tx_info->mode == PKTS_TX) 1783 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, idx); 1784} 1785 1786static void rtw8852b_start_pmac_tx(struct rtw89_dev *rtwdev, 1787 struct rtw8852b_bb_pmac_info *tx_info, 1788 enum rtw89_phy_idx idx) 1789{ 1790 enum rtw8852b_pmac_mode mode = tx_info->mode; 1791 u32 pkt_cnt = tx_info->tx_cnt; 1792 u16 period = tx_info->period; 1793 1794 if (mode == CONT_TX && !tx_info->is_cck) { 1795 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, idx); 1796 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1797 } else if (mode == PKTS_TX) { 1798 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, idx); 1799 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1800 B_PMAC_TX_PRD_MSK, period, idx); 1801 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1802 pkt_cnt, idx); 1803 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1804 } 1805 1806 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1807 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1808} 1809 1810void rtw8852b_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1811 struct rtw8852b_bb_pmac_info *tx_info, 1812 enum rtw89_phy_idx idx) 1813{ 1814 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1815 1816 if (!tx_info->en_pmac_tx) { 1817 rtw8852b_stop_pmac_tx(rtwdev, tx_info, idx); 1818 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1819 if (chan->band_type == RTW89_BAND_2G) 1820 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1821 return; 1822 } 1823 1824 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1825 1826 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1827 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1828 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, idx); 1829 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1830 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1831 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1832 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1833 1834 rtw8852b_start_pmac_tx(rtwdev, tx_info, idx); 1835} 1836 1837void rtw8852b_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1838 u16 tx_cnt, u16 period, u16 tx_time, 1839 enum rtw89_phy_idx idx) 1840{ 1841 struct rtw8852b_bb_pmac_info tx_info = {0}; 1842 1843 tx_info.en_pmac_tx = enable; 1844 tx_info.is_cck = 0; 1845 tx_info.mode = PKTS_TX; 1846 tx_info.tx_cnt = tx_cnt; 1847 tx_info.period = period; 1848 tx_info.tx_time = tx_time; 1849 1850 rtw8852b_bb_set_pmac_tx(rtwdev, &tx_info, idx); 1851} 1852 1853void rtw8852b_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1854 enum rtw89_phy_idx idx) 1855{ 1856 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1857 1858 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1859 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1860} 1861 1862void rtw8852b_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1863{ 1864 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1865 1866 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1867 1868 if (tx_path == RF_PATH_A) { 1869 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1); 1870 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0); 1871 } else if (tx_path == RF_PATH_B) { 1872 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2); 1873 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0); 1874 } else if (tx_path == RF_PATH_AB) { 1875 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 3); 1876 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4); 1877 } else { 1878 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1879 } 1880} 1881 1882void rtw8852b_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1883 enum rtw89_phy_idx idx, u8 mode) 1884{ 1885 if (mode != 0) 1886 return; 1887 1888 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1889 1890 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1891 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1892 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1893 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1894 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1895 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1896 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1897} 1898 1899void rtw8852b_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 1900 struct rtw8852b_bb_tssi_bak *bak) 1901{ 1902 s32 tmp; 1903 1904 bak->tx_path = rtw89_phy_read32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, idx); 1905 bak->rx_path = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, idx); 1906 bak->p0_rfmode = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, idx); 1907 bak->p0_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, idx); 1908 bak->p1_rfmode = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, idx); 1909 bak->p1_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, idx); 1910 tmp = rtw89_phy_read32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, idx); 1911 bak->tx_pwr = sign_extend32(tmp, 8); 1912} 1913 1914void rtw8852b_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 1915 const struct rtw8852b_bb_tssi_bak *bak) 1916{ 1917 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, bak->tx_path, idx); 1918 if (bak->tx_path == RF_AB) 1919 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x4); 1920 else 1921 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x0); 1922 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, bak->rx_path, idx); 1923 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1924 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, bak->p0_rfmode, idx); 1925 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, bak->p0_rfmode_ftm, idx); 1926 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, bak->p1_rfmode, idx); 1927 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, bak->p1_rfmode_ftm, idx); 1928 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, bak->tx_pwr, idx); 1929} 1930 1931static void rtw8852b_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en) 1932{ 1933 rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852b_btc_preagc_en_defs_tbl : 1934 &rtw8852b_btc_preagc_dis_defs_tbl); 1935} 1936 1937static void rtw8852b_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 1938{ 1939 if (btg) { 1940 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1941 B_PATH0_BT_SHARE_V1, 0x1); 1942 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1943 B_PATH0_BTG_PATH_V1, 0x0); 1944 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 1945 B_PATH1_G_LNA6_OP1DB_V1, 0x20); 1946 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 1947 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); 1948 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 1949 B_PATH1_BT_SHARE_V1, 0x1); 1950 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 1951 B_PATH1_BTG_PATH_V1, 0x1); 1952 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1953 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1); 1954 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x2); 1955 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1956 B_BT_DYN_DC_EST_EN_MSK, 0x1); 1957 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1); 1958 } else { 1959 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1960 B_PATH0_BT_SHARE_V1, 0x0); 1961 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1962 B_PATH0_BTG_PATH_V1, 0x0); 1963 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 1964 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 1965 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 1966 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 1967 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 1968 B_PATH1_BT_SHARE_V1, 0x0); 1969 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 1970 B_PATH1_BTG_PATH_V1, 0x0); 1971 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc); 1972 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0); 1973 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0); 1974 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1975 B_BT_DYN_DC_EST_EN_MSK, 0x1); 1976 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0); 1977 } 1978} 1979 1980void rtw8852b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev, 1981 enum rtw89_rf_path_bit rx_path) 1982{ 1983 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1984 u32 rst_mask0; 1985 u32 rst_mask1; 1986 1987 if (rx_path == RF_A) { 1988 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1); 1989 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1); 1990 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1); 1991 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 1992 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 1993 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); 1994 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 1995 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 1996 } else if (rx_path == RF_B) { 1997 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 2); 1998 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 2); 1999 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 2); 2000 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2001 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2002 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); 2003 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2004 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2005 } else if (rx_path == RF_AB) { 2006 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 3); 2007 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 3); 2008 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 3); 2009 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 2010 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 2011 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); 2012 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 2013 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 2014 } 2015 2016 rtw8852b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0); 2017 2018 if (chan->band_type == RTW89_BAND_2G && 2019 (rx_path == RF_B || rx_path == RF_AB)) 2020 rtw8852b_ctrl_btg(rtwdev, true); 2021 else 2022 rtw8852b_ctrl_btg(rtwdev, false); 2023 2024 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 2025 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 2026 if (rx_path == RF_A) { 2027 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 2028 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 2029 } else { 2030 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 2031 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 2032 } 2033} 2034 2035static void rtw8852b_bb_ctrl_rf_mode_rx_path(struct rtw89_dev *rtwdev, 2036 enum rtw89_rf_path_bit rx_path) 2037{ 2038 if (rx_path == RF_A) { 2039 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, 2040 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 2041 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, 2042 B_P0_RFMODE_FTM_RX, 0x333); 2043 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, 2044 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1111111); 2045 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, 2046 B_P1_RFMODE_FTM_RX, 0x111); 2047 } else if (rx_path == RF_B) { 2048 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, 2049 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1111111); 2050 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, 2051 B_P0_RFMODE_FTM_RX, 0x111); 2052 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, 2053 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 2054 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, 2055 B_P1_RFMODE_FTM_RX, 0x333); 2056 } else if (rx_path == RF_AB) { 2057 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, 2058 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 2059 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, 2060 B_P0_RFMODE_FTM_RX, 0x333); 2061 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, 2062 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 2063 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, 2064 B_P1_RFMODE_FTM_RX, 0x333); 2065 } 2066} 2067 2068static void rtw8852b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 2069{ 2070 struct rtw89_hal *hal = &rtwdev->hal; 2071 enum rtw89_rf_path_bit rx_path = hal->antenna_rx ? hal->antenna_rx : RF_AB; 2072 2073 rtw8852b_bb_ctrl_rx_path(rtwdev, rx_path); 2074 rtw8852b_bb_ctrl_rf_mode_rx_path(rtwdev, rx_path); 2075 2076 if (rtwdev->hal.rx_nss == 1) { 2077 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2078 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2079 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2080 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2081 } else { 2082 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 2083 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 2084 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 2085 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 2086 } 2087 2088 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 2089} 2090 2091static u8 rtw8852b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 2092{ 2093 if (rtwdev->is_tssi_mode[rf_path]) { 2094 u32 addr = 0x1c10 + (rf_path << 13); 2095 2096 return rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 2097 } 2098 2099 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2100 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 2101 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2102 2103 fsleep(200); 2104 2105 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 2106} 2107 2108static void rtw8852b_btc_set_rfe(struct rtw89_dev *rtwdev) 2109{ 2110 struct rtw89_btc *btc = &rtwdev->btc; 2111 struct rtw89_btc_module *module = &btc->mdinfo; 2112 2113 module->rfe_type = rtwdev->efuse.rfe_type; 2114 module->cv = rtwdev->hal.cv; 2115 module->bt_solo = 0; 2116 module->switch_type = BTC_SWITCH_INTERNAL; 2117 2118 if (module->rfe_type > 0) 2119 module->ant.num = module->rfe_type % 2 ? 2 : 3; 2120 else 2121 module->ant.num = 2; 2122 2123 module->ant.diversity = 0; 2124 module->ant.isolation = 10; 2125 2126 if (module->ant.num == 3) { 2127 module->ant.type = BTC_ANT_DEDICATED; 2128 module->bt_pos = BTC_BT_ALONE; 2129 } else { 2130 module->ant.type = BTC_ANT_SHARED; 2131 module->bt_pos = BTC_BT_BTG; 2132 } 2133} 2134 2135static 2136void rtw8852b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 2137{ 2138 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); 2139 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 2140 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 2141 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); 2142} 2143 2144static void rtw8852b_btc_init_cfg(struct rtw89_dev *rtwdev) 2145{ 2146 struct rtw89_btc *btc = &rtwdev->btc; 2147 struct rtw89_btc_module *module = &btc->mdinfo; 2148 const struct rtw89_chip_info *chip = rtwdev->chip; 2149 const struct rtw89_mac_ax_coex coex_params = { 2150 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 2151 .direction = RTW89_MAC_AX_COEX_INNER, 2152 }; 2153 2154 /* PTA init */ 2155 rtw89_mac_coex_init(rtwdev, &coex_params); 2156 2157 /* set WL Tx response = Hi-Pri */ 2158 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 2159 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 2160 2161 /* set rf gnt debug off */ 2162 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); 2163 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); 2164 2165 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 2166 if (module->ant.type == BTC_ANT_SHARED) { 2167 rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 2168 rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 2169 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 2170 rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 2171 rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x55f); 2172 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 2173 rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 2174 rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 2175 rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 2176 rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x5ff); 2177 } 2178 2179 /* set PTA break table */ 2180 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 2181 2182 /* enable BT counter 0xda40[16,2] = 2b'11 */ 2183 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 2184 btc->cx.wl.status.map.init_ok = true; 2185} 2186 2187static 2188void rtw8852b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 2189{ 2190 u32 bitmap; 2191 u32 reg; 2192 2193 switch (map) { 2194 case BTC_PRI_MASK_TX_RESP: 2195 reg = R_BTC_BT_COEX_MSK_TABLE; 2196 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 2197 break; 2198 case BTC_PRI_MASK_BEACON: 2199 reg = R_AX_WL_PRI_MSK; 2200 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 2201 break; 2202 case BTC_PRI_MASK_RX_CCK: 2203 reg = R_BTC_BT_COEX_MSK_TABLE; 2204 bitmap = B_BTC_PRI_MASK_RXCCK_V1; 2205 break; 2206 default: 2207 return; 2208 } 2209 2210 if (state) 2211 rtw89_write32_set(rtwdev, reg, bitmap); 2212 else 2213 rtw89_write32_clr(rtwdev, reg, bitmap); 2214} 2215 2216union rtw8852b_btc_wl_txpwr_ctrl { 2217 u32 txpwr_val; 2218 struct { 2219 union { 2220 u16 ctrl_all_time; 2221 struct { 2222 s16 data:9; 2223 u16 rsvd:6; 2224 u16 flag:1; 2225 } all_time; 2226 }; 2227 union { 2228 u16 ctrl_gnt_bt; 2229 struct { 2230 s16 data:9; 2231 u16 rsvd:7; 2232 } gnt_bt; 2233 }; 2234 }; 2235} __packed; 2236 2237static void 2238rtw8852b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 2239{ 2240 union rtw8852b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 2241 s32 val; 2242 2243#define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 2244do { \ 2245 u32 _wrt = FIELD_PREP(_msk, _val); \ 2246 BUILD_BUG_ON(!!(_msk & _en)); \ 2247 if (_cond) \ 2248 _wrt |= _en; \ 2249 else \ 2250 _wrt &= ~_en; \ 2251 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 2252 _msk | _en, _wrt); \ 2253} while (0) 2254 2255 switch (arg.ctrl_all_time) { 2256 case 0xffff: 2257 val = 0; 2258 break; 2259 default: 2260 val = arg.all_time.data; 2261 break; 2262 } 2263 2264 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 2265 val, B_AX_FORCE_PWR_BY_RATE_EN, 2266 arg.ctrl_all_time != 0xffff); 2267 2268 switch (arg.ctrl_gnt_bt) { 2269 case 0xffff: 2270 val = 0; 2271 break; 2272 default: 2273 val = arg.gnt_bt.data; 2274 break; 2275 } 2276 2277 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 2278 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 2279 2280#undef __write_ctrl 2281} 2282 2283static 2284s8 rtw8852b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 2285{ 2286 /* +6 for compensate offset */ 2287 return clamp_t(s8, val + 6, -100, 0) + 100; 2288} 2289 2290static 2291void rtw8852b_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2292{ 2293 /* Feature move to firmware */ 2294} 2295 2296static void rtw8852b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2297{ 2298 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2299 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2300 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x31); 2301 2302 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2303 if (state) 2304 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x179); 2305 else 2306 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x20); 2307 2308 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2309} 2310 2311static void rtw8852b_btc_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 2312{ 2313 switch (level) { 2314 case 0: /* default */ 2315 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2316 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2317 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2318 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2319 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2320 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2321 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2322 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2323 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2324 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2325 break; 2326 case 1: /* Fix LNA2=5 */ 2327 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2328 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2329 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2330 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2331 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2332 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2333 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2334 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2335 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2336 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2337 break; 2338 } 2339} 2340 2341static void rtw8852b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2342{ 2343 struct rtw89_btc *btc = &rtwdev->btc; 2344 2345 switch (level) { 2346 case 0: /* original */ 2347 default: 2348 rtw8852b_bb_ctrl_btc_preagc(rtwdev, false); 2349 btc->dm.wl_lna2 = 0; 2350 break; 2351 case 1: /* for FDD free-run */ 2352 rtw8852b_bb_ctrl_btc_preagc(rtwdev, true); 2353 btc->dm.wl_lna2 = 0; 2354 break; 2355 case 2: /* for BTG Co-Rx*/ 2356 rtw8852b_bb_ctrl_btc_preagc(rtwdev, false); 2357 btc->dm.wl_lna2 = 1; 2358 break; 2359 } 2360 2361 rtw8852b_btc_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2362} 2363 2364static void rtw8852b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2365 struct rtw89_rx_phy_ppdu *phy_ppdu, 2366 struct ieee80211_rx_status *status) 2367{ 2368 u16 chan = phy_ppdu->chan_idx; 2369 enum nl80211_band band; 2370 u8 ch; 2371 2372 if (chan == 0) 2373 return; 2374 2375 rtw89_decode_chan_idx(rtwdev, chan, &ch, &band); 2376 status->freq = ieee80211_channel_to_frequency(ch, band); 2377 status->band = band; 2378} 2379 2380static void rtw8852b_query_ppdu(struct rtw89_dev *rtwdev, 2381 struct rtw89_rx_phy_ppdu *phy_ppdu, 2382 struct ieee80211_rx_status *status) 2383{ 2384 u8 path; 2385 u8 *rx_power = phy_ppdu->rssi; 2386 2387 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2388 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2389 status->chains |= BIT(path); 2390 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2391 } 2392 if (phy_ppdu->valid) 2393 rtw8852b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2394} 2395 2396static int rtw8852b_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2397{ 2398 int ret; 2399 2400 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2401 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2402 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x1); 2403 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2404 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2405 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2406 2407 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7, 2408 FULL_BIT_MASK); 2409 if (ret) 2410 return ret; 2411 2412 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7, 2413 FULL_BIT_MASK); 2414 if (ret) 2415 return ret; 2416 2417 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE); 2418 2419 return 0; 2420} 2421 2422static int rtw8852b_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2423{ 2424 u8 wl_rfc_s0; 2425 u8 wl_rfc_s1; 2426 int ret; 2427 2428 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2429 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2430 2431 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0); 2432 if (ret) 2433 return ret; 2434 wl_rfc_s0 &= ~XTAL_SI_RF00S_EN; 2435 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0, 2436 FULL_BIT_MASK); 2437 if (ret) 2438 return ret; 2439 2440 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1); 2441 if (ret) 2442 return ret; 2443 wl_rfc_s1 &= ~XTAL_SI_RF10S_EN; 2444 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1, 2445 FULL_BIT_MASK); 2446 return ret; 2447} 2448 2449static const struct rtw89_chip_ops rtw8852b_chip_ops = { 2450 .enable_bb_rf = rtw8852b_mac_enable_bb_rf, 2451 .disable_bb_rf = rtw8852b_mac_disable_bb_rf, 2452 .bb_reset = rtw8852b_bb_reset, 2453 .bb_sethw = rtw8852b_bb_sethw, 2454 .read_rf = rtw89_phy_read_rf_v1, 2455 .write_rf = rtw89_phy_write_rf_v1, 2456 .set_channel = rtw8852b_set_channel, 2457 .set_channel_help = rtw8852b_set_channel_help, 2458 .read_efuse = rtw8852b_read_efuse, 2459 .read_phycap = rtw8852b_read_phycap, 2460 .fem_setup = NULL, 2461 .rfe_gpio = NULL, 2462 .rfk_init = rtw8852b_rfk_init, 2463 .rfk_channel = rtw8852b_rfk_channel, 2464 .rfk_band_changed = rtw8852b_rfk_band_changed, 2465 .rfk_scan = rtw8852b_rfk_scan, 2466 .rfk_track = rtw8852b_rfk_track, 2467 .power_trim = rtw8852b_power_trim, 2468 .set_txpwr = rtw8852b_set_txpwr, 2469 .set_txpwr_ctrl = rtw8852b_set_txpwr_ctrl, 2470 .init_txpwr_unit = rtw8852b_init_txpwr_unit, 2471 .get_thermal = rtw8852b_get_thermal, 2472 .ctrl_btg = rtw8852b_ctrl_btg, 2473 .query_ppdu = rtw8852b_query_ppdu, 2474 .bb_ctrl_btc_preagc = rtw8852b_bb_ctrl_btc_preagc, 2475 .cfg_txrx_path = rtw8852b_bb_cfg_txrx_path, 2476 .set_txpwr_ul_tb_offset = rtw8852b_set_txpwr_ul_tb_offset, 2477 .pwr_on_func = rtw8852b_pwr_on_func, 2478 .pwr_off_func = rtw8852b_pwr_off_func, 2479 .query_rxdesc = rtw89_core_query_rxdesc, 2480 .fill_txdesc = rtw89_core_fill_txdesc, 2481 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 2482 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2483 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2484 .stop_sch_tx = rtw89_mac_stop_sch_tx, 2485 .resume_sch_tx = rtw89_mac_resume_sch_tx, 2486 .h2c_dctl_sec_cam = NULL, 2487 2488 .btc_set_rfe = rtw8852b_btc_set_rfe, 2489 .btc_init_cfg = rtw8852b_btc_init_cfg, 2490 .btc_set_wl_pri = rtw8852b_btc_set_wl_pri, 2491 .btc_set_wl_txpwr_ctrl = rtw8852b_btc_set_wl_txpwr_ctrl, 2492 .btc_get_bt_rssi = rtw8852b_btc_get_bt_rssi, 2493 .btc_update_bt_cnt = rtw8852b_btc_update_bt_cnt, 2494 .btc_wl_s1_standby = rtw8852b_btc_wl_s1_standby, 2495 .btc_set_wl_rx_gain = rtw8852b_btc_set_wl_rx_gain, 2496 .btc_set_policy = rtw89_btc_set_policy_v1, 2497}; 2498 2499#ifdef CONFIG_PM 2500static const struct wiphy_wowlan_support rtw_wowlan_stub_8852b = { 2501 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2502 .n_patterns = RTW89_MAX_PATTERN_NUM, 2503 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2504 .pattern_min_len = 1, 2505}; 2506#endif 2507 2508const struct rtw89_chip_info rtw8852b_chip_info = { 2509 .chip_id = RTL8852B, 2510 .chip_gen = RTW89_CHIP_AX, 2511 .ops = &rtw8852b_chip_ops, 2512 .mac_def = &rtw89_mac_gen_ax, 2513 .phy_def = &rtw89_phy_gen_ax, 2514 .fw_basename = RTW8852B_FW_BASENAME, 2515 .fw_format_max = RTW8852B_FW_FORMAT_MAX, 2516 .try_ce_fw = true, 2517 .needed_fw_elms = 0, 2518 .fifo_size = 196608, 2519 .small_fifo_size = true, 2520 .dle_scc_rsvd_size = 98304, 2521 .max_amsdu_limit = 3500, 2522 .dis_2g_40m_ul_ofdma = true, 2523 .rsvd_ple_ofst = 0x2f800, 2524 .hfc_param_ini = rtw8852b_hfc_param_ini_pcie, 2525 .dle_mem = rtw8852b_dle_mem_pcie, 2526 .wde_qempty_acq_num = 4, 2527 .wde_qempty_mgq_sel = 4, 2528 .rf_base_addr = {0xe000, 0xf000}, 2529 .pwr_on_seq = NULL, 2530 .pwr_off_seq = NULL, 2531 .bb_table = &rtw89_8852b_phy_bb_table, 2532 .bb_gain_table = &rtw89_8852b_phy_bb_gain_table, 2533 .rf_table = {&rtw89_8852b_phy_radioa_table, 2534 &rtw89_8852b_phy_radiob_table,}, 2535 .nctl_table = &rtw89_8852b_phy_nctl_table, 2536 .nctl_post_table = NULL, 2537 .byr_table = &rtw89_8852b_byr_table, 2538 .dflt_parms = &rtw89_8852b_dflt_parms, 2539 .rfe_parms_conf = NULL, 2540 .txpwr_factor_rf = 2, 2541 .txpwr_factor_mac = 1, 2542 .dig_table = NULL, 2543 .dig_regs = &rtw8852b_dig_regs, 2544 .tssi_dbw_table = NULL, 2545 .support_chanctx_num = 0, 2546 .support_bands = BIT(NL80211_BAND_2GHZ) | 2547 BIT(NL80211_BAND_5GHZ), 2548 .support_bw160 = false, 2549 .support_unii4 = true, 2550 .support_ul_tb_ctrl = true, 2551 .hw_sec_hdr = false, 2552 .rf_path_num = 2, 2553 .tx_nss = 2, 2554 .rx_nss = 2, 2555 .acam_num = 128, 2556 .bcam_num = 10, 2557 .scam_num = 128, 2558 .bacam_num = 2, 2559 .bacam_dynamic_num = 4, 2560 .bacam_ver = RTW89_BACAM_V0, 2561 .sec_ctrl_efuse_size = 4, 2562 .physical_efuse_size = 1216, 2563 .logical_efuse_size = 2048, 2564 .limit_efuse_size = 1280, 2565 .dav_phy_efuse_size = 96, 2566 .dav_log_efuse_size = 16, 2567 .phycap_addr = 0x580, 2568 .phycap_size = 128, 2569 .para_ver = 0, 2570 .wlcx_desired = 0x05050000, 2571 .btcx_desired = 0x5, 2572 .scbd = 0x1, 2573 .mailbox = 0x1, 2574 2575 .afh_guard_ch = 6, 2576 .wl_rssi_thres = rtw89_btc_8852b_wl_rssi_thres, 2577 .bt_rssi_thres = rtw89_btc_8852b_bt_rssi_thres, 2578 .rssi_tol = 2, 2579 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852b_mon_reg), 2580 .mon_reg = rtw89_btc_8852b_mon_reg, 2581 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_ul), 2582 .rf_para_ulink = rtw89_btc_8852b_rf_ul, 2583 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_dl), 2584 .rf_para_dlink = rtw89_btc_8852b_rf_dl, 2585 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2586 BIT(RTW89_PS_MODE_CLK_GATED) | 2587 BIT(RTW89_PS_MODE_PWR_GATED), 2588 .low_power_hci_modes = 0, 2589 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 2590 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 2591 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 2592 .txwd_body_size = sizeof(struct rtw89_txwd_body), 2593 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 2594 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2595 .h2c_regs = rtw8852b_h2c_regs, 2596 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 2597 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2598 .c2h_regs = rtw8852b_c2h_regs, 2599 .page_regs = &rtw8852b_page_regs, 2600 .cfo_src_fd = true, 2601 .cfo_hw_comp = true, 2602 .dcfo_comp = &rtw8852b_dcfo_comp, 2603 .dcfo_comp_sft = 10, 2604 .imr_info = &rtw8852b_imr_info, 2605 .rrsr_cfgs = &rtw8852b_rrsr_cfgs, 2606 .bss_clr_map_reg = R_BSS_CLR_MAP_V1, 2607 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) | 2608 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) | 2609 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI), 2610 .edcca_lvl_reg = R_SEG0R_EDCCA_LVL_V1, 2611#ifdef CONFIG_PM 2612 .wowlan_stub = &rtw_wowlan_stub_8852b, 2613#endif 2614 .xtal_info = NULL, 2615}; 2616EXPORT_SYMBOL(rtw8852b_chip_info); 2617 2618MODULE_FIRMWARE(RTW8852B_MODULE_FIRMWARE); 2619MODULE_AUTHOR("Realtek Corporation"); 2620MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852B driver"); 2621MODULE_LICENSE("Dual BSD/GPL"); 2622