1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4#include "../wifi.h" 5#include "../efuse.h" 6#include "../base.h" 7#include "../regd.h" 8#include "../cam.h" 9#include "../ps.h" 10#include "../pci.h" 11#include "reg.h" 12#include "def.h" 13#include "phy.h" 14#include "../rtl8723com/phy_common.h" 15#include "dm.h" 16#include "../rtl8723com/dm_common.h" 17#include "fw.h" 18#include "../rtl8723com/fw_common.h" 19#include "led.h" 20#include "hw.h" 21#include "../pwrseqcmd.h" 22#include "pwrseq.h" 23#include "btc.h" 24 25#define LLT_CONFIG 5 26 27static void _rtl8723e_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 28 u8 set_bits, u8 clear_bits) 29{ 30 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 31 struct rtl_priv *rtlpriv = rtl_priv(hw); 32 33 rtlpci->reg_bcn_ctrl_val |= set_bits; 34 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 35 36 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); 37} 38 39static void _rtl8723e_stop_tx_beacon(struct ieee80211_hw *hw) 40{ 41 struct rtl_priv *rtlpriv = rtl_priv(hw); 42 u8 tmp1byte; 43 44 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 45 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 46 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 47 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 48 tmp1byte &= ~(BIT(0)); 49 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 50} 51 52static void _rtl8723e_resume_tx_beacon(struct ieee80211_hw *hw) 53{ 54 struct rtl_priv *rtlpriv = rtl_priv(hw); 55 u8 tmp1byte; 56 57 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 58 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 59 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 60 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 61 tmp1byte |= BIT(1); 62 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 63} 64 65static void _rtl8723e_enable_bcn_sub_func(struct ieee80211_hw *hw) 66{ 67 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(1)); 68} 69 70static void _rtl8723e_disable_bcn_sub_func(struct ieee80211_hw *hw) 71{ 72 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(1), 0); 73} 74 75void rtl8723e_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 76{ 77 struct rtl_priv *rtlpriv = rtl_priv(hw); 78 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 79 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 80 81 switch (variable) { 82 case HW_VAR_RCR: 83 *((u32 *)(val)) = rtlpci->receive_config; 84 break; 85 case HW_VAR_RF_STATE: 86 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 87 break; 88 case HW_VAR_FWLPS_RF_ON:{ 89 enum rf_pwrstate rfstate; 90 u32 val_rcr; 91 92 rtlpriv->cfg->ops->get_hw_reg(hw, 93 HW_VAR_RF_STATE, 94 (u8 *)(&rfstate)); 95 if (rfstate == ERFOFF) { 96 *((bool *)(val)) = true; 97 } else { 98 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 99 val_rcr &= 0x00070000; 100 if (val_rcr) 101 *((bool *)(val)) = false; 102 else 103 *((bool *)(val)) = true; 104 } 105 break; 106 } 107 case HW_VAR_FW_PSMODE_STATUS: 108 *((bool *)(val)) = ppsc->fw_current_inpsmode; 109 break; 110 case HW_VAR_CORRECT_TSF:{ 111 u64 tsf; 112 u32 *ptsf_low = (u32 *)&tsf; 113 u32 *ptsf_high = ((u32 *)&tsf) + 1; 114 115 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 116 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 117 118 *((u64 *)(val)) = tsf; 119 120 break; 121 } 122 case HAL_DEF_WOWLAN: 123 break; 124 default: 125 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 126 "switch case %#x not processed\n", variable); 127 break; 128 } 129} 130 131void rtl8723e_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 132{ 133 struct rtl_priv *rtlpriv = rtl_priv(hw); 134 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 135 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 136 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 137 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 138 u8 idx; 139 140 switch (variable) { 141 case HW_VAR_ETHER_ADDR:{ 142 for (idx = 0; idx < ETH_ALEN; idx++) { 143 rtl_write_byte(rtlpriv, (REG_MACID + idx), 144 val[idx]); 145 } 146 break; 147 } 148 case HW_VAR_BASIC_RATE:{ 149 u16 b_rate_cfg = ((u16 *)val)[0]; 150 u8 rate_index = 0; 151 152 b_rate_cfg = b_rate_cfg & 0x15f; 153 b_rate_cfg |= 0x01; 154 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff); 155 rtl_write_byte(rtlpriv, REG_RRSR + 1, 156 (b_rate_cfg >> 8) & 0xff); 157 while (b_rate_cfg > 0x1) { 158 b_rate_cfg = (b_rate_cfg >> 1); 159 rate_index++; 160 } 161 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 162 rate_index); 163 break; 164 } 165 case HW_VAR_BSSID:{ 166 for (idx = 0; idx < ETH_ALEN; idx++) { 167 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 168 val[idx]); 169 } 170 break; 171 } 172 case HW_VAR_SIFS:{ 173 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 174 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); 175 176 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 177 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 178 179 if (!mac->ht_enable) 180 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 181 0x0e0e); 182 else 183 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 184 *((u16 *)val)); 185 break; 186 } 187 case HW_VAR_SLOT_TIME:{ 188 u8 e_aci; 189 190 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 191 "HW_VAR_SLOT_TIME %x\n", val[0]); 192 193 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 194 195 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 196 rtlpriv->cfg->ops->set_hw_reg(hw, 197 HW_VAR_AC_PARAM, 198 (u8 *)(&e_aci)); 199 } 200 break; 201 } 202 case HW_VAR_ACK_PREAMBLE:{ 203 u8 reg_tmp; 204 u8 short_preamble = (bool)(*(u8 *)val); 205 206 reg_tmp = (mac->cur_40_prime_sc) << 5; 207 if (short_preamble) 208 reg_tmp |= 0x80; 209 210 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 211 break; 212 } 213 case HW_VAR_AMPDU_MIN_SPACE:{ 214 u8 min_spacing_to_set; 215 u8 sec_min_space; 216 217 min_spacing_to_set = *((u8 *)val); 218 if (min_spacing_to_set <= 7) { 219 sec_min_space = 0; 220 221 if (min_spacing_to_set < sec_min_space) 222 min_spacing_to_set = sec_min_space; 223 224 mac->min_space_cfg = ((mac->min_space_cfg & 225 0xf8) | 226 min_spacing_to_set); 227 228 *val = min_spacing_to_set; 229 230 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 231 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 232 mac->min_space_cfg); 233 234 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 235 mac->min_space_cfg); 236 } 237 break; 238 } 239 case HW_VAR_SHORTGI_DENSITY:{ 240 u8 density_to_set; 241 242 density_to_set = *((u8 *)val); 243 mac->min_space_cfg |= (density_to_set << 3); 244 245 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 246 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 247 mac->min_space_cfg); 248 249 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 250 mac->min_space_cfg); 251 252 break; 253 } 254 case HW_VAR_AMPDU_FACTOR:{ 255 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 }; 256 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97}; 257 u8 factor_toset; 258 u8 *p_regtoset = NULL; 259 u8 index = 0; 260 261 if ((rtlpriv->btcoexist.bt_coexistence) && 262 (rtlpriv->btcoexist.bt_coexist_type == 263 BT_CSR_BC4)) 264 p_regtoset = regtoset_bt; 265 else 266 p_regtoset = regtoset_normal; 267 268 factor_toset = *((u8 *)val); 269 if (factor_toset <= 3) { 270 factor_toset = (1 << (factor_toset + 2)); 271 if (factor_toset > 0xf) 272 factor_toset = 0xf; 273 274 for (index = 0; index < 4; index++) { 275 if ((p_regtoset[index] & 0xf0) > 276 (factor_toset << 4)) 277 p_regtoset[index] = 278 (p_regtoset[index] & 0x0f) | 279 (factor_toset << 4); 280 281 if ((p_regtoset[index] & 0x0f) > 282 factor_toset) 283 p_regtoset[index] = 284 (p_regtoset[index] & 0xf0) | 285 (factor_toset); 286 287 rtl_write_byte(rtlpriv, 288 (REG_AGGLEN_LMT + index), 289 p_regtoset[index]); 290 } 291 292 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 293 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 294 factor_toset); 295 } 296 break; 297 } 298 case HW_VAR_AC_PARAM:{ 299 u8 e_aci = *((u8 *)val); 300 301 rtl8723_dm_init_edca_turbo(hw); 302 303 if (rtlpci->acm_method != EACMWAY2_SW) 304 rtlpriv->cfg->ops->set_hw_reg(hw, 305 HW_VAR_ACM_CTRL, 306 (u8 *)(&e_aci)); 307 break; 308 } 309 case HW_VAR_ACM_CTRL:{ 310 u8 e_aci = *((u8 *)val); 311 union aci_aifsn *p_aci_aifsn = 312 (union aci_aifsn *)(&mac->ac[0].aifs); 313 u8 acm = p_aci_aifsn->f.acm; 314 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 315 316 acm_ctrl = 317 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 318 319 if (acm) { 320 switch (e_aci) { 321 case AC0_BE: 322 acm_ctrl |= ACMHW_BEQEN; 323 break; 324 case AC2_VI: 325 acm_ctrl |= ACMHW_VIQEN; 326 break; 327 case AC3_VO: 328 acm_ctrl |= ACMHW_VOQEN; 329 break; 330 default: 331 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 332 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 333 acm); 334 break; 335 } 336 } else { 337 switch (e_aci) { 338 case AC0_BE: 339 acm_ctrl &= (~ACMHW_BEQEN); 340 break; 341 case AC2_VI: 342 acm_ctrl &= (~ACMHW_VIQEN); 343 break; 344 case AC3_VO: 345 acm_ctrl &= (~ACMHW_VOQEN); 346 break; 347 default: 348 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 349 "switch case %#x not processed\n", 350 e_aci); 351 break; 352 } 353 } 354 355 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE, 356 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 357 acm_ctrl); 358 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 359 break; 360 } 361 case HW_VAR_RCR:{ 362 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); 363 rtlpci->receive_config = ((u32 *)(val))[0]; 364 break; 365 } 366 case HW_VAR_RETRY_LIMIT:{ 367 u8 retry_limit = ((u8 *)(val))[0]; 368 369 rtl_write_word(rtlpriv, REG_RL, 370 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 371 retry_limit << RETRY_LIMIT_LONG_SHIFT); 372 break; 373 } 374 case HW_VAR_DUAL_TSF_RST: 375 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 376 break; 377 case HW_VAR_EFUSE_BYTES: 378 rtlefuse->efuse_usedbytes = *((u16 *)val); 379 break; 380 case HW_VAR_EFUSE_USAGE: 381 rtlefuse->efuse_usedpercentage = *((u8 *)val); 382 break; 383 case HW_VAR_IO_CMD: 384 rtl8723e_phy_set_io_cmd(hw, (*(enum io_type *)val)); 385 break; 386 case HW_VAR_WPA_CONFIG: 387 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); 388 break; 389 case HW_VAR_SET_RPWM:{ 390 u8 rpwm_val; 391 392 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 393 udelay(1); 394 395 if (rpwm_val & BIT(7)) { 396 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 397 (*(u8 *)val)); 398 } else { 399 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 400 ((*(u8 *)val) | BIT(7))); 401 } 402 403 break; 404 } 405 case HW_VAR_H2C_FW_PWRMODE:{ 406 u8 psmode = (*(u8 *)val); 407 408 if (psmode != FW_PS_ACTIVE_MODE) 409 rtl8723e_dm_rf_saving(hw, true); 410 411 rtl8723e_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); 412 break; 413 } 414 case HW_VAR_FW_PSMODE_STATUS: 415 ppsc->fw_current_inpsmode = *((bool *)val); 416 break; 417 case HW_VAR_H2C_FW_JOINBSSRPT:{ 418 u8 mstatus = (*(u8 *)val); 419 u8 tmp_regcr, tmp_reg422; 420 bool b_recover = false; 421 422 if (mstatus == RT_MEDIA_CONNECT) { 423 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, 424 NULL); 425 426 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 427 rtl_write_byte(rtlpriv, REG_CR + 1, 428 (tmp_regcr | BIT(0))); 429 430 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3)); 431 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0); 432 433 tmp_reg422 = 434 rtl_read_byte(rtlpriv, 435 REG_FWHW_TXQ_CTRL + 2); 436 if (tmp_reg422 & BIT(6)) 437 b_recover = true; 438 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 439 tmp_reg422 & (~BIT(6))); 440 441 rtl8723e_set_fw_rsvdpagepkt(hw, 0); 442 443 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0); 444 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4)); 445 446 if (b_recover) { 447 rtl_write_byte(rtlpriv, 448 REG_FWHW_TXQ_CTRL + 2, 449 tmp_reg422); 450 } 451 452 rtl_write_byte(rtlpriv, REG_CR + 1, 453 (tmp_regcr & ~(BIT(0)))); 454 } 455 rtl8723e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val)); 456 457 break; 458 } 459 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:{ 460 rtl8723e_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); 461 break; 462 } 463 case HW_VAR_AID:{ 464 u16 u2btmp; 465 466 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 467 u2btmp &= 0xC000; 468 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, 469 (u2btmp | mac->assoc_id)); 470 471 break; 472 } 473 case HW_VAR_CORRECT_TSF:{ 474 u8 btype_ibss = ((u8 *)(val))[0]; 475 476 if (btype_ibss) 477 _rtl8723e_stop_tx_beacon(hw); 478 479 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3)); 480 481 rtl_write_dword(rtlpriv, REG_TSFTR, 482 (u32)(mac->tsf & 0xffffffff)); 483 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 484 (u32)((mac->tsf >> 32) & 0xffffffff)); 485 486 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0); 487 488 if (btype_ibss) 489 _rtl8723e_resume_tx_beacon(hw); 490 491 break; 492 } 493 case HW_VAR_FW_LPS_ACTION:{ 494 bool b_enter_fwlps = *((bool *)val); 495 u8 rpwm_val, fw_pwrmode; 496 bool fw_current_inps; 497 498 if (b_enter_fwlps) { 499 rpwm_val = 0x02; /* RF off */ 500 fw_current_inps = true; 501 rtlpriv->cfg->ops->set_hw_reg(hw, 502 HW_VAR_FW_PSMODE_STATUS, 503 (u8 *)(&fw_current_inps)); 504 rtlpriv->cfg->ops->set_hw_reg(hw, 505 HW_VAR_H2C_FW_PWRMODE, 506 (u8 *)(&ppsc->fwctrl_psmode)); 507 508 rtlpriv->cfg->ops->set_hw_reg(hw, 509 HW_VAR_SET_RPWM, 510 (u8 *)(&rpwm_val)); 511 } else { 512 rpwm_val = 0x0C; /* RF on */ 513 fw_pwrmode = FW_PS_ACTIVE_MODE; 514 fw_current_inps = false; 515 rtlpriv->cfg->ops->set_hw_reg(hw, 516 HW_VAR_SET_RPWM, 517 (u8 *)(&rpwm_val)); 518 rtlpriv->cfg->ops->set_hw_reg(hw, 519 HW_VAR_H2C_FW_PWRMODE, 520 (u8 *)(&fw_pwrmode)); 521 522 rtlpriv->cfg->ops->set_hw_reg(hw, 523 HW_VAR_FW_PSMODE_STATUS, 524 (u8 *)(&fw_current_inps)); 525 } 526 break; 527 } 528 default: 529 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 530 "switch case %#x not processed\n", variable); 531 break; 532 } 533} 534 535static bool _rtl8723e_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 536{ 537 struct rtl_priv *rtlpriv = rtl_priv(hw); 538 bool status = true; 539 long count = 0; 540 u32 value = _LLT_INIT_ADDR(address) | 541 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); 542 543 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 544 545 do { 546 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 547 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 548 break; 549 550 if (count > POLLING_LLT_THRESHOLD) { 551 pr_err("Failed to polling write LLT done at address %d!\n", 552 address); 553 status = false; 554 break; 555 } 556 } while (++count); 557 558 return status; 559} 560 561static bool _rtl8723e_llt_table_init(struct ieee80211_hw *hw) 562{ 563 struct rtl_priv *rtlpriv = rtl_priv(hw); 564 unsigned short i; 565 u8 txpktbuf_bndy; 566 u8 maxpage; 567 bool status; 568 u8 ubyte; 569 570#if LLT_CONFIG == 1 571 maxpage = 255; 572 txpktbuf_bndy = 252; 573#elif LLT_CONFIG == 2 574 maxpage = 127; 575 txpktbuf_bndy = 124; 576#elif LLT_CONFIG == 3 577 maxpage = 255; 578 txpktbuf_bndy = 174; 579#elif LLT_CONFIG == 4 580 maxpage = 255; 581 txpktbuf_bndy = 246; 582#elif LLT_CONFIG == 5 583 maxpage = 255; 584 txpktbuf_bndy = 246; 585#endif 586 587 rtl_write_byte(rtlpriv, REG_CR, 0x8B); 588 589#if LLT_CONFIG == 1 590 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c); 591 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c); 592#elif LLT_CONFIG == 2 593 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010); 594#elif LLT_CONFIG == 3 595 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484); 596#elif LLT_CONFIG == 4 597 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c); 598#elif LLT_CONFIG == 5 599 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000); 600 601 rtl_write_dword(rtlpriv, REG_RQPN, 0x80ac1c29); 602 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x03); 603#endif 604 605 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy)); 606 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 607 608 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 609 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 610 611 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); 612 rtl_write_byte(rtlpriv, REG_PBP, 0x11); 613 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 614 615 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 616 status = _rtl8723e_llt_write(hw, i, i + 1); 617 if (!status) 618 return status; 619 } 620 621 status = _rtl8723e_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 622 if (!status) 623 return status; 624 625 for (i = txpktbuf_bndy; i < maxpage; i++) { 626 status = _rtl8723e_llt_write(hw, i, (i + 1)); 627 if (!status) 628 return status; 629 } 630 631 status = _rtl8723e_llt_write(hw, maxpage, txpktbuf_bndy); 632 if (!status) 633 return status; 634 635 rtl_write_byte(rtlpriv, REG_CR, 0xff); 636 ubyte = rtl_read_byte(rtlpriv, REG_RQPN + 3); 637 rtl_write_byte(rtlpriv, REG_RQPN + 3, ubyte | BIT(7)); 638 639 return true; 640} 641 642static void _rtl8723e_gen_refresh_led_state(struct ieee80211_hw *hw) 643{ 644 struct rtl_priv *rtlpriv = rtl_priv(hw); 645 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 646 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0; 647 648 if (rtlpriv->rtlhal.up_first_time) 649 return; 650 651 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 652 rtl8723e_sw_led_on(hw, pin0); 653 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 654 rtl8723e_sw_led_on(hw, pin0); 655 else 656 rtl8723e_sw_led_off(hw, pin0); 657} 658 659static bool _rtl8712e_init_mac(struct ieee80211_hw *hw) 660{ 661 struct rtl_priv *rtlpriv = rtl_priv(hw); 662 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 663 664 unsigned char bytetmp; 665 unsigned short wordtmp; 666 u16 retry = 0; 667 u16 tmpu2b; 668 bool mac_func_enable; 669 670 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 671 bytetmp = rtl_read_byte(rtlpriv, REG_CR); 672 if (bytetmp == 0xFF) 673 mac_func_enable = true; 674 else 675 mac_func_enable = false; 676 677 /* HW Power on sequence */ 678 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 679 PWR_INTF_PCI_MSK, RTL8723_NIC_ENABLE_FLOW)) 680 return false; 681 682 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2); 683 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp | BIT(4)); 684 685 /* eMAC time out function enable, 0x369[7]=1 */ 686 bytetmp = rtl_read_byte(rtlpriv, 0x369); 687 rtl_write_byte(rtlpriv, 0x369, bytetmp | BIT(7)); 688 689 /* ePHY reg 0x1e bit[4]=1 using MDIO interface, 690 * we should do this before Enabling ASPM backdoor. 691 */ 692 do { 693 rtl_write_word(rtlpriv, 0x358, 0x5e); 694 udelay(100); 695 rtl_write_word(rtlpriv, 0x356, 0xc280); 696 rtl_write_word(rtlpriv, 0x354, 0xc290); 697 rtl_write_word(rtlpriv, 0x358, 0x3e); 698 udelay(100); 699 rtl_write_word(rtlpriv, 0x358, 0x5e); 700 udelay(100); 701 tmpu2b = rtl_read_word(rtlpriv, 0x356); 702 retry++; 703 } while (tmpu2b != 0xc290 && retry < 100); 704 705 if (retry >= 100) { 706 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 707 "InitMAC(): ePHY configure fail!!!\n"); 708 return false; 709 } 710 711 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 712 rtl_write_word(rtlpriv, REG_CR + 1, 0x06); 713 714 if (!mac_func_enable) { 715 if (!_rtl8723e_llt_table_init(hw)) 716 return false; 717 } 718 719 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 720 rtl_write_byte(rtlpriv, REG_HISRE, 0xff); 721 722 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff); 723 724 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 725 wordtmp &= 0xf; 726 wordtmp |= 0xF771; 727 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 728 729 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 730 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 731 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF); 732 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); 733 734 rtl_write_byte(rtlpriv, 0x4d0, 0x0); 735 736 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 737 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) & 738 DMA_BIT_MASK(32)); 739 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 740 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma & 741 DMA_BIT_MASK(32)); 742 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 743 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 744 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 745 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 746 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 747 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 748 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 749 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 750 rtl_write_dword(rtlpriv, REG_HQ_DESA, 751 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma & 752 DMA_BIT_MASK(32)); 753 rtl_write_dword(rtlpriv, REG_RX_DESA, 754 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma & 755 DMA_BIT_MASK(32)); 756 757 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x74); 758 759 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 760 761 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 762 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); 763 do { 764 retry++; 765 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 766 } while ((retry < 200) && (bytetmp & BIT(7))); 767 768 _rtl8723e_gen_refresh_led_state(hw); 769 770 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 771 772 return true; 773} 774 775static void _rtl8723e_hw_configure(struct ieee80211_hw *hw) 776{ 777 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 778 struct rtl_priv *rtlpriv = rtl_priv(hw); 779 u8 reg_bw_opmode; 780 u32 reg_prsr; 781 782 reg_bw_opmode = BW_OPMODE_20MHZ; 783 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 784 785 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); 786 787 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 788 789 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr); 790 791 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 792 793 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); 794 795 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); 796 797 rtl_write_word(rtlpriv, REG_RL, 0x0707); 798 799 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); 800 801 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 802 803 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 804 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 805 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 806 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 807 808 if ((rtlpriv->btcoexist.bt_coexistence) && 809 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) 810 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431); 811 else 812 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); 813 814 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); 815 816 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); 817 818 rtlpci->reg_bcn_ctrl_val = 0x1f; 819 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 820 821 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 822 823 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 824 825 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); 826 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 827 828 if ((rtlpriv->btcoexist.bt_coexistence) && 829 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) { 830 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 831 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402); 832 } else { 833 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 834 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 835 } 836 837 if ((rtlpriv->btcoexist.bt_coexistence) && 838 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) 839 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 840 else 841 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666); 842 843 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); 844 845 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); 846 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); 847 848 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); 849 850 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); 851 852 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); 853 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); 854 855 rtl_write_dword(rtlpriv, 0x394, 0x1); 856} 857 858static void _rtl8723e_enable_aspm_back_door(struct ieee80211_hw *hw) 859{ 860 struct rtl_priv *rtlpriv = rtl_priv(hw); 861 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 862 863 rtl_write_byte(rtlpriv, 0x34b, 0x93); 864 rtl_write_word(rtlpriv, 0x350, 0x870c); 865 rtl_write_byte(rtlpriv, 0x352, 0x1); 866 867 if (ppsc->support_backdoor) 868 rtl_write_byte(rtlpriv, 0x349, 0x1b); 869 else 870 rtl_write_byte(rtlpriv, 0x349, 0x03); 871 872 rtl_write_word(rtlpriv, 0x350, 0x2718); 873 rtl_write_byte(rtlpriv, 0x352, 0x1); 874} 875 876void rtl8723e_enable_hw_security_config(struct ieee80211_hw *hw) 877{ 878 struct rtl_priv *rtlpriv = rtl_priv(hw); 879 u8 sec_reg_value; 880 881 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 882 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 883 rtlpriv->sec.pairwise_enc_algorithm, 884 rtlpriv->sec.group_enc_algorithm); 885 886 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 887 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 888 "not open hw encryption\n"); 889 return; 890 } 891 892 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE; 893 894 if (rtlpriv->sec.use_defaultkey) { 895 sec_reg_value |= SCR_TXUSEDK; 896 sec_reg_value |= SCR_RXUSEDK; 897 } 898 899 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 900 901 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 902 903 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 904 "The SECR-value %x\n", sec_reg_value); 905 906 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 907 908} 909 910int rtl8723e_hw_init(struct ieee80211_hw *hw) 911{ 912 struct rtl_priv *rtlpriv = rtl_priv(hw); 913 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 914 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 915 struct rtl_phy *rtlphy = &(rtlpriv->phy); 916 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 917 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 918 bool rtstatus; 919 int err; 920 u8 tmp_u1b; 921 unsigned long flags; 922 923 rtlpriv->rtlhal.being_init_adapter = true; 924 /* As this function can take a very long time (up to 350 ms) 925 * and can be called with irqs disabled, reenable the irqs 926 * to let the other devices continue being serviced. 927 * 928 * It is safe doing so since our own interrupts will only be enabled 929 * in a subsequent step. 930 */ 931 local_save_flags(flags); 932 local_irq_enable(); 933 rtlhal->fw_ready = false; 934 935 rtlpriv->intf_ops->disable_aspm(hw); 936 rtstatus = _rtl8712e_init_mac(hw); 937 if (!rtstatus) { 938 pr_err("Init MAC failed\n"); 939 err = 1; 940 goto exit; 941 } 942 943 err = rtl8723_download_fw(hw, false, FW_8723A_POLLING_TIMEOUT_COUNT); 944 if (err) { 945 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 946 "Failed to download FW. Init HW without FW now..\n"); 947 err = 1; 948 goto exit; 949 } 950 rtlhal->fw_ready = true; 951 952 rtlhal->last_hmeboxnum = 0; 953 rtl8723e_phy_mac_config(hw); 954 /* because last function modify RCR, so we update 955 * rcr var here, or TP will unstable for receive_config 956 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx 957 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 958 */ 959 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 960 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 961 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 962 963 rtl8723e_phy_bb_config(hw); 964 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 965 rtl8723e_phy_rf_config(hw); 966 if (IS_VENDOR_UMC_A_CUT(rtlhal->version)) { 967 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); 968 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); 969 } else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) { 970 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE); 971 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31); 972 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425); 973 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200); 974 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053); 975 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201); 976 } 977 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 978 RF_CHNLBW, RFREG_OFFSET_MASK); 979 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 980 RF_CHNLBW, RFREG_OFFSET_MASK); 981 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 982 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 983 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); 984 _rtl8723e_hw_configure(hw); 985 rtl_cam_reset_all_entry(hw); 986 rtl8723e_enable_hw_security_config(hw); 987 988 ppsc->rfpwr_state = ERFON; 989 990 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 991 _rtl8723e_enable_aspm_back_door(hw); 992 rtlpriv->intf_ops->enable_aspm(hw); 993 994 rtl8723e_bt_hw_init(hw); 995 996 if (ppsc->rfpwr_state == ERFON) { 997 rtl8723e_phy_set_rfpath_switch(hw, 1); 998 if (rtlphy->iqk_initialized) { 999 rtl8723e_phy_iq_calibrate(hw, true); 1000 } else { 1001 rtl8723e_phy_iq_calibrate(hw, false); 1002 rtlphy->iqk_initialized = true; 1003 } 1004 1005 rtl8723e_dm_check_txpower_tracking(hw); 1006 rtl8723e_phy_lc_calibrate(hw); 1007 } 1008 1009 tmp_u1b = efuse_read_1byte(hw, 0x1FA); 1010 if (!(tmp_u1b & BIT(0))) { 1011 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); 1012 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n"); 1013 } 1014 1015 if (!(tmp_u1b & BIT(4))) { 1016 tmp_u1b = rtl_read_byte(rtlpriv, 0x16); 1017 tmp_u1b &= 0x0F; 1018 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80); 1019 udelay(10); 1020 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90); 1021 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n"); 1022 } 1023 rtl8723e_dm_init(hw); 1024exit: 1025 local_irq_restore(flags); 1026 rtlpriv->rtlhal.being_init_adapter = false; 1027 return err; 1028} 1029 1030static enum version_8723e _rtl8723e_read_chip_version(struct ieee80211_hw *hw) 1031{ 1032 struct rtl_priv *rtlpriv = rtl_priv(hw); 1033 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1034 enum version_8723e version = 0x0000; 1035 u32 value32; 1036 1037 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 1038 if (value32 & TRP_VAUX_EN) { 1039 version = (enum version_8723e)(version | 1040 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); 1041 /* RTL8723 with BT function. */ 1042 version = (enum version_8723e)(version | 1043 ((value32 & BT_FUNC) ? CHIP_8723 : 0)); 1044 1045 } else { 1046 /* Normal mass production chip. */ 1047 version = (enum version_8723e) NORMAL_CHIP; 1048 version = (enum version_8723e)(version | 1049 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); 1050 /* RTL8723 with BT function. */ 1051 version = (enum version_8723e)(version | 1052 ((value32 & BT_FUNC) ? CHIP_8723 : 0)); 1053 if (IS_CHIP_VENDOR_UMC(version)) 1054 version = (enum version_8723e)(version | 1055 ((value32 & CHIP_VER_RTL_MASK)));/* IC version (CUT) */ 1056 if (IS_8723_SERIES(version)) { 1057 value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS); 1058 /* ROM code version. */ 1059 version = (enum version_8723e)(version | 1060 ((value32 & RF_RL_ID)>>20)); 1061 } 1062 } 1063 1064 if (IS_8723_SERIES(version)) { 1065 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 1066 rtlphy->polarity_ctl = ((value32 & WL_HWPDN_SL) ? 1067 RT_POLARITY_HIGH_ACT : 1068 RT_POLARITY_LOW_ACT); 1069 } 1070 switch (version) { 1071 case VERSION_TEST_UMC_CHIP_8723: 1072 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1073 "Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n"); 1074 break; 1075 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT: 1076 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1077 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT.\n"); 1078 break; 1079 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT: 1080 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1081 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT.\n"); 1082 break; 1083 default: 1084 pr_err("Chip Version ID: Unknown. Bug?\n"); 1085 break; 1086 } 1087 1088 if (IS_8723_SERIES(version)) 1089 rtlphy->rf_type = RF_1T1R; 1090 1091 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n", 1092 (rtlphy->rf_type == RF_2T2R) ? "RF_2T2R" : "RF_1T1R"); 1093 1094 return version; 1095} 1096 1097static int _rtl8723e_set_media_status(struct ieee80211_hw *hw, 1098 enum nl80211_iftype type) 1099{ 1100 struct rtl_priv *rtlpriv = rtl_priv(hw); 1101 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc; 1102 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1103 u8 mode = MSR_NOLINK; 1104 1105 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0); 1106 rtl_dbg(rtlpriv, COMP_BEACON, DBG_LOUD, 1107 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n"); 1108 1109 switch (type) { 1110 case NL80211_IFTYPE_UNSPECIFIED: 1111 mode = MSR_NOLINK; 1112 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1113 "Set Network type to NO LINK!\n"); 1114 break; 1115 case NL80211_IFTYPE_ADHOC: 1116 mode = MSR_ADHOC; 1117 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1118 "Set Network type to Ad Hoc!\n"); 1119 break; 1120 case NL80211_IFTYPE_STATION: 1121 mode = MSR_INFRA; 1122 ledaction = LED_CTL_LINK; 1123 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1124 "Set Network type to STA!\n"); 1125 break; 1126 case NL80211_IFTYPE_AP: 1127 mode = MSR_AP; 1128 ledaction = LED_CTL_LINK; 1129 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1130 "Set Network type to AP!\n"); 1131 break; 1132 default: 1133 pr_err("Network type %d not support!\n", type); 1134 return 1; 1135 } 1136 1137 /* MSR_INFRA == Link in infrastructure network; 1138 * MSR_ADHOC == Link in ad hoc network; 1139 * Therefore, check link state is necessary. 1140 * 1141 * MSR_AP == AP mode; link state is not cared here. 1142 */ 1143 if (mode != MSR_AP && 1144 rtlpriv->mac80211.link_state < MAC80211_LINKED) { 1145 mode = MSR_NOLINK; 1146 ledaction = LED_CTL_NO_LINK; 1147 } 1148 if (mode == MSR_NOLINK || mode == MSR_INFRA) { 1149 _rtl8723e_stop_tx_beacon(hw); 1150 _rtl8723e_enable_bcn_sub_func(hw); 1151 } else if (mode == MSR_ADHOC || mode == MSR_AP) { 1152 _rtl8723e_resume_tx_beacon(hw); 1153 _rtl8723e_disable_bcn_sub_func(hw); 1154 } else { 1155 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1156 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 1157 mode); 1158 } 1159 1160 rtl_write_byte(rtlpriv, MSR, bt_msr | mode); 1161 rtlpriv->cfg->ops->led_control(hw, ledaction); 1162 if (mode == MSR_AP) 1163 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1164 else 1165 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1166 return 0; 1167} 1168 1169void rtl8723e_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1170{ 1171 struct rtl_priv *rtlpriv = rtl_priv(hw); 1172 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1173 u32 reg_rcr = rtlpci->receive_config; 1174 1175 if (rtlpriv->psc.rfpwr_state != ERFON) 1176 return; 1177 1178 if (check_bssid) { 1179 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1180 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1181 (u8 *)(®_rcr)); 1182 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1183 } else if (!check_bssid) { 1184 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1185 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0); 1186 rtlpriv->cfg->ops->set_hw_reg(hw, 1187 HW_VAR_RCR, (u8 *)(®_rcr)); 1188 } 1189} 1190 1191int rtl8723e_set_network_type(struct ieee80211_hw *hw, 1192 enum nl80211_iftype type) 1193{ 1194 struct rtl_priv *rtlpriv = rtl_priv(hw); 1195 1196 if (_rtl8723e_set_media_status(hw, type)) 1197 return -EOPNOTSUPP; 1198 1199 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1200 if (type != NL80211_IFTYPE_AP) 1201 rtl8723e_set_check_bssid(hw, true); 1202 } else { 1203 rtl8723e_set_check_bssid(hw, false); 1204 } 1205 1206 return 0; 1207} 1208 1209/* don't set REG_EDCA_BE_PARAM here 1210 * because mac80211 will send pkt when scan 1211 */ 1212void rtl8723e_set_qos(struct ieee80211_hw *hw, int aci) 1213{ 1214 struct rtl_priv *rtlpriv = rtl_priv(hw); 1215 1216 rtl8723_dm_init_edca_turbo(hw); 1217 switch (aci) { 1218 case AC1_BK: 1219 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 1220 break; 1221 case AC0_BE: 1222 break; 1223 case AC2_VI: 1224 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 1225 break; 1226 case AC3_VO: 1227 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 1228 break; 1229 default: 1230 WARN_ONCE(true, "rtl8723ae: invalid aci: %d !\n", aci); 1231 break; 1232 } 1233} 1234 1235void rtl8723e_enable_interrupt(struct ieee80211_hw *hw) 1236{ 1237 struct rtl_priv *rtlpriv = rtl_priv(hw); 1238 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1239 1240 rtl_write_dword(rtlpriv, 0x3a8, rtlpci->irq_mask[0] & 0xFFFFFFFF); 1241 rtl_write_dword(rtlpriv, 0x3ac, rtlpci->irq_mask[1] & 0xFFFFFFFF); 1242 rtlpci->irq_enabled = true; 1243} 1244 1245void rtl8723e_disable_interrupt(struct ieee80211_hw *hw) 1246{ 1247 struct rtl_priv *rtlpriv = rtl_priv(hw); 1248 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1249 rtl_write_dword(rtlpriv, 0x3a8, IMR8190_DISABLED); 1250 rtl_write_dword(rtlpriv, 0x3ac, IMR8190_DISABLED); 1251 rtlpci->irq_enabled = false; 1252 /*synchronize_irq(rtlpci->pdev->irq);*/ 1253} 1254 1255static void _rtl8723e_poweroff_adapter(struct ieee80211_hw *hw) 1256{ 1257 struct rtl_priv *rtlpriv = rtl_priv(hw); 1258 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1259 u8 u1b_tmp; 1260 1261 /* Combo (PCIe + USB) Card and PCIe-MF Card */ 1262 /* 1. Run LPS WL RFOFF flow */ 1263 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1264 PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW); 1265 1266 /* 2. 0x1F[7:0] = 0 */ 1267 /* turn off RF */ 1268 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1269 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && 1270 rtlhal->fw_ready) { 1271 rtl8723ae_firmware_selfreset(hw); 1272 } 1273 1274 /* Reset MCU. Suggested by Filen. */ 1275 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1); 1276 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2)))); 1277 1278 /* g. MCUFWDL 0x80[1:0]=0 */ 1279 /* reset MCU ready status */ 1280 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1281 1282 /* HW card disable configuration. */ 1283 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1284 PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW); 1285 1286 /* Reset MCU IO Wrapper */ 1287 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1288 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); 1289 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1290 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0)); 1291 1292 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */ 1293 /* lock ISO/CLK/Power control register */ 1294 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1295} 1296 1297void rtl8723e_card_disable(struct ieee80211_hw *hw) 1298{ 1299 struct rtl_priv *rtlpriv = rtl_priv(hw); 1300 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1301 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1302 enum nl80211_iftype opmode; 1303 1304 mac->link_state = MAC80211_NOLINK; 1305 opmode = NL80211_IFTYPE_UNSPECIFIED; 1306 _rtl8723e_set_media_status(hw, opmode); 1307 if (rtlpriv->rtlhal.driver_is_goingto_unload || 1308 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1309 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1310 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1311 _rtl8723e_poweroff_adapter(hw); 1312 1313 /* after power off we should do iqk again */ 1314 rtlpriv->phy.iqk_initialized = false; 1315} 1316 1317void rtl8723e_interrupt_recognized(struct ieee80211_hw *hw, 1318 struct rtl_int *intvec) 1319{ 1320 struct rtl_priv *rtlpriv = rtl_priv(hw); 1321 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1322 1323 intvec->inta = rtl_read_dword(rtlpriv, 0x3a0) & rtlpci->irq_mask[0]; 1324 rtl_write_dword(rtlpriv, 0x3a0, intvec->inta); 1325} 1326 1327void rtl8723e_set_beacon_related_registers(struct ieee80211_hw *hw) 1328{ 1329 1330 struct rtl_priv *rtlpriv = rtl_priv(hw); 1331 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1332 u16 bcn_interval, atim_window; 1333 1334 bcn_interval = mac->beacon_interval; 1335 atim_window = 2; /*FIX MERGE */ 1336 rtl8723e_disable_interrupt(hw); 1337 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1338 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1339 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 1340 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 1341 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 1342 rtl_write_byte(rtlpriv, 0x606, 0x30); 1343 rtl8723e_enable_interrupt(hw); 1344} 1345 1346void rtl8723e_set_beacon_interval(struct ieee80211_hw *hw) 1347{ 1348 struct rtl_priv *rtlpriv = rtl_priv(hw); 1349 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1350 u16 bcn_interval = mac->beacon_interval; 1351 1352 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG, 1353 "beacon_interval:%d\n", bcn_interval); 1354 rtl8723e_disable_interrupt(hw); 1355 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1356 rtl8723e_enable_interrupt(hw); 1357} 1358 1359void rtl8723e_update_interrupt_mask(struct ieee80211_hw *hw, 1360 u32 add_msr, u32 rm_msr) 1361{ 1362 struct rtl_priv *rtlpriv = rtl_priv(hw); 1363 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1364 1365 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, 1366 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr); 1367 1368 if (add_msr) 1369 rtlpci->irq_mask[0] |= add_msr; 1370 if (rm_msr) 1371 rtlpci->irq_mask[0] &= (~rm_msr); 1372 rtl8723e_disable_interrupt(hw); 1373 rtl8723e_enable_interrupt(hw); 1374} 1375 1376static u8 _rtl8723e_get_chnl_group(u8 chnl) 1377{ 1378 u8 group; 1379 1380 if (chnl < 3) 1381 group = 0; 1382 else if (chnl < 9) 1383 group = 1; 1384 else 1385 group = 2; 1386 return group; 1387} 1388 1389static void _rtl8723e_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 1390 bool autoload_fail, 1391 u8 *hwinfo) 1392{ 1393 struct rtl_priv *rtlpriv = rtl_priv(hw); 1394 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1395 u8 rf_path, index, tempval; 1396 u16 i; 1397 1398 for (rf_path = 0; rf_path < 1; rf_path++) { 1399 for (i = 0; i < 3; i++) { 1400 if (!autoload_fail) { 1401 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] = 1402 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; 1403 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1404 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + i]; 1405 } else { 1406 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] = 1407 EEPROM_DEFAULT_TXPOWERLEVEL; 1408 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1409 EEPROM_DEFAULT_TXPOWERLEVEL; 1410 } 1411 } 1412 } 1413 1414 for (i = 0; i < 3; i++) { 1415 if (!autoload_fail) 1416 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; 1417 else 1418 tempval = EEPROM_DEFAULT_HT40_2SDIFF; 1419 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = 1420 (tempval & 0xf); 1421 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = 1422 ((tempval & 0xf0) >> 4); 1423 } 1424 1425 for (rf_path = 0; rf_path < 2; rf_path++) 1426 for (i = 0; i < 3; i++) 1427 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1428 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path, 1429 i, rtlefuse->eeprom_chnlarea_txpwr_cck 1430 [rf_path][i]); 1431 for (rf_path = 0; rf_path < 2; rf_path++) 1432 for (i = 0; i < 3; i++) 1433 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1434 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 1435 rf_path, i, 1436 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1437 [rf_path][i]); 1438 for (rf_path = 0; rf_path < 2; rf_path++) 1439 for (i = 0; i < 3; i++) 1440 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1441 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 1442 rf_path, i, 1443 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1444 [rf_path][i]); 1445 1446 for (rf_path = 0; rf_path < 2; rf_path++) { 1447 for (i = 0; i < 14; i++) { 1448 index = _rtl8723e_get_chnl_group((u8)i); 1449 1450 rtlefuse->txpwrlevel_cck[rf_path][i] = 1451 rtlefuse->eeprom_chnlarea_txpwr_cck 1452 [rf_path][index]; 1453 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 1454 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1455 [rf_path][index]; 1456 1457 if ((rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1458 [rf_path][index] - 1459 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1460 [rf_path][index]) > 0) { 1461 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 1462 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1463 [rf_path][index] - 1464 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1465 [rf_path][index]; 1466 } else { 1467 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; 1468 } 1469 } 1470 1471 for (i = 0; i < 14; i++) { 1472 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1473 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", 1474 rf_path, i, 1475 rtlefuse->txpwrlevel_cck[rf_path][i], 1476 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 1477 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 1478 } 1479 } 1480 1481 for (i = 0; i < 3; i++) { 1482 if (!autoload_fail) { 1483 rtlefuse->eeprom_pwrlimit_ht40[i] = 1484 hwinfo[EEPROM_TXPWR_GROUP + i]; 1485 rtlefuse->eeprom_pwrlimit_ht20[i] = 1486 hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; 1487 } else { 1488 rtlefuse->eeprom_pwrlimit_ht40[i] = 0; 1489 rtlefuse->eeprom_pwrlimit_ht20[i] = 0; 1490 } 1491 } 1492 1493 for (rf_path = 0; rf_path < 2; rf_path++) { 1494 for (i = 0; i < 14; i++) { 1495 index = _rtl8723e_get_chnl_group((u8)i); 1496 1497 if (rf_path == RF90_PATH_A) { 1498 rtlefuse->pwrgroup_ht20[rf_path][i] = 1499 (rtlefuse->eeprom_pwrlimit_ht20[index] & 0xf); 1500 rtlefuse->pwrgroup_ht40[rf_path][i] = 1501 (rtlefuse->eeprom_pwrlimit_ht40[index] & 0xf); 1502 } else if (rf_path == RF90_PATH_B) { 1503 rtlefuse->pwrgroup_ht20[rf_path][i] = 1504 ((rtlefuse->eeprom_pwrlimit_ht20[index] & 1505 0xf0) >> 4); 1506 rtlefuse->pwrgroup_ht40[rf_path][i] = 1507 ((rtlefuse->eeprom_pwrlimit_ht40[index] & 1508 0xf0) >> 4); 1509 } 1510 1511 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1512 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", rf_path, i, 1513 rtlefuse->pwrgroup_ht20[rf_path][i]); 1514 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1515 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", rf_path, i, 1516 rtlefuse->pwrgroup_ht40[rf_path][i]); 1517 } 1518 } 1519 1520 for (i = 0; i < 14; i++) { 1521 index = _rtl8723e_get_chnl_group((u8)i); 1522 1523 if (!autoload_fail) 1524 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; 1525 else 1526 tempval = EEPROM_DEFAULT_HT20_DIFF; 1527 1528 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 1529 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 1530 ((tempval >> 4) & 0xF); 1531 1532 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) 1533 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; 1534 1535 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) 1536 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; 1537 1538 index = _rtl8723e_get_chnl_group((u8)i); 1539 1540 if (!autoload_fail) 1541 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; 1542 else 1543 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 1544 1545 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); 1546 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 1547 ((tempval >> 4) & 0xF); 1548 } 1549 1550 rtlefuse->legacy_ht_txpowerdiff = 1551 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; 1552 1553 for (i = 0; i < 14; i++) 1554 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1555 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, 1556 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 1557 for (i = 0; i < 14; i++) 1558 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1559 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, 1560 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 1561 for (i = 0; i < 14; i++) 1562 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1563 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i, 1564 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 1565 for (i = 0; i < 14; i++) 1566 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1567 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i, 1568 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 1569 1570 if (!autoload_fail) 1571 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 1572 else 1573 rtlefuse->eeprom_regulatory = 0; 1574 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1575 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 1576 1577 if (!autoload_fail) 1578 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 1579 else 1580 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; 1581 1582 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1583 "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 1584 rtlefuse->eeprom_tssi[RF90_PATH_A], 1585 rtlefuse->eeprom_tssi[RF90_PATH_B]); 1586 1587 if (!autoload_fail) 1588 tempval = hwinfo[EEPROM_THERMAL_METER]; 1589 else 1590 tempval = EEPROM_DEFAULT_THERMALMETER; 1591 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); 1592 1593 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) 1594 rtlefuse->apk_thermalmeterignore = true; 1595 1596 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 1597 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1598 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1599} 1600 1601static void _rtl8723e_read_adapter_info(struct ieee80211_hw *hw, 1602 bool b_pseudo_test) 1603{ 1604 struct rtl_priv *rtlpriv = rtl_priv(hw); 1605 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1606 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1607 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, 1608 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 1609 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 1610 COUNTRY_CODE_WORLD_WIDE_13}; 1611 u8 *hwinfo; 1612 1613 if (b_pseudo_test) { 1614 /* need add */ 1615 return; 1616 } 1617 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 1618 if (!hwinfo) 1619 return; 1620 1621 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 1622 goto exit; 1623 1624 _rtl8723e_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag, 1625 hwinfo); 1626 1627 rtl8723e_read_bt_coexist_info_from_hwpg(hw, 1628 rtlefuse->autoload_failflag, hwinfo); 1629 1630 if (rtlhal->oem_id != RT_CID_DEFAULT) 1631 goto exit; 1632 1633 switch (rtlefuse->eeprom_oemid) { 1634 case EEPROM_CID_DEFAULT: 1635 switch (rtlefuse->eeprom_did) { 1636 case 0x8176: 1637 switch (rtlefuse->eeprom_svid) { 1638 case 0x10EC: 1639 switch (rtlefuse->eeprom_smid) { 1640 case 0x6151 ... 0x6152: 1641 case 0x6154 ... 0x6155: 1642 case 0x6177 ... 0x6180: 1643 case 0x7151 ... 0x7152: 1644 case 0x7154 ... 0x7155: 1645 case 0x7177 ... 0x7180: 1646 case 0x8151 ... 0x8152: 1647 case 0x8154 ... 0x8155: 1648 case 0x8181 ... 0x8182: 1649 case 0x8184 ... 0x8185: 1650 case 0x9151 ... 0x9152: 1651 case 0x9154 ... 0x9155: 1652 case 0x9181 ... 0x9182: 1653 case 0x9184 ... 0x9185: 1654 rtlhal->oem_id = RT_CID_TOSHIBA; 1655 break; 1656 case 0x6191 ... 0x6193: 1657 case 0x7191 ... 0x7193: 1658 case 0x8191 ... 0x8193: 1659 case 0x9191 ... 0x9193: 1660 rtlhal->oem_id = RT_CID_819X_SAMSUNG; 1661 break; 1662 case 0x8197: 1663 case 0x9196: 1664 rtlhal->oem_id = RT_CID_819X_CLEVO; 1665 break; 1666 case 0x8203: 1667 rtlhal->oem_id = RT_CID_819X_PRONETS; 1668 break; 1669 case 0x8195: 1670 case 0x9195: 1671 case 0x7194: 1672 case 0x8200 ... 0x8202: 1673 case 0x9200: 1674 rtlhal->oem_id = RT_CID_819X_LENOVO; 1675 break; 1676 } 1677 break; 1678 case 0x1025: 1679 rtlhal->oem_id = RT_CID_819X_ACER; 1680 break; 1681 case 0x1028: 1682 switch (rtlefuse->eeprom_smid) { 1683 case 0x8194: 1684 case 0x8198: 1685 case 0x9197 ... 0x9198: 1686 rtlhal->oem_id = RT_CID_819X_DELL; 1687 break; 1688 } 1689 break; 1690 case 0x103C: 1691 switch (rtlefuse->eeprom_smid) { 1692 case 0x1629: 1693 rtlhal->oem_id = RT_CID_819X_HP; 1694 } 1695 break; 1696 case 0x1A32: 1697 switch (rtlefuse->eeprom_smid) { 1698 case 0x2315: 1699 rtlhal->oem_id = RT_CID_819X_QMI; 1700 break; 1701 } 1702 break; 1703 case 0x1043: 1704 switch (rtlefuse->eeprom_smid) { 1705 case 0x84B5: 1706 rtlhal->oem_id = 1707 RT_CID_819X_EDIMAX_ASUS; 1708 } 1709 break; 1710 } 1711 break; 1712 case 0x8178: 1713 switch (rtlefuse->eeprom_svid) { 1714 case 0x10ec: 1715 switch (rtlefuse->eeprom_smid) { 1716 case 0x6181 ... 0x6182: 1717 case 0x6184 ... 0x6185: 1718 case 0x7181 ... 0x7182: 1719 case 0x7184 ... 0x7185: 1720 case 0x8181 ... 0x8182: 1721 case 0x8184 ... 0x8185: 1722 case 0x9181 ... 0x9182: 1723 case 0x9184 ... 0x9185: 1724 rtlhal->oem_id = RT_CID_TOSHIBA; 1725 break; 1726 case 0x8186: 1727 rtlhal->oem_id = 1728 RT_CID_819X_PRONETS; 1729 break; 1730 } 1731 break; 1732 case 0x1025: 1733 rtlhal->oem_id = RT_CID_819X_ACER; 1734 break; 1735 case 0x1043: 1736 switch (rtlefuse->eeprom_smid) { 1737 case 0x8486: 1738 rtlhal->oem_id = 1739 RT_CID_819X_EDIMAX_ASUS; 1740 } 1741 break; 1742 } 1743 break; 1744 } 1745 break; 1746 case EEPROM_CID_TOSHIBA: 1747 rtlhal->oem_id = RT_CID_TOSHIBA; 1748 break; 1749 case EEPROM_CID_CCX: 1750 rtlhal->oem_id = RT_CID_CCX; 1751 break; 1752 case EEPROM_CID_QMI: 1753 rtlhal->oem_id = RT_CID_819X_QMI; 1754 break; 1755 case EEPROM_CID_WHQL: 1756 break; 1757 default: 1758 rtlhal->oem_id = RT_CID_DEFAULT; 1759 break; 1760 } 1761exit: 1762 kfree(hwinfo); 1763} 1764 1765static void _rtl8723e_hal_customized_behavior(struct ieee80211_hw *hw) 1766{ 1767 struct rtl_priv *rtlpriv = rtl_priv(hw); 1768 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1769 1770 rtlpriv->ledctl.led_opendrain = true; 1771 switch (rtlhal->oem_id) { 1772 case RT_CID_819X_HP: 1773 rtlpriv->ledctl.led_opendrain = true; 1774 break; 1775 case RT_CID_819X_LENOVO: 1776 case RT_CID_DEFAULT: 1777 case RT_CID_TOSHIBA: 1778 case RT_CID_CCX: 1779 case RT_CID_819X_ACER: 1780 case RT_CID_WHQL: 1781 default: 1782 break; 1783 } 1784 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1785 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 1786} 1787 1788void rtl8723e_read_eeprom_info(struct ieee80211_hw *hw) 1789{ 1790 struct rtl_priv *rtlpriv = rtl_priv(hw); 1791 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1792 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1793 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1794 u8 tmp_u1b; 1795 u32 value32; 1796 1797 value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST]); 1798 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); 1799 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST], value32); 1800 1801 rtlhal->version = _rtl8723e_read_chip_version(hw); 1802 1803 if (get_rf_type(rtlphy) == RF_1T1R) 1804 rtlpriv->dm.rfpath_rxenable[0] = true; 1805 else 1806 rtlpriv->dm.rfpath_rxenable[0] = 1807 rtlpriv->dm.rfpath_rxenable[1] = true; 1808 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 1809 rtlhal->version); 1810 1811 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 1812 if (tmp_u1b & BIT(4)) { 1813 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 1814 rtlefuse->epromtype = EEPROM_93C46; 1815 } else { 1816 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 1817 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 1818 } 1819 if (tmp_u1b & BIT(5)) { 1820 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1821 rtlefuse->autoload_failflag = false; 1822 _rtl8723e_read_adapter_info(hw, false); 1823 } else { 1824 rtlefuse->autoload_failflag = true; 1825 _rtl8723e_read_adapter_info(hw, false); 1826 pr_err("Autoload ERR!!\n"); 1827 } 1828 _rtl8723e_hal_customized_behavior(hw); 1829} 1830 1831static void rtl8723e_update_hal_rate_table(struct ieee80211_hw *hw, 1832 struct ieee80211_sta *sta) 1833{ 1834 struct rtl_priv *rtlpriv = rtl_priv(hw); 1835 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1836 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1837 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1838 u32 ratr_value; 1839 u8 ratr_index = 0; 1840 u8 b_nmode = mac->ht_enable; 1841 u16 shortgi_rate; 1842 u32 tmp_ratr_value; 1843 u8 curtxbw_40mhz = mac->bw_40; 1844 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1845 1 : 0; 1846 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1847 1 : 0; 1848 enum wireless_mode wirelessmode = mac->mode; 1849 u32 ratr_mask; 1850 1851 if (rtlhal->current_bandtype == BAND_ON_5G) 1852 ratr_value = sta->deflink.supp_rates[1] << 4; 1853 else 1854 ratr_value = sta->deflink.supp_rates[0]; 1855 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1856 ratr_value = 0xfff; 1857 ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | 1858 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 1859 switch (wirelessmode) { 1860 case WIRELESS_MODE_B: 1861 if (ratr_value & 0x0000000c) 1862 ratr_value &= 0x0000000d; 1863 else 1864 ratr_value &= 0x0000000f; 1865 break; 1866 case WIRELESS_MODE_G: 1867 ratr_value &= 0x00000FF5; 1868 break; 1869 case WIRELESS_MODE_N_24G: 1870 case WIRELESS_MODE_N_5G: 1871 b_nmode = 1; 1872 if (get_rf_type(rtlphy) == RF_1T2R || 1873 get_rf_type(rtlphy) == RF_1T1R) 1874 ratr_mask = 0x000ff005; 1875 else 1876 ratr_mask = 0x0f0ff005; 1877 1878 ratr_value &= ratr_mask; 1879 break; 1880 default: 1881 if (rtlphy->rf_type == RF_1T2R) 1882 ratr_value &= 0x000ff0ff; 1883 else 1884 ratr_value &= 0x0f0ff0ff; 1885 1886 break; 1887 } 1888 1889 if ((rtlpriv->btcoexist.bt_coexistence) && 1890 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) && 1891 (rtlpriv->btcoexist.bt_cur_state) && 1892 (rtlpriv->btcoexist.bt_ant_isolation) && 1893 ((rtlpriv->btcoexist.bt_service == BT_SCO) || 1894 (rtlpriv->btcoexist.bt_service == BT_BUSY))) 1895 ratr_value &= 0x0fffcfc0; 1896 else 1897 ratr_value &= 0x0FFFFFFF; 1898 1899 if (b_nmode && 1900 ((curtxbw_40mhz && curshortgi_40mhz) || 1901 (!curtxbw_40mhz && curshortgi_20mhz))) { 1902 ratr_value |= 0x10000000; 1903 tmp_ratr_value = (ratr_value >> 12); 1904 1905 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 1906 if ((1 << shortgi_rate) & tmp_ratr_value) 1907 break; 1908 } 1909 1910 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 1911 (shortgi_rate << 4) | (shortgi_rate); 1912 } 1913 1914 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 1915 1916 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, 1917 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)); 1918} 1919 1920static void rtl8723e_update_hal_rate_mask(struct ieee80211_hw *hw, 1921 struct ieee80211_sta *sta, 1922 u8 rssi_level, bool update_bw) 1923{ 1924 struct rtl_priv *rtlpriv = rtl_priv(hw); 1925 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1926 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1927 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1928 struct rtl_sta_info *sta_entry = NULL; 1929 u32 ratr_bitmap; 1930 u8 ratr_index; 1931 u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) 1932 ? 1 : 0; 1933 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1934 1 : 0; 1935 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1936 1 : 0; 1937 enum wireless_mode wirelessmode = 0; 1938 bool shortgi = false; 1939 u8 rate_mask[5]; 1940 u8 macid = 0; 1941 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/ 1942 1943 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1944 wirelessmode = sta_entry->wireless_mode; 1945 if (mac->opmode == NL80211_IFTYPE_STATION) 1946 curtxbw_40mhz = mac->bw_40; 1947 else if (mac->opmode == NL80211_IFTYPE_AP || 1948 mac->opmode == NL80211_IFTYPE_ADHOC) 1949 macid = sta->aid + 1; 1950 1951 if (rtlhal->current_bandtype == BAND_ON_5G) 1952 ratr_bitmap = sta->deflink.supp_rates[1] << 4; 1953 else 1954 ratr_bitmap = sta->deflink.supp_rates[0]; 1955 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1956 ratr_bitmap = 0xfff; 1957 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | 1958 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 1959 switch (wirelessmode) { 1960 case WIRELESS_MODE_B: 1961 ratr_index = RATR_INX_WIRELESS_B; 1962 if (ratr_bitmap & 0x0000000c) 1963 ratr_bitmap &= 0x0000000d; 1964 else 1965 ratr_bitmap &= 0x0000000f; 1966 break; 1967 case WIRELESS_MODE_G: 1968 ratr_index = RATR_INX_WIRELESS_GB; 1969 1970 if (rssi_level == 1) 1971 ratr_bitmap &= 0x00000f00; 1972 else if (rssi_level == 2) 1973 ratr_bitmap &= 0x00000ff0; 1974 else 1975 ratr_bitmap &= 0x00000ff5; 1976 break; 1977 case WIRELESS_MODE_A: 1978 ratr_index = RATR_INX_WIRELESS_G; 1979 ratr_bitmap &= 0x00000ff0; 1980 break; 1981 case WIRELESS_MODE_N_24G: 1982 case WIRELESS_MODE_N_5G: 1983 ratr_index = RATR_INX_WIRELESS_NGB; 1984 if (rtlphy->rf_type == RF_1T2R || 1985 rtlphy->rf_type == RF_1T1R) { 1986 if (curtxbw_40mhz) { 1987 if (rssi_level == 1) 1988 ratr_bitmap &= 0x000f0000; 1989 else if (rssi_level == 2) 1990 ratr_bitmap &= 0x000ff000; 1991 else 1992 ratr_bitmap &= 0x000ff015; 1993 } else { 1994 if (rssi_level == 1) 1995 ratr_bitmap &= 0x000f0000; 1996 else if (rssi_level == 2) 1997 ratr_bitmap &= 0x000ff000; 1998 else 1999 ratr_bitmap &= 0x000ff005; 2000 } 2001 } else { 2002 if (curtxbw_40mhz) { 2003 if (rssi_level == 1) 2004 ratr_bitmap &= 0x0f0f0000; 2005 else if (rssi_level == 2) 2006 ratr_bitmap &= 0x0f0ff000; 2007 else 2008 ratr_bitmap &= 0x0f0ff015; 2009 } else { 2010 if (rssi_level == 1) 2011 ratr_bitmap &= 0x0f0f0000; 2012 else if (rssi_level == 2) 2013 ratr_bitmap &= 0x0f0ff000; 2014 else 2015 ratr_bitmap &= 0x0f0ff005; 2016 } 2017 } 2018 2019 if ((curtxbw_40mhz && curshortgi_40mhz) || 2020 (!curtxbw_40mhz && curshortgi_20mhz)) { 2021 if (macid == 0) 2022 shortgi = true; 2023 else if (macid == 1) 2024 shortgi = false; 2025 } 2026 break; 2027 default: 2028 ratr_index = RATR_INX_WIRELESS_NGB; 2029 2030 if (rtlphy->rf_type == RF_1T2R) 2031 ratr_bitmap &= 0x000ff0ff; 2032 else 2033 ratr_bitmap &= 0x0f0ff0ff; 2034 break; 2035 } 2036 sta_entry->ratr_index = ratr_index; 2037 2038 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, 2039 "ratr_bitmap :%x\n", ratr_bitmap); 2040 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2041 (ratr_index << 28); 2042 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 2043 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, 2044 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n", 2045 ratr_index, ratr_bitmap, 2046 rate_mask[0], rate_mask[1], 2047 rate_mask[2], rate_mask[3], 2048 rate_mask[4]); 2049 rtl8723e_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask); 2050} 2051 2052void rtl8723e_update_hal_rate_tbl(struct ieee80211_hw *hw, 2053 struct ieee80211_sta *sta, u8 rssi_level, 2054 bool update_bw) 2055{ 2056 struct rtl_priv *rtlpriv = rtl_priv(hw); 2057 2058 if (rtlpriv->dm.useramask) 2059 rtl8723e_update_hal_rate_mask(hw, sta, rssi_level, update_bw); 2060 else 2061 rtl8723e_update_hal_rate_table(hw, sta); 2062} 2063 2064void rtl8723e_update_channel_access_setting(struct ieee80211_hw *hw) 2065{ 2066 struct rtl_priv *rtlpriv = rtl_priv(hw); 2067 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2068 u16 sifs_timer; 2069 2070 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time); 2071 if (!mac->ht_enable) 2072 sifs_timer = 0x0a0a; 2073 else 2074 sifs_timer = 0x1010; 2075 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2076} 2077 2078bool rtl8723e_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2079{ 2080 struct rtl_priv *rtlpriv = rtl_priv(hw); 2081 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2082 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2083 enum rf_pwrstate e_rfpowerstate_toset; 2084 u8 u1tmp; 2085 bool b_actuallyset = false; 2086 2087 if (rtlpriv->rtlhal.being_init_adapter) 2088 return false; 2089 2090 if (ppsc->swrf_processing) 2091 return false; 2092 2093 spin_lock(&rtlpriv->locks.rf_ps_lock); 2094 if (ppsc->rfchange_inprogress) { 2095 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2096 return false; 2097 } else { 2098 ppsc->rfchange_inprogress = true; 2099 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2100 } 2101 2102 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2, 2103 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2)&~(BIT(1))); 2104 2105 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2); 2106 2107 if (rtlphy->polarity_ctl) 2108 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON; 2109 else 2110 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF; 2111 2112 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) { 2113 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2114 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2115 2116 e_rfpowerstate_toset = ERFON; 2117 ppsc->hwradiooff = false; 2118 b_actuallyset = true; 2119 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) { 2120 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2121 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 2122 2123 e_rfpowerstate_toset = ERFOFF; 2124 ppsc->hwradiooff = true; 2125 b_actuallyset = true; 2126 } 2127 2128 if (b_actuallyset) { 2129 spin_lock(&rtlpriv->locks.rf_ps_lock); 2130 ppsc->rfchange_inprogress = false; 2131 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2132 } else { 2133 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 2134 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2135 2136 spin_lock(&rtlpriv->locks.rf_ps_lock); 2137 ppsc->rfchange_inprogress = false; 2138 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2139 } 2140 2141 *valid = 1; 2142 return !ppsc->hwradiooff; 2143 2144} 2145 2146void rtl8723e_set_key(struct ieee80211_hw *hw, u32 key_index, 2147 u8 *p_macaddr, bool is_group, u8 enc_algo, 2148 bool is_wepkey, bool clear_all) 2149{ 2150 struct rtl_priv *rtlpriv = rtl_priv(hw); 2151 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2152 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2153 u8 *macaddr = p_macaddr; 2154 u32 entry_id = 0; 2155 bool is_pairwise = false; 2156 2157 static u8 cam_const_addr[4][6] = { 2158 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2159 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2160 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2161 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2162 }; 2163 static u8 cam_const_broad[] = { 2164 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2165 }; 2166 2167 if (clear_all) { 2168 u8 idx = 0; 2169 u8 cam_offset = 0; 2170 u8 clear_number = 5; 2171 2172 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2173 2174 for (idx = 0; idx < clear_number; idx++) { 2175 rtl_cam_mark_invalid(hw, cam_offset + idx); 2176 rtl_cam_empty_entry(hw, cam_offset + idx); 2177 2178 if (idx < 5) { 2179 memset(rtlpriv->sec.key_buf[idx], 0, 2180 MAX_KEY_LEN); 2181 rtlpriv->sec.key_len[idx] = 0; 2182 } 2183 } 2184 2185 } else { 2186 switch (enc_algo) { 2187 case WEP40_ENCRYPTION: 2188 enc_algo = CAM_WEP40; 2189 break; 2190 case WEP104_ENCRYPTION: 2191 enc_algo = CAM_WEP104; 2192 break; 2193 case TKIP_ENCRYPTION: 2194 enc_algo = CAM_TKIP; 2195 break; 2196 case AESCCMP_ENCRYPTION: 2197 enc_algo = CAM_AES; 2198 break; 2199 default: 2200 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 2201 "switch case %#x not processed\n", enc_algo); 2202 enc_algo = CAM_TKIP; 2203 break; 2204 } 2205 2206 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2207 macaddr = cam_const_addr[key_index]; 2208 entry_id = key_index; 2209 } else { 2210 if (is_group) { 2211 macaddr = cam_const_broad; 2212 entry_id = key_index; 2213 } else { 2214 if (mac->opmode == NL80211_IFTYPE_AP) { 2215 entry_id = 2216 rtl_cam_get_free_entry(hw, p_macaddr); 2217 if (entry_id >= TOTAL_CAM_ENTRY) { 2218 pr_err("Can not find free hw security cam entry\n"); 2219 return; 2220 } 2221 } else { 2222 entry_id = CAM_PAIRWISE_KEY_POSITION; 2223 } 2224 2225 key_index = PAIRWISE_KEYIDX; 2226 is_pairwise = true; 2227 } 2228 } 2229 2230 if (rtlpriv->sec.key_len[key_index] == 0) { 2231 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2232 "delete one entry, entry_id is %d\n", 2233 entry_id); 2234 if (mac->opmode == NL80211_IFTYPE_AP) 2235 rtl_cam_del_entry(hw, p_macaddr); 2236 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2237 } else { 2238 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2239 "add one entry\n"); 2240 if (is_pairwise) { 2241 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2242 "set Pairwise key\n"); 2243 2244 rtl_cam_add_one_entry(hw, macaddr, key_index, 2245 entry_id, enc_algo, 2246 CAM_CONFIG_NO_USEDK, 2247 rtlpriv->sec.key_buf[key_index]); 2248 } else { 2249 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2250 "set group key\n"); 2251 2252 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2253 rtl_cam_add_one_entry(hw, 2254 rtlefuse->dev_addr, 2255 PAIRWISE_KEYIDX, 2256 CAM_PAIRWISE_KEY_POSITION, 2257 enc_algo, 2258 CAM_CONFIG_NO_USEDK, 2259 rtlpriv->sec.key_buf 2260 [entry_id]); 2261 } 2262 2263 rtl_cam_add_one_entry(hw, macaddr, key_index, 2264 entry_id, enc_algo, 2265 CAM_CONFIG_NO_USEDK, 2266 rtlpriv->sec.key_buf[entry_id]); 2267 } 2268 2269 } 2270 } 2271} 2272 2273static void rtl8723e_bt_var_init(struct ieee80211_hw *hw) 2274{ 2275 struct rtl_priv *rtlpriv = rtl_priv(hw); 2276 2277 rtlpriv->btcoexist.bt_coexistence = 2278 rtlpriv->btcoexist.eeprom_bt_coexist; 2279 rtlpriv->btcoexist.bt_ant_num = 2280 rtlpriv->btcoexist.eeprom_bt_ant_num; 2281 rtlpriv->btcoexist.bt_coexist_type = 2282 rtlpriv->btcoexist.eeprom_bt_type; 2283 2284 rtlpriv->btcoexist.bt_ant_isolation = 2285 rtlpriv->btcoexist.eeprom_bt_ant_isol; 2286 2287 rtlpriv->btcoexist.bt_radio_shared_type = 2288 rtlpriv->btcoexist.eeprom_bt_radio_shared; 2289 2290 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2291 "BT Coexistence = 0x%x\n", 2292 rtlpriv->btcoexist.bt_coexistence); 2293 2294 if (rtlpriv->btcoexist.bt_coexistence) { 2295 rtlpriv->btcoexist.bt_busy_traffic = false; 2296 rtlpriv->btcoexist.bt_traffic_mode_set = false; 2297 rtlpriv->btcoexist.bt_non_traffic_mode_set = false; 2298 2299 rtlpriv->btcoexist.cstate = 0; 2300 rtlpriv->btcoexist.previous_state = 0; 2301 2302 if (rtlpriv->btcoexist.bt_ant_num == ANT_X2) { 2303 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2304 "BlueTooth BT_Ant_Num = Antx2\n"); 2305 } else if (rtlpriv->btcoexist.bt_ant_num == ANT_X1) { 2306 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2307 "BlueTooth BT_Ant_Num = Antx1\n"); 2308 } 2309 switch (rtlpriv->btcoexist.bt_coexist_type) { 2310 case BT_2WIRE: 2311 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2312 "BlueTooth BT_CoexistType = BT_2Wire\n"); 2313 break; 2314 case BT_ISSC_3WIRE: 2315 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2316 "BlueTooth BT_CoexistType = BT_ISSC_3Wire\n"); 2317 break; 2318 case BT_ACCEL: 2319 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2320 "BlueTooth BT_CoexistType = BT_ACCEL\n"); 2321 break; 2322 case BT_CSR_BC4: 2323 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2324 "BlueTooth BT_CoexistType = BT_CSR_BC4\n"); 2325 break; 2326 case BT_CSR_BC8: 2327 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2328 "BlueTooth BT_CoexistType = BT_CSR_BC8\n"); 2329 break; 2330 case BT_RTL8756: 2331 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2332 "BlueTooth BT_CoexistType = BT_RTL8756\n"); 2333 break; 2334 default: 2335 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2336 "BlueTooth BT_CoexistType = Unknown\n"); 2337 break; 2338 } 2339 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2340 "BlueTooth BT_Ant_isolation = %d\n", 2341 rtlpriv->btcoexist.bt_ant_isolation); 2342 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2343 "BT_RadioSharedType = 0x%x\n", 2344 rtlpriv->btcoexist.bt_radio_shared_type); 2345 rtlpriv->btcoexist.bt_active_zero_cnt = 0; 2346 rtlpriv->btcoexist.cur_bt_disabled = false; 2347 rtlpriv->btcoexist.pre_bt_disabled = false; 2348 } 2349} 2350 2351void rtl8723e_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 2352 bool auto_load_fail, u8 *hwinfo) 2353{ 2354 struct rtl_priv *rtlpriv = rtl_priv(hw); 2355 u8 value; 2356 u32 tmpu_32; 2357 2358 if (!auto_load_fail) { 2359 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 2360 if (tmpu_32 & BIT(18)) 2361 rtlpriv->btcoexist.eeprom_bt_coexist = 1; 2362 else 2363 rtlpriv->btcoexist.eeprom_bt_coexist = 0; 2364 value = hwinfo[RF_OPTION4]; 2365 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A; 2366 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1); 2367 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4); 2368 rtlpriv->btcoexist.eeprom_bt_radio_shared = 2369 ((value & 0x20) >> 5); 2370 } else { 2371 rtlpriv->btcoexist.eeprom_bt_coexist = 0; 2372 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A; 2373 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2; 2374 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0; 2375 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED; 2376 } 2377 2378 rtl8723e_bt_var_init(hw); 2379} 2380 2381void rtl8723e_bt_reg_init(struct ieee80211_hw *hw) 2382{ 2383 struct rtl_priv *rtlpriv = rtl_priv(hw); 2384 2385 /* 0:Low, 1:High, 2:From Efuse. */ 2386 rtlpriv->btcoexist.reg_bt_iso = 2; 2387 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 2388 rtlpriv->btcoexist.reg_bt_sco = 3; 2389 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 2390 rtlpriv->btcoexist.reg_bt_sco = 0; 2391} 2392 2393void rtl8723e_bt_hw_init(struct ieee80211_hw *hw) 2394{ 2395 struct rtl_priv *rtlpriv = rtl_priv(hw); 2396 2397 if (rtlpriv->cfg->ops->get_btc_status()) 2398 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv); 2399} 2400 2401void rtl8723e_suspend(struct ieee80211_hw *hw) 2402{ 2403} 2404 2405void rtl8723e_resume(struct ieee80211_hw *hw) 2406{ 2407} 2408