1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4#include "../wifi.h" 5#include "../efuse.h" 6#include "../base.h" 7#include "../regd.h" 8#include "../cam.h" 9#include "../ps.h" 10#include "../pci.h" 11#include "reg.h" 12#include "def.h" 13#include "phy.h" 14#include "dm.h" 15#include "fw.h" 16#include "led.h" 17#include "sw.h" 18#include "hw.h" 19 20u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct) 21{ 22 struct rtl_priv *rtlpriv = rtl_priv(hw); 23 u32 value; 24 25 rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC)); 26 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct); 27 udelay(10); 28 value = rtl_read_dword(rtlpriv, REG_DBI_RDATA); 29 return value; 30} 31 32void rtl92de_write_dword_dbi(struct ieee80211_hw *hw, 33 u16 offset, u32 value, u8 direct) 34{ 35 struct rtl_priv *rtlpriv = rtl_priv(hw); 36 37 rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000)); 38 rtl_write_dword(rtlpriv, REG_DBI_WDATA, value); 39 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct); 40} 41 42static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 43 u8 set_bits, u8 clear_bits) 44{ 45 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 46 struct rtl_priv *rtlpriv = rtl_priv(hw); 47 48 rtlpci->reg_bcn_ctrl_val |= set_bits; 49 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 50 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); 51} 52 53static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw) 54{ 55 struct rtl_priv *rtlpriv = rtl_priv(hw); 56 u8 tmp1byte; 57 58 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 59 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 60 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); 61 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 62 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 63 tmp1byte &= ~(BIT(0)); 64 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 65} 66 67static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw) 68{ 69 struct rtl_priv *rtlpriv = rtl_priv(hw); 70 u8 tmp1byte; 71 72 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 73 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 74 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); 75 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 76 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 77 tmp1byte |= BIT(0); 78 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 79} 80 81static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw) 82{ 83 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1)); 84} 85 86static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw) 87{ 88 _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0); 89} 90 91void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 92{ 93 struct rtl_priv *rtlpriv = rtl_priv(hw); 94 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 95 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 96 97 switch (variable) { 98 case HW_VAR_RCR: 99 *((u32 *) (val)) = rtlpci->receive_config; 100 break; 101 case HW_VAR_RF_STATE: 102 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 103 break; 104 case HW_VAR_FWLPS_RF_ON:{ 105 enum rf_pwrstate rfstate; 106 u32 val_rcr; 107 108 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, 109 (u8 *)(&rfstate)); 110 if (rfstate == ERFOFF) { 111 *((bool *) (val)) = true; 112 } else { 113 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 114 val_rcr &= 0x00070000; 115 if (val_rcr) 116 *((bool *) (val)) = false; 117 else 118 *((bool *) (val)) = true; 119 } 120 break; 121 } 122 case HW_VAR_FW_PSMODE_STATUS: 123 *((bool *) (val)) = ppsc->fw_current_inpsmode; 124 break; 125 case HW_VAR_CORRECT_TSF:{ 126 u64 tsf; 127 u32 *ptsf_low = (u32 *)&tsf; 128 u32 *ptsf_high = ((u32 *)&tsf) + 1; 129 130 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 131 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 132 *((u64 *) (val)) = tsf; 133 break; 134 } 135 case HW_VAR_INT_MIGRATION: 136 *((bool *)(val)) = rtlpriv->dm.interrupt_migration; 137 break; 138 case HW_VAR_INT_AC: 139 *((bool *)(val)) = rtlpriv->dm.disable_tx_int; 140 break; 141 case HAL_DEF_WOWLAN: 142 break; 143 default: 144 pr_err("switch case %#x not processed\n", variable); 145 break; 146 } 147} 148 149void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 150{ 151 struct rtl_priv *rtlpriv = rtl_priv(hw); 152 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 153 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 154 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 155 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 156 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 157 u8 idx; 158 159 switch (variable) { 160 case HW_VAR_ETHER_ADDR: 161 for (idx = 0; idx < ETH_ALEN; idx++) { 162 rtl_write_byte(rtlpriv, (REG_MACID + idx), 163 val[idx]); 164 } 165 break; 166 case HW_VAR_BASIC_RATE: { 167 u16 rate_cfg = ((u16 *) val)[0]; 168 u8 rate_index = 0; 169 170 rate_cfg = rate_cfg & 0x15f; 171 if (mac->vendor == PEER_CISCO && 172 ((rate_cfg & 0x150) == 0)) 173 rate_cfg |= 0x01; 174 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); 175 rtl_write_byte(rtlpriv, REG_RRSR + 1, 176 (rate_cfg >> 8) & 0xff); 177 while (rate_cfg > 0x1) { 178 rate_cfg = (rate_cfg >> 1); 179 rate_index++; 180 } 181 if (rtlhal->fw_version > 0xe) 182 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 183 rate_index); 184 break; 185 } 186 case HW_VAR_BSSID: 187 for (idx = 0; idx < ETH_ALEN; idx++) { 188 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 189 val[idx]); 190 } 191 break; 192 case HW_VAR_SIFS: 193 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 194 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); 195 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 196 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 197 if (!mac->ht_enable) 198 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 199 0x0e0e); 200 else 201 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 202 *((u16 *) val)); 203 break; 204 case HW_VAR_SLOT_TIME: { 205 u8 e_aci; 206 207 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 208 "HW_VAR_SLOT_TIME %x\n", val[0]); 209 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 210 for (e_aci = 0; e_aci < AC_MAX; e_aci++) 211 rtlpriv->cfg->ops->set_hw_reg(hw, 212 HW_VAR_AC_PARAM, 213 (&e_aci)); 214 break; 215 } 216 case HW_VAR_ACK_PREAMBLE: { 217 u8 reg_tmp; 218 u8 short_preamble = (bool) (*val); 219 220 reg_tmp = (mac->cur_40_prime_sc) << 5; 221 if (short_preamble) 222 reg_tmp |= 0x80; 223 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 224 break; 225 } 226 case HW_VAR_AMPDU_MIN_SPACE: { 227 u8 min_spacing_to_set; 228 u8 sec_min_space; 229 230 min_spacing_to_set = *val; 231 if (min_spacing_to_set <= 7) { 232 sec_min_space = 0; 233 if (min_spacing_to_set < sec_min_space) 234 min_spacing_to_set = sec_min_space; 235 mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) | 236 min_spacing_to_set); 237 *val = min_spacing_to_set; 238 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 239 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 240 mac->min_space_cfg); 241 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 242 mac->min_space_cfg); 243 } 244 break; 245 } 246 case HW_VAR_SHORTGI_DENSITY: { 247 u8 density_to_set; 248 249 density_to_set = *val; 250 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg; 251 mac->min_space_cfg |= (density_to_set << 3); 252 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 253 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 254 mac->min_space_cfg); 255 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 256 mac->min_space_cfg); 257 break; 258 } 259 case HW_VAR_AMPDU_FACTOR: { 260 u8 factor_toset; 261 u32 regtoset; 262 u8 *ptmp_byte = NULL; 263 u8 index; 264 265 if (rtlhal->macphymode == DUALMAC_DUALPHY) 266 regtoset = 0xb9726641; 267 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY) 268 regtoset = 0x66626641; 269 else 270 regtoset = 0xb972a841; 271 factor_toset = *val; 272 if (factor_toset <= 3) { 273 factor_toset = (1 << (factor_toset + 2)); 274 if (factor_toset > 0xf) 275 factor_toset = 0xf; 276 for (index = 0; index < 4; index++) { 277 ptmp_byte = (u8 *)(®toset) + index; 278 if ((*ptmp_byte & 0xf0) > 279 (factor_toset << 4)) 280 *ptmp_byte = (*ptmp_byte & 0x0f) 281 | (factor_toset << 4); 282 if ((*ptmp_byte & 0x0f) > factor_toset) 283 *ptmp_byte = (*ptmp_byte & 0xf0) 284 | (factor_toset); 285 } 286 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoset); 287 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 288 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 289 factor_toset); 290 } 291 break; 292 } 293 case HW_VAR_AC_PARAM: { 294 u8 e_aci = *val; 295 rtl92d_dm_init_edca_turbo(hw); 296 if (rtlpci->acm_method != EACMWAY2_SW) 297 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL, 298 &e_aci); 299 break; 300 } 301 case HW_VAR_ACM_CTRL: { 302 u8 e_aci = *val; 303 union aci_aifsn *p_aci_aifsn = 304 (union aci_aifsn *)(&(mac->ac[0].aifs)); 305 u8 acm = p_aci_aifsn->f.acm; 306 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 307 308 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 309 if (acm) { 310 switch (e_aci) { 311 case AC0_BE: 312 acm_ctrl |= ACMHW_BEQEN; 313 break; 314 case AC2_VI: 315 acm_ctrl |= ACMHW_VIQEN; 316 break; 317 case AC3_VO: 318 acm_ctrl |= ACMHW_VOQEN; 319 break; 320 default: 321 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 322 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 323 acm); 324 break; 325 } 326 } else { 327 switch (e_aci) { 328 case AC0_BE: 329 acm_ctrl &= (~ACMHW_BEQEN); 330 break; 331 case AC2_VI: 332 acm_ctrl &= (~ACMHW_VIQEN); 333 break; 334 case AC3_VO: 335 acm_ctrl &= (~ACMHW_VOQEN); 336 break; 337 default: 338 pr_err("switch case %#x not processed\n", 339 e_aci); 340 break; 341 } 342 } 343 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE, 344 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 345 acm_ctrl); 346 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 347 break; 348 } 349 case HW_VAR_RCR: 350 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); 351 rtlpci->receive_config = ((u32 *) (val))[0]; 352 break; 353 case HW_VAR_RETRY_LIMIT: { 354 u8 retry_limit = val[0]; 355 356 rtl_write_word(rtlpriv, REG_RL, 357 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 358 retry_limit << RETRY_LIMIT_LONG_SHIFT); 359 break; 360 } 361 case HW_VAR_DUAL_TSF_RST: 362 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 363 break; 364 case HW_VAR_EFUSE_BYTES: 365 rtlefuse->efuse_usedbytes = *((u16 *) val); 366 break; 367 case HW_VAR_EFUSE_USAGE: 368 rtlefuse->efuse_usedpercentage = *val; 369 break; 370 case HW_VAR_IO_CMD: 371 rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val)); 372 break; 373 case HW_VAR_WPA_CONFIG: 374 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 375 break; 376 case HW_VAR_SET_RPWM: 377 rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val)); 378 break; 379 case HW_VAR_H2C_FW_PWRMODE: 380 break; 381 case HW_VAR_FW_PSMODE_STATUS: 382 ppsc->fw_current_inpsmode = *((bool *) val); 383 break; 384 case HW_VAR_H2C_FW_JOINBSSRPT: { 385 u8 mstatus = (*val); 386 u8 tmp_regcr, tmp_reg422; 387 bool recover = false; 388 389 if (mstatus == RT_MEDIA_CONNECT) { 390 rtlpriv->cfg->ops->set_hw_reg(hw, 391 HW_VAR_AID, NULL); 392 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 393 rtl_write_byte(rtlpriv, REG_CR + 1, 394 (tmp_regcr | BIT(0))); 395 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); 396 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0); 397 tmp_reg422 = rtl_read_byte(rtlpriv, 398 REG_FWHW_TXQ_CTRL + 2); 399 if (tmp_reg422 & BIT(6)) 400 recover = true; 401 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 402 tmp_reg422 & (~BIT(6))); 403 rtl92d_set_fw_rsvdpagepkt(hw, 0); 404 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); 405 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4)); 406 if (recover) 407 rtl_write_byte(rtlpriv, 408 REG_FWHW_TXQ_CTRL + 2, 409 tmp_reg422); 410 rtl_write_byte(rtlpriv, REG_CR + 1, 411 (tmp_regcr & ~(BIT(0)))); 412 } 413 rtl92d_set_fw_joinbss_report_cmd(hw, (*val)); 414 break; 415 } 416 case HW_VAR_AID: { 417 u16 u2btmp; 418 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 419 u2btmp &= 0xC000; 420 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | 421 mac->assoc_id)); 422 break; 423 } 424 case HW_VAR_CORRECT_TSF: { 425 u8 btype_ibss = val[0]; 426 427 if (btype_ibss) 428 _rtl92de_stop_tx_beacon(hw); 429 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); 430 rtl_write_dword(rtlpriv, REG_TSFTR, 431 (u32) (mac->tsf & 0xffffffff)); 432 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 433 (u32) ((mac->tsf >> 32) & 0xffffffff)); 434 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); 435 if (btype_ibss) 436 _rtl92de_resume_tx_beacon(hw); 437 438 break; 439 } 440 case HW_VAR_INT_MIGRATION: { 441 bool int_migration = *(bool *) (val); 442 443 if (int_migration) { 444 /* Set interrupt migration timer and 445 * corresponding Tx/Rx counter. 446 * timer 25ns*0xfa0=100us for 0xf packets. 447 * 0x306:Rx, 0x307:Tx */ 448 rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0); 449 rtlpriv->dm.interrupt_migration = int_migration; 450 } else { 451 /* Reset all interrupt migration settings. */ 452 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 453 rtlpriv->dm.interrupt_migration = int_migration; 454 } 455 break; 456 } 457 case HW_VAR_INT_AC: { 458 bool disable_ac_int = *((bool *) val); 459 460 /* Disable four ACs interrupts. */ 461 if (disable_ac_int) { 462 /* Disable VO, VI, BE and BK four AC interrupts 463 * to gain more efficient CPU utilization. 464 * When extremely highly Rx OK occurs, 465 * we will disable Tx interrupts. 466 */ 467 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0, 468 RT_AC_INT_MASKS); 469 rtlpriv->dm.disable_tx_int = disable_ac_int; 470 /* Enable four ACs interrupts. */ 471 } else { 472 rtlpriv->cfg->ops->update_interrupt_mask(hw, 473 RT_AC_INT_MASKS, 0); 474 rtlpriv->dm.disable_tx_int = disable_ac_int; 475 } 476 break; 477 } 478 default: 479 pr_err("switch case %#x not processed\n", variable); 480 break; 481 } 482} 483 484static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 485{ 486 struct rtl_priv *rtlpriv = rtl_priv(hw); 487 bool status = true; 488 long count = 0; 489 u32 value = _LLT_INIT_ADDR(address) | 490 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); 491 492 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 493 do { 494 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 495 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 496 break; 497 if (count > POLLING_LLT_THRESHOLD) { 498 pr_err("Failed to polling write LLT done at address %d!\n", 499 address); 500 status = false; 501 break; 502 } 503 } while (++count); 504 return status; 505} 506 507static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw) 508{ 509 struct rtl_priv *rtlpriv = rtl_priv(hw); 510 unsigned short i; 511 u8 txpktbuf_bndy; 512 u8 maxpage; 513 bool status; 514 u32 value32; /* High+low page number */ 515 u8 value8; /* normal page number */ 516 517 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { 518 maxpage = 255; 519 txpktbuf_bndy = 246; 520 value8 = 0; 521 value32 = 0x80bf0d29; 522 } else { 523 maxpage = 127; 524 txpktbuf_bndy = 123; 525 value8 = 0; 526 value32 = 0x80750005; 527 } 528 529 /* Set reserved page for each queue */ 530 /* 11. RQPN 0x200[31:0] = 0x80BD1C1C */ 531 /* load RQPN */ 532 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); 533 rtl_write_dword(rtlpriv, REG_RQPN, value32); 534 535 /* 12. TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */ 536 /* TXRKTBUG_PG_BNDY */ 537 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, 538 (rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 | 539 txpktbuf_bndy)); 540 541 /* 13. TDECTRL[15:8] 0x209[7:0] = 0xF6 */ 542 /* Beacon Head for TXDMA */ 543 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 544 545 /* 14. BCNQ_PGBNDY 0x424[7:0] = 0xF6 */ 546 /* BCNQ_PGBNDY */ 547 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 548 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 549 550 /* 15. WMAC_LBK_BF_HD 0x45D[7:0] = 0xF6 */ 551 /* WMAC_LBK_BF_HD */ 552 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); 553 554 /* Set Tx/Rx page size (Tx must be 128 Bytes, */ 555 /* Rx can be 64,128,256,512,1024 bytes) */ 556 /* 16. PBP [7:0] = 0x11 */ 557 /* TRX page size */ 558 rtl_write_byte(rtlpriv, REG_PBP, 0x11); 559 560 /* 17. DRV_INFO_SZ = 0x04 */ 561 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 562 563 /* 18. LLT_table_init(Adapter); */ 564 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 565 status = _rtl92de_llt_write(hw, i, i + 1); 566 if (!status) 567 return status; 568 } 569 570 /* end of list */ 571 status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 572 if (!status) 573 return status; 574 575 /* Make the other pages as ring buffer */ 576 /* This ring buffer is used as beacon buffer if we */ 577 /* config this MAC as two MAC transfer. */ 578 /* Otherwise used as local loopback buffer. */ 579 for (i = txpktbuf_bndy; i < maxpage; i++) { 580 status = _rtl92de_llt_write(hw, i, (i + 1)); 581 if (!status) 582 return status; 583 } 584 585 /* Let last entry point to the start entry of ring buffer */ 586 status = _rtl92de_llt_write(hw, maxpage, txpktbuf_bndy); 587 if (!status) 588 return status; 589 590 return true; 591} 592 593static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw) 594{ 595 struct rtl_priv *rtlpriv = rtl_priv(hw); 596 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 597 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 598 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0; 599 600 if (rtlpci->up_first_time) 601 return; 602 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 603 rtl92de_sw_led_on(hw, pin0); 604 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 605 rtl92de_sw_led_on(hw, pin0); 606 else 607 rtl92de_sw_led_off(hw, pin0); 608} 609 610static bool _rtl92de_init_mac(struct ieee80211_hw *hw) 611{ 612 struct rtl_priv *rtlpriv = rtl_priv(hw); 613 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 614 unsigned char bytetmp; 615 unsigned short wordtmp; 616 u16 retry; 617 618 rtl92d_phy_set_poweron(hw); 619 /* Add for resume sequence of power domain according 620 * to power document V11. Chapter V.11.... */ 621 /* 0. RSV_CTRL 0x1C[7:0] = 0x00 */ 622 /* unlock ISO/CLK/Power control register */ 623 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 624 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05); 625 626 /* 1. AFE_XTAL_CTRL [7:0] = 0x0F enable XTAL */ 627 /* 2. SPS0_CTRL 0x11[7:0] = 0x2b enable SPS into PWM mode */ 628 /* 3. delay (1ms) this is not necessary when initially power on */ 629 630 /* C. Resume Sequence */ 631 /* a. SPS0_CTRL 0x11[7:0] = 0x2b */ 632 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 633 634 /* b. AFE_XTAL_CTRL [7:0] = 0x0F */ 635 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F); 636 637 /* c. DRV runs power on init flow */ 638 639 /* auto enable WLAN */ 640 /* 4. APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0 */ 641 /* Power On Reset for MAC Block */ 642 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); 643 udelay(2); 644 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); 645 udelay(2); 646 647 /* 5. Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */ 648 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); 649 udelay(50); 650 retry = 0; 651 while ((bytetmp & BIT(0)) && retry < 1000) { 652 retry++; 653 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); 654 udelay(50); 655 } 656 657 /* Enable Radio off, GPIO, and LED function */ 658 /* 6. APS_FSMCO 0x04[15:0] = 0x0012 when enable HWPDN */ 659 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012); 660 661 /* release RF digital isolation */ 662 /* 7. SYS_ISO_CTRL 0x01[1] = 0x0; */ 663 /*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */ 664 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82); 665 udelay(2); 666 667 /* make sure that BB reset OK. */ 668 /* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */ 669 670 /* Disable REG_CR before enable it to assure reset */ 671 rtl_write_word(rtlpriv, REG_CR, 0x0); 672 673 /* Release MAC IO register reset */ 674 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 675 676 /* clear stopping tx/rx dma */ 677 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0); 678 679 /* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */ 680 681 /* System init */ 682 /* 18. LLT_table_init(Adapter); */ 683 if (!_rtl92de_llt_table_init(hw)) 684 return false; 685 686 /* Clear interrupt and enable interrupt */ 687 /* 19. HISR 0x124[31:0] = 0xffffffff; */ 688 /* HISRE 0x12C[7:0] = 0xFF */ 689 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 690 rtl_write_byte(rtlpriv, REG_HISRE, 0xff); 691 692 /* 20. HIMR 0x120[31:0] |= [enable INT mask bit map]; */ 693 /* 21. HIMRE 0x128[7:0] = [enable INT mask bit map] */ 694 /* The IMR should be enabled later after all init sequence 695 * is finished. */ 696 697 /* 22. PCIE configuration space configuration */ 698 /* 23. Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ), */ 699 /* and PCIe gated clock function is enabled. */ 700 /* PCIE configuration space will be written after 701 * all init sequence.(Or by BIOS) */ 702 703 rtl92d_phy_config_maccoexist_rfpage(hw); 704 705 /* THe below section is not related to power document Vxx . */ 706 /* This is only useful for driver and OS setting. */ 707 /* -------------------Software Relative Setting---------------------- */ 708 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 709 wordtmp &= 0xf; 710 wordtmp |= 0xF771; 711 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 712 713 /* Reported Tx status from HW for rate adaptive. */ 714 /* This should be realtive to power on step 14. But in document V11 */ 715 /* still not contain the description.!!! */ 716 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 717 718 /* Set Tx/Rx page size (Tx must be 128 Bytes, 719 * Rx can be 64,128,256,512,1024 bytes) */ 720 /* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */ 721 722 /* Set RCR register */ 723 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 724 /* rtl_write_byte(rtlpriv,REG_RX_DRVINFO_SZ, 4); */ 725 726 /* Set TCR register */ 727 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); 728 729 /* disable earlymode */ 730 rtl_write_byte(rtlpriv, 0x4d0, 0x0); 731 732 /* Set TX/RX descriptor physical address(from OS API). */ 733 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 734 rtlpci->tx_ring[BEACON_QUEUE].dma); 735 rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma); 736 rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma); 737 rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma); 738 rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma); 739 rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma); 740 rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma); 741 /* Set RX Desc Address */ 742 rtl_write_dword(rtlpriv, REG_RX_DESA, 743 rtlpci->rx_ring[RX_MPDU_QUEUE].dma); 744 745 /* if we want to support 64 bit DMA, we should set it here, 746 * but now we do not support 64 bit DMA*/ 747 748 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33); 749 750 /* Reset interrupt migration setting when initialization */ 751 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 752 753 /* Reconsider when to do this operation after asking HWSD. */ 754 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 755 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); 756 do { 757 retry++; 758 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 759 } while ((retry < 200) && !(bytetmp & BIT(7))); 760 761 /* After MACIO reset,we must refresh LED state. */ 762 _rtl92de_gen_refresh_led_state(hw); 763 764 /* Reset H2C protection register */ 765 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 766 767 return true; 768} 769 770static void _rtl92de_hw_configure(struct ieee80211_hw *hw) 771{ 772 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 773 struct rtl_priv *rtlpriv = rtl_priv(hw); 774 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 775 u8 reg_bw_opmode = BW_OPMODE_20MHZ; 776 u32 reg_rrsr; 777 778 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 779 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); 780 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 781 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr); 782 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 783 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); 784 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); 785 rtl_write_word(rtlpriv, REG_RL, 0x0707); 786 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); 787 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 788 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 789 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 790 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 791 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 792 /* Aggregation threshold */ 793 if (rtlhal->macphymode == DUALMAC_DUALPHY) 794 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641); 795 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY) 796 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641); 797 else 798 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); 799 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); 800 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); 801 rtlpci->reg_bcn_ctrl_val = 0x1f; 802 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 803 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 804 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); 805 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 806 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 807 /* For throughput */ 808 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666); 809 /* ACKTO for IOT issue. */ 810 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); 811 /* Set Spec SIFS (used in NAV) */ 812 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); 813 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); 814 /* Set SIFS for CCK */ 815 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); 816 /* Set SIFS for OFDM */ 817 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); 818 /* Set Multicast Address. */ 819 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); 820 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); 821 switch (rtlpriv->phy.rf_type) { 822 case RF_1T2R: 823 case RF_1T1R: 824 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3); 825 break; 826 case RF_2T2R: 827 case RF_2T2R_GREEN: 828 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3); 829 break; 830 } 831} 832 833static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw) 834{ 835 struct rtl_priv *rtlpriv = rtl_priv(hw); 836 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 837 838 rtl_write_byte(rtlpriv, 0x34b, 0x93); 839 rtl_write_word(rtlpriv, 0x350, 0x870c); 840 rtl_write_byte(rtlpriv, 0x352, 0x1); 841 if (ppsc->support_backdoor) 842 rtl_write_byte(rtlpriv, 0x349, 0x1b); 843 else 844 rtl_write_byte(rtlpriv, 0x349, 0x03); 845 rtl_write_word(rtlpriv, 0x350, 0x2718); 846 rtl_write_byte(rtlpriv, 0x352, 0x1); 847} 848 849void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw) 850{ 851 struct rtl_priv *rtlpriv = rtl_priv(hw); 852 u8 sec_reg_value; 853 854 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 855 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 856 rtlpriv->sec.pairwise_enc_algorithm, 857 rtlpriv->sec.group_enc_algorithm); 858 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 859 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 860 "not open hw encryption\n"); 861 return; 862 } 863 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE; 864 if (rtlpriv->sec.use_defaultkey) { 865 sec_reg_value |= SCR_TXUSEDK; 866 sec_reg_value |= SCR_RXUSEDK; 867 } 868 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 869 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 870 rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, 871 "The SECR-value %x\n", sec_reg_value); 872 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 873} 874 875int rtl92de_hw_init(struct ieee80211_hw *hw) 876{ 877 struct rtl_priv *rtlpriv = rtl_priv(hw); 878 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 879 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 880 struct rtl_phy *rtlphy = &(rtlpriv->phy); 881 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 882 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 883 bool rtstatus = true; 884 u8 tmp_u1b; 885 int i; 886 int err; 887 unsigned long flags; 888 889 rtlpci->being_init_adapter = true; 890 rtlpci->init_ready = false; 891 spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags); 892 /* we should do iqk after disable/enable */ 893 rtl92d_phy_reset_iqk_result(hw); 894 /* rtlpriv->intf_ops->disable_aspm(hw); */ 895 rtstatus = _rtl92de_init_mac(hw); 896 if (!rtstatus) { 897 pr_err("Init MAC failed\n"); 898 err = 1; 899 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags); 900 return err; 901 } 902 err = rtl92d_download_fw(hw); 903 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags); 904 if (err) { 905 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 906 "Failed to download FW. Init HW without FW..\n"); 907 return 1; 908 } 909 rtlhal->last_hmeboxnum = 0; 910 rtlpriv->psc.fw_current_inpsmode = false; 911 912 tmp_u1b = rtl_read_byte(rtlpriv, 0x605); 913 tmp_u1b = tmp_u1b | 0x30; 914 rtl_write_byte(rtlpriv, 0x605, tmp_u1b); 915 916 if (rtlhal->earlymode_enable) { 917 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 918 "EarlyMode Enabled!!!\n"); 919 920 tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0); 921 tmp_u1b = tmp_u1b | 0x1f; 922 rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b); 923 924 rtl_write_byte(rtlpriv, 0x4d3, 0x80); 925 926 tmp_u1b = rtl_read_byte(rtlpriv, 0x605); 927 tmp_u1b = tmp_u1b | 0x40; 928 rtl_write_byte(rtlpriv, 0x605, tmp_u1b); 929 } 930 931 if (mac->rdg_en) { 932 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff); 933 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200); 934 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05); 935 } 936 937 rtl92d_phy_mac_config(hw); 938 /* because last function modify RCR, so we update 939 * rcr var here, or TP will unstable for receive_config 940 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 941 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/ 942 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 943 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 944 945 rtl92d_phy_bb_config(hw); 946 947 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 948 /* set before initialize RF */ 949 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); 950 951 /* config RF */ 952 rtl92d_phy_rf_config(hw); 953 954 /* After read predefined TXT, we must set BB/MAC/RF 955 * register as our requirement */ 956 /* After load BB,RF params,we need do more for 92D. */ 957 rtl92d_update_bbrf_configuration(hw); 958 /* set default value after initialize RF, */ 959 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); 960 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 961 RF_CHNLBW, RFREG_OFFSET_MASK); 962 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 963 RF_CHNLBW, RFREG_OFFSET_MASK); 964 965 /*---- Set CCK and OFDM Block "ON"----*/ 966 if (rtlhal->current_bandtype == BAND_ON_2_4G) 967 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 968 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 969 if (rtlhal->interfaceindex == 0) { 970 /* RFPGA0_ANALOGPARAMETER2: cck clock select, 971 * set to 20MHz by default */ 972 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | 973 BIT(11), 3); 974 } else { 975 /* Mac1 */ 976 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) | 977 BIT(10), 3); 978 } 979 980 _rtl92de_hw_configure(hw); 981 982 /* reset hw sec */ 983 rtl_cam_reset_all_entry(hw); 984 rtl92de_enable_hw_security_config(hw); 985 986 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */ 987 /* TX power index for different rate set. */ 988 rtl92d_phy_get_hw_reg_originalvalue(hw); 989 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel); 990 991 ppsc->rfpwr_state = ERFON; 992 993 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 994 995 _rtl92de_enable_aspm_back_door(hw); 996 /* rtlpriv->intf_ops->enable_aspm(hw); */ 997 998 rtl92d_dm_init(hw); 999 rtlpci->being_init_adapter = false; 1000 1001 if (ppsc->rfpwr_state == ERFON) { 1002 rtl92d_phy_lc_calibrate(hw); 1003 /* 5G and 2.4G must wait sometime to let RF LO ready */ 1004 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 1005 u32 tmp_rega; 1006 for (i = 0; i < 10000; i++) { 1007 udelay(MAX_STALL_TIME); 1008 1009 tmp_rega = rtl_get_rfreg(hw, 1010 (enum radio_path)RF90_PATH_A, 1011 0x2a, MASKDWORD); 1012 1013 if (((tmp_rega & BIT(11)) == BIT(11))) 1014 break; 1015 } 1016 /* check that loop was successful. If not, exit now */ 1017 if (i == 10000) { 1018 rtlpci->init_ready = false; 1019 return 1; 1020 } 1021 } 1022 } 1023 rtlpci->init_ready = true; 1024 return err; 1025} 1026 1027static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw) 1028{ 1029 struct rtl_priv *rtlpriv = rtl_priv(hw); 1030 enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY; 1031 u32 value32; 1032 1033 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 1034 if (!(value32 & 0x000f0000)) { 1035 version = VERSION_TEST_CHIP_92D_SINGLEPHY; 1036 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n"); 1037 } else { 1038 version = VERSION_NORMAL_CHIP_92D_SINGLEPHY; 1039 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n"); 1040 } 1041 return version; 1042} 1043 1044static int _rtl92de_set_media_status(struct ieee80211_hw *hw, 1045 enum nl80211_iftype type) 1046{ 1047 struct rtl_priv *rtlpriv = rtl_priv(hw); 1048 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1049 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1050 1051 bt_msr &= 0xfc; 1052 1053 if (type == NL80211_IFTYPE_UNSPECIFIED || 1054 type == NL80211_IFTYPE_STATION) { 1055 _rtl92de_stop_tx_beacon(hw); 1056 _rtl92de_enable_bcn_sub_func(hw); 1057 } else if (type == NL80211_IFTYPE_ADHOC || 1058 type == NL80211_IFTYPE_AP) { 1059 _rtl92de_resume_tx_beacon(hw); 1060 _rtl92de_disable_bcn_sub_func(hw); 1061 } else { 1062 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1063 "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n", 1064 type); 1065 } 1066 switch (type) { 1067 case NL80211_IFTYPE_UNSPECIFIED: 1068 bt_msr |= MSR_NOLINK; 1069 ledaction = LED_CTL_LINK; 1070 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1071 "Set Network type to NO LINK!\n"); 1072 break; 1073 case NL80211_IFTYPE_ADHOC: 1074 bt_msr |= MSR_ADHOC; 1075 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1076 "Set Network type to Ad Hoc!\n"); 1077 break; 1078 case NL80211_IFTYPE_STATION: 1079 bt_msr |= MSR_INFRA; 1080 ledaction = LED_CTL_LINK; 1081 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1082 "Set Network type to STA!\n"); 1083 break; 1084 case NL80211_IFTYPE_AP: 1085 bt_msr |= MSR_AP; 1086 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1087 "Set Network type to AP!\n"); 1088 break; 1089 default: 1090 pr_err("Network type %d not supported!\n", type); 1091 return 1; 1092 } 1093 rtl_write_byte(rtlpriv, MSR, bt_msr); 1094 rtlpriv->cfg->ops->led_control(hw, ledaction); 1095 if ((bt_msr & MSR_MASK) == MSR_AP) 1096 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1097 else 1098 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1099 return 0; 1100} 1101 1102void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1103{ 1104 struct rtl_priv *rtlpriv = rtl_priv(hw); 1105 u32 reg_rcr; 1106 1107 if (rtlpriv->psc.rfpwr_state != ERFON) 1108 return; 1109 1110 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1111 1112 if (check_bssid) { 1113 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1114 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1115 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1116 } else if (!check_bssid) { 1117 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1118 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0); 1119 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1120 } 1121} 1122 1123int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1124{ 1125 struct rtl_priv *rtlpriv = rtl_priv(hw); 1126 1127 if (_rtl92de_set_media_status(hw, type)) 1128 return -EOPNOTSUPP; 1129 1130 /* check bssid */ 1131 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1132 if (type != NL80211_IFTYPE_AP) 1133 rtl92de_set_check_bssid(hw, true); 1134 } else { 1135 rtl92de_set_check_bssid(hw, false); 1136 } 1137 return 0; 1138} 1139 1140/* do iqk or reload iqk */ 1141/* windows just rtl92d_phy_reload_iqk_setting in set channel, 1142 * but it's very strict for time sequence so we add 1143 * rtl92d_phy_reload_iqk_setting here */ 1144void rtl92d_linked_set_reg(struct ieee80211_hw *hw) 1145{ 1146 struct rtl_priv *rtlpriv = rtl_priv(hw); 1147 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1148 u8 indexforchannel; 1149 u8 channel = rtlphy->current_channel; 1150 1151 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel); 1152 if (!rtlphy->iqk_matrix[indexforchannel].iqk_done) { 1153 rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG, 1154 "Do IQK for channel:%d\n", channel); 1155 rtl92d_phy_iq_calibrate(hw); 1156 } 1157} 1158 1159/* don't set REG_EDCA_BE_PARAM here because 1160 * mac80211 will send pkt when scan */ 1161void rtl92de_set_qos(struct ieee80211_hw *hw, int aci) 1162{ 1163 rtl92d_dm_init_edca_turbo(hw); 1164} 1165 1166void rtl92de_enable_interrupt(struct ieee80211_hw *hw) 1167{ 1168 struct rtl_priv *rtlpriv = rtl_priv(hw); 1169 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1170 1171 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 1172 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 1173 rtlpci->irq_enabled = true; 1174} 1175 1176void rtl92de_disable_interrupt(struct ieee80211_hw *hw) 1177{ 1178 struct rtl_priv *rtlpriv = rtl_priv(hw); 1179 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1180 1181 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); 1182 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); 1183 rtlpci->irq_enabled = false; 1184} 1185 1186static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw) 1187{ 1188 struct rtl_priv *rtlpriv = rtl_priv(hw); 1189 u8 u1b_tmp; 1190 unsigned long flags; 1191 1192 rtlpriv->intf_ops->enable_aspm(hw); 1193 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1194 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0); 1195 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0); 1196 1197 /* 0x20:value 05-->04 */ 1198 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); 1199 1200 /* ==== Reset digital sequence ====== */ 1201 rtl92d_firmware_selfreset(hw); 1202 1203 /* f. SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */ 1204 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51); 1205 1206 /* g. MCUFWDL 0x80[1:0]=0 reset MCU ready status */ 1207 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1208 1209 /* ==== Pull GPIO PIN to balance level and LED control ====== */ 1210 1211 /* h. GPIO_PIN_CTRL 0x44[31:0]=0x000 */ 1212 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000); 1213 1214 /* i. Value = GPIO_PIN_CTRL[7:0] */ 1215 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL); 1216 1217 /* j. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */ 1218 /* write external PIN level */ 1219 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 1220 0x00FF0000 | (u1b_tmp << 8)); 1221 1222 /* k. GPIO_MUXCFG 0x42 [15:0] = 0x0780 */ 1223 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790); 1224 1225 /* l. LEDCFG 0x4C[15:0] = 0x8080 */ 1226 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); 1227 1228 /* ==== Disable analog sequence === */ 1229 1230 /* m. AFE_PLL_CTRL[7:0] = 0x80 disable PLL */ 1231 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); 1232 1233 /* n. SPS0_CTRL 0x11[7:0] = 0x22 enter PFM mode */ 1234 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); 1235 1236 /* o. AFE_XTAL_CTRL 0x24[7:0] = 0x0E disable XTAL, if No BT COEX */ 1237 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e); 1238 1239 /* p. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */ 1240 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1241 1242 /* ==== interface into suspend === */ 1243 1244 /* q. APS_FSMCO[15:8] = 0x58 PCIe suspend mode */ 1245 /* According to power document V11, we need to set this */ 1246 /* value as 0x18. Otherwise, we may not L0s sometimes. */ 1247 /* This indluences power consumption. Bases on SD1's test, */ 1248 /* set as 0x00 do not affect power current. And if it */ 1249 /* is set as 0x18, they had ever met auto load fail problem. */ 1250 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10); 1251 1252 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1253 "In PowerOff,reg0x%x=%X\n", 1254 REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL)); 1255 /* r. Note: for PCIe interface, PON will not turn */ 1256 /* off m-bias and BandGap in PCIe suspend mode. */ 1257 1258 /* 0x17[7] 1b': power off in process 0b' : power off over */ 1259 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) { 1260 spin_lock_irqsave(&globalmutex_power, flags); 1261 u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); 1262 u1b_tmp &= (~BIT(7)); 1263 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp); 1264 spin_unlock_irqrestore(&globalmutex_power, flags); 1265 } 1266 1267 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n"); 1268} 1269 1270void rtl92de_card_disable(struct ieee80211_hw *hw) 1271{ 1272 struct rtl_priv *rtlpriv = rtl_priv(hw); 1273 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1274 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1275 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1276 enum nl80211_iftype opmode; 1277 1278 mac->link_state = MAC80211_NOLINK; 1279 opmode = NL80211_IFTYPE_UNSPECIFIED; 1280 _rtl92de_set_media_status(hw, opmode); 1281 1282 if (rtlpci->driver_is_goingto_unload || 1283 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1284 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1285 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1286 /* Power sequence for each MAC. */ 1287 /* a. stop tx DMA */ 1288 /* b. close RF */ 1289 /* c. clear rx buf */ 1290 /* d. stop rx DMA */ 1291 /* e. reset MAC */ 1292 1293 /* a. stop tx DMA */ 1294 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); 1295 udelay(50); 1296 1297 /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ 1298 1299 /* c. ========RF OFF sequence========== */ 1300 /* 0x88c[23:20] = 0xf. */ 1301 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); 1302 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 1303 1304 /* APSD_CTRL 0x600[7:0] = 0x40 */ 1305 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 1306 1307 /* Close antenna 0,0xc04,0xd04 */ 1308 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0); 1309 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0); 1310 1311 /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */ 1312 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 1313 1314 /* Mac0 can not do Global reset. Mac1 can do. */ 1315 /* SYS_FUNC_EN 0x02[7:0] = 0xE0 reset BB state machine */ 1316 if (rtlpriv->rtlhal.interfaceindex == 1) 1317 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0); 1318 udelay(50); 1319 1320 /* d. stop tx/rx dma before disable REG_CR (0x100) to fix */ 1321 /* dma hang issue when disable/enable device. */ 1322 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff); 1323 udelay(50); 1324 rtl_write_byte(rtlpriv, REG_CR, 0x0); 1325 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n"); 1326 if (rtl92d_phy_check_poweroff(hw)) 1327 _rtl92de_poweroff_adapter(hw); 1328 return; 1329} 1330 1331void rtl92de_interrupt_recognized(struct ieee80211_hw *hw, 1332 struct rtl_int *intvec) 1333{ 1334 struct rtl_priv *rtlpriv = rtl_priv(hw); 1335 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1336 1337 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 1338 rtl_write_dword(rtlpriv, ISR, intvec->inta); 1339} 1340 1341void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw) 1342{ 1343 struct rtl_priv *rtlpriv = rtl_priv(hw); 1344 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1345 u16 bcn_interval, atim_window; 1346 1347 bcn_interval = mac->beacon_interval; 1348 atim_window = 2; 1349 rtl92de_disable_interrupt(hw); 1350 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1351 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1352 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 1353 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20); 1354 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) 1355 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30); 1356 else 1357 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20); 1358 rtl_write_byte(rtlpriv, 0x606, 0x30); 1359} 1360 1361void rtl92de_set_beacon_interval(struct ieee80211_hw *hw) 1362{ 1363 struct rtl_priv *rtlpriv = rtl_priv(hw); 1364 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1365 u16 bcn_interval = mac->beacon_interval; 1366 1367 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG, 1368 "beacon_interval:%d\n", bcn_interval); 1369 rtl92de_disable_interrupt(hw); 1370 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1371 rtl92de_enable_interrupt(hw); 1372} 1373 1374void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw, 1375 u32 add_msr, u32 rm_msr) 1376{ 1377 struct rtl_priv *rtlpriv = rtl_priv(hw); 1378 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1379 1380 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n", 1381 add_msr, rm_msr); 1382 if (add_msr) 1383 rtlpci->irq_mask[0] |= add_msr; 1384 if (rm_msr) 1385 rtlpci->irq_mask[0] &= (~rm_msr); 1386 rtl92de_disable_interrupt(hw); 1387 rtl92de_enable_interrupt(hw); 1388} 1389 1390static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo, 1391 u8 *rom_content, bool autoloadfail) 1392{ 1393 u32 rfpath, eeaddr, group, offset1, offset2; 1394 u8 i; 1395 1396 memset(pwrinfo, 0, sizeof(struct txpower_info)); 1397 if (autoloadfail) { 1398 for (group = 0; group < CHANNEL_GROUP_MAX; group++) { 1399 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { 1400 if (group < CHANNEL_GROUP_MAX_2G) { 1401 pwrinfo->cck_index[rfpath][group] = 1402 EEPROM_DEFAULT_TXPOWERLEVEL_2G; 1403 pwrinfo->ht40_1sindex[rfpath][group] = 1404 EEPROM_DEFAULT_TXPOWERLEVEL_2G; 1405 } else { 1406 pwrinfo->ht40_1sindex[rfpath][group] = 1407 EEPROM_DEFAULT_TXPOWERLEVEL_5G; 1408 } 1409 pwrinfo->ht40_2sindexdiff[rfpath][group] = 1410 EEPROM_DEFAULT_HT40_2SDIFF; 1411 pwrinfo->ht20indexdiff[rfpath][group] = 1412 EEPROM_DEFAULT_HT20_DIFF; 1413 pwrinfo->ofdmindexdiff[rfpath][group] = 1414 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 1415 pwrinfo->ht40maxoffset[rfpath][group] = 1416 EEPROM_DEFAULT_HT40_PWRMAXOFFSET; 1417 pwrinfo->ht20maxoffset[rfpath][group] = 1418 EEPROM_DEFAULT_HT20_PWRMAXOFFSET; 1419 } 1420 } 1421 for (i = 0; i < 3; i++) { 1422 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; 1423 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI; 1424 } 1425 return; 1426 } 1427 1428 /* Maybe autoload OK,buf the tx power index value is not filled. 1429 * If we find it, we set it to default value. */ 1430 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { 1431 for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) { 1432 eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3) 1433 + group; 1434 pwrinfo->cck_index[rfpath][group] = 1435 (rom_content[eeaddr] == 0xFF) ? 1436 (eeaddr > 0x7B ? 1437 EEPROM_DEFAULT_TXPOWERLEVEL_5G : 1438 EEPROM_DEFAULT_TXPOWERLEVEL_2G) : 1439 rom_content[eeaddr]; 1440 } 1441 } 1442 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { 1443 for (group = 0; group < CHANNEL_GROUP_MAX; group++) { 1444 offset1 = group / 3; 1445 offset2 = group % 3; 1446 eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) + 1447 offset2 + offset1 * 21; 1448 pwrinfo->ht40_1sindex[rfpath][group] = 1449 (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ? 1450 EEPROM_DEFAULT_TXPOWERLEVEL_5G : 1451 EEPROM_DEFAULT_TXPOWERLEVEL_2G) : 1452 rom_content[eeaddr]; 1453 } 1454 } 1455 /* These just for 92D efuse offset. */ 1456 for (group = 0; group < CHANNEL_GROUP_MAX; group++) { 1457 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { 1458 int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G; 1459 1460 offset1 = group / 3; 1461 offset2 = group % 3; 1462 1463 if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF) 1464 pwrinfo->ht40_2sindexdiff[rfpath][group] = 1465 (rom_content[base1 + 1466 offset2 + offset1 * 21] >> (rfpath * 4)) 1467 & 0xF; 1468 else 1469 pwrinfo->ht40_2sindexdiff[rfpath][group] = 1470 EEPROM_DEFAULT_HT40_2SDIFF; 1471 if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2 1472 + offset1 * 21] != 0xFF) 1473 pwrinfo->ht20indexdiff[rfpath][group] = 1474 (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G 1475 + offset2 + offset1 * 21] >> (rfpath * 4)) 1476 & 0xF; 1477 else 1478 pwrinfo->ht20indexdiff[rfpath][group] = 1479 EEPROM_DEFAULT_HT20_DIFF; 1480 if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2 1481 + offset1 * 21] != 0xFF) 1482 pwrinfo->ofdmindexdiff[rfpath][group] = 1483 (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G 1484 + offset2 + offset1 * 21] >> (rfpath * 4)) 1485 & 0xF; 1486 else 1487 pwrinfo->ofdmindexdiff[rfpath][group] = 1488 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 1489 if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2 1490 + offset1 * 21] != 0xFF) 1491 pwrinfo->ht40maxoffset[rfpath][group] = 1492 (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G 1493 + offset2 + offset1 * 21] >> (rfpath * 4)) 1494 & 0xF; 1495 else 1496 pwrinfo->ht40maxoffset[rfpath][group] = 1497 EEPROM_DEFAULT_HT40_PWRMAXOFFSET; 1498 if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2 1499 + offset1 * 21] != 0xFF) 1500 pwrinfo->ht20maxoffset[rfpath][group] = 1501 (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + 1502 offset2 + offset1 * 21] >> (rfpath * 4)) & 1503 0xF; 1504 else 1505 pwrinfo->ht20maxoffset[rfpath][group] = 1506 EEPROM_DEFAULT_HT20_PWRMAXOFFSET; 1507 } 1508 } 1509 if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) { 1510 /* 5GL */ 1511 pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F; 1512 pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F; 1513 /* 5GM */ 1514 pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F; 1515 pwrinfo->tssi_b[1] = 1516 (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 | 1517 (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2; 1518 /* 5GH */ 1519 pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] & 1520 0xF0) >> 4 | 1521 (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4; 1522 pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] & 1523 0xFC) >> 2; 1524 } else { 1525 for (i = 0; i < 3; i++) { 1526 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; 1527 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI; 1528 } 1529 } 1530} 1531 1532static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw, 1533 bool autoload_fail, u8 *hwinfo) 1534{ 1535 struct rtl_priv *rtlpriv = rtl_priv(hw); 1536 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1537 struct txpower_info pwrinfo; 1538 u8 tempval[2], i, pwr, diff; 1539 u32 ch, rfpath, group; 1540 1541 _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail); 1542 if (!autoload_fail) { 1543 /* bit0~2 */ 1544 rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7); 1545 rtlefuse->eeprom_thermalmeter = 1546 hwinfo[EEPROM_THERMAL_METER] & 0x1f; 1547 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K]; 1548 tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03; 1549 tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2; 1550 rtlefuse->txpwr_fromeprom = true; 1551 if (IS_92D_D_CUT(rtlpriv->rtlhal.version) || 1552 IS_92D_E_CUT(rtlpriv->rtlhal.version)) { 1553 rtlefuse->internal_pa_5g[0] = 1554 !((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6); 1555 rtlefuse->internal_pa_5g[1] = 1556 !((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6); 1557 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1558 "Is D cut,Internal PA0 %d Internal PA1 %d\n", 1559 rtlefuse->internal_pa_5g[0], 1560 rtlefuse->internal_pa_5g[1]); 1561 } 1562 rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6]; 1563 rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7]; 1564 } else { 1565 rtlefuse->eeprom_regulatory = 0; 1566 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; 1567 rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP; 1568 tempval[0] = tempval[1] = 3; 1569 } 1570 1571 /* Use default value to fill parameters if 1572 * efuse is not filled on some place. */ 1573 1574 /* ThermalMeter from EEPROM */ 1575 if (rtlefuse->eeprom_thermalmeter < 0x06 || 1576 rtlefuse->eeprom_thermalmeter > 0x1c) 1577 rtlefuse->eeprom_thermalmeter = 0x12; 1578 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 1579 1580 /* check XTAL_K */ 1581 if (rtlefuse->crystalcap == 0xFF) 1582 rtlefuse->crystalcap = 0; 1583 if (rtlefuse->eeprom_regulatory > 3) 1584 rtlefuse->eeprom_regulatory = 0; 1585 1586 for (i = 0; i < 2; i++) { 1587 switch (tempval[i]) { 1588 case 0: 1589 tempval[i] = 5; 1590 break; 1591 case 1: 1592 tempval[i] = 4; 1593 break; 1594 case 2: 1595 tempval[i] = 3; 1596 break; 1597 case 3: 1598 default: 1599 tempval[i] = 0; 1600 break; 1601 } 1602 } 1603 1604 rtlefuse->delta_iqk = tempval[0]; 1605 if (tempval[1] > 0) 1606 rtlefuse->delta_lck = tempval[1] - 1; 1607 if (rtlefuse->eeprom_c9 == 0xFF) 1608 rtlefuse->eeprom_c9 = 0x00; 1609 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, 1610 "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 1611 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, 1612 "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1613 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, 1614 "CrystalCap = 0x%x\n", rtlefuse->crystalcap); 1615 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, 1616 "Delta_IQK = 0x%x Delta_LCK = 0x%x\n", 1617 rtlefuse->delta_iqk, rtlefuse->delta_lck); 1618 1619 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { 1620 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) { 1621 group = rtl92d_get_chnlgroup_fromarray((u8) ch); 1622 if (ch < CHANNEL_MAX_NUMBER_2G) 1623 rtlefuse->txpwrlevel_cck[rfpath][ch] = 1624 pwrinfo.cck_index[rfpath][group]; 1625 rtlefuse->txpwrlevel_ht40_1s[rfpath][ch] = 1626 pwrinfo.ht40_1sindex[rfpath][group]; 1627 rtlefuse->txpwr_ht20diff[rfpath][ch] = 1628 pwrinfo.ht20indexdiff[rfpath][group]; 1629 rtlefuse->txpwr_legacyhtdiff[rfpath][ch] = 1630 pwrinfo.ofdmindexdiff[rfpath][group]; 1631 rtlefuse->pwrgroup_ht20[rfpath][ch] = 1632 pwrinfo.ht20maxoffset[rfpath][group]; 1633 rtlefuse->pwrgroup_ht40[rfpath][ch] = 1634 pwrinfo.ht40maxoffset[rfpath][group]; 1635 pwr = pwrinfo.ht40_1sindex[rfpath][group]; 1636 diff = pwrinfo.ht40_2sindexdiff[rfpath][group]; 1637 rtlefuse->txpwrlevel_ht40_2s[rfpath][ch] = 1638 (pwr > diff) ? (pwr - diff) : 0; 1639 } 1640 } 1641} 1642 1643static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw, 1644 u8 *content) 1645{ 1646 struct rtl_priv *rtlpriv = rtl_priv(hw); 1647 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1648 u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION]; 1649 1650 if (macphy_crvalue & BIT(3)) { 1651 rtlhal->macphymode = SINGLEMAC_SINGLEPHY; 1652 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1653 "MacPhyMode SINGLEMAC_SINGLEPHY\n"); 1654 } else { 1655 rtlhal->macphymode = DUALMAC_DUALPHY; 1656 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1657 "MacPhyMode DUALMAC_DUALPHY\n"); 1658 } 1659} 1660 1661static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw, 1662 u8 *content) 1663{ 1664 _rtl92de_read_macphymode_from_prom(hw, content); 1665 rtl92d_phy_config_macphymode(hw); 1666 rtl92d_phy_config_macphymode_info(hw); 1667} 1668 1669static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) 1670{ 1671 struct rtl_priv *rtlpriv = rtl_priv(hw); 1672 enum version_8192d chipver = rtlpriv->rtlhal.version; 1673 u8 cutvalue[2]; 1674 u16 chipvalue; 1675 1676 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H, 1677 &cutvalue[1]); 1678 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L, 1679 &cutvalue[0]); 1680 chipvalue = (cutvalue[1] << 8) | cutvalue[0]; 1681 switch (chipvalue) { 1682 case 0xAA55: 1683 chipver |= CHIP_92D_C_CUT; 1684 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n"); 1685 break; 1686 case 0x9966: 1687 chipver |= CHIP_92D_D_CUT; 1688 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n"); 1689 break; 1690 case 0xCC33: 1691 chipver |= CHIP_92D_E_CUT; 1692 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n"); 1693 break; 1694 default: 1695 chipver |= CHIP_92D_D_CUT; 1696 pr_err("Unknown CUT!\n"); 1697 break; 1698 } 1699 rtlpriv->rtlhal.version = chipver; 1700} 1701 1702static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) 1703{ 1704 struct rtl_priv *rtlpriv = rtl_priv(hw); 1705 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1706 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1707 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, 1708 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D, 1709 EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 1710 COUNTRY_CODE_WORLD_WIDE_13}; 1711 int i; 1712 u16 usvalue; 1713 u8 *hwinfo; 1714 1715 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 1716 if (!hwinfo) 1717 return; 1718 1719 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 1720 goto exit; 1721 1722 _rtl92de_efuse_update_chip_version(hw); 1723 _rtl92de_read_macphymode_and_bandtype(hw, hwinfo); 1724 1725 /* Read Permanent MAC address for 2nd interface */ 1726 if (rtlhal->interfaceindex != 0) { 1727 for (i = 0; i < 6; i += 2) { 1728 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i]; 1729 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; 1730 } 1731 } 1732 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, 1733 rtlefuse->dev_addr); 1734 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); 1735 _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo); 1736 1737 /* Read Channel Plan */ 1738 switch (rtlhal->bandset) { 1739 case BAND_ON_2_4G: 1740 rtlefuse->channel_plan = COUNTRY_CODE_TELEC; 1741 break; 1742 case BAND_ON_5G: 1743 rtlefuse->channel_plan = COUNTRY_CODE_FCC; 1744 break; 1745 case BAND_ON_BOTH: 1746 rtlefuse->channel_plan = COUNTRY_CODE_FCC; 1747 break; 1748 default: 1749 rtlefuse->channel_plan = COUNTRY_CODE_FCC; 1750 break; 1751 } 1752 rtlefuse->txpwr_fromeprom = true; 1753exit: 1754 kfree(hwinfo); 1755} 1756 1757void rtl92de_read_eeprom_info(struct ieee80211_hw *hw) 1758{ 1759 struct rtl_priv *rtlpriv = rtl_priv(hw); 1760 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1761 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1762 u8 tmp_u1b; 1763 1764 rtlhal->version = _rtl92de_read_chip_version(hw); 1765 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 1766 rtlefuse->autoload_status = tmp_u1b; 1767 if (tmp_u1b & BIT(4)) { 1768 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 1769 rtlefuse->epromtype = EEPROM_93C46; 1770 } else { 1771 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 1772 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 1773 } 1774 if (tmp_u1b & BIT(5)) { 1775 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1776 1777 rtlefuse->autoload_failflag = false; 1778 _rtl92de_read_adapter_info(hw); 1779 } else { 1780 pr_err("Autoload ERR!!\n"); 1781 } 1782 return; 1783} 1784 1785static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw, 1786 struct ieee80211_sta *sta) 1787{ 1788 struct rtl_priv *rtlpriv = rtl_priv(hw); 1789 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1790 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1791 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1792 u32 ratr_value; 1793 u8 ratr_index = 0; 1794 u8 nmode = mac->ht_enable; 1795 u8 mimo_ps = IEEE80211_SMPS_OFF; 1796 u16 shortgi_rate; 1797 u32 tmp_ratr_value; 1798 u8 curtxbw_40mhz = mac->bw_40; 1799 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1800 1 : 0; 1801 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1802 1 : 0; 1803 enum wireless_mode wirelessmode = mac->mode; 1804 1805 if (rtlhal->current_bandtype == BAND_ON_5G) 1806 ratr_value = sta->deflink.supp_rates[1] << 4; 1807 else 1808 ratr_value = sta->deflink.supp_rates[0]; 1809 ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | 1810 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 1811 switch (wirelessmode) { 1812 case WIRELESS_MODE_A: 1813 ratr_value &= 0x00000FF0; 1814 break; 1815 case WIRELESS_MODE_B: 1816 if (ratr_value & 0x0000000c) 1817 ratr_value &= 0x0000000d; 1818 else 1819 ratr_value &= 0x0000000f; 1820 break; 1821 case WIRELESS_MODE_G: 1822 ratr_value &= 0x00000FF5; 1823 break; 1824 case WIRELESS_MODE_N_24G: 1825 case WIRELESS_MODE_N_5G: 1826 nmode = 1; 1827 if (mimo_ps == IEEE80211_SMPS_STATIC) { 1828 ratr_value &= 0x0007F005; 1829 } else { 1830 u32 ratr_mask; 1831 1832 if (get_rf_type(rtlphy) == RF_1T2R || 1833 get_rf_type(rtlphy) == RF_1T1R) { 1834 ratr_mask = 0x000ff005; 1835 } else { 1836 ratr_mask = 0x0f0ff005; 1837 } 1838 1839 ratr_value &= ratr_mask; 1840 } 1841 break; 1842 default: 1843 if (rtlphy->rf_type == RF_1T2R) 1844 ratr_value &= 0x000ff0ff; 1845 else 1846 ratr_value &= 0x0f0ff0ff; 1847 1848 break; 1849 } 1850 ratr_value &= 0x0FFFFFFF; 1851 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) || 1852 (!curtxbw_40mhz && curshortgi_20mhz))) { 1853 ratr_value |= 0x10000000; 1854 tmp_ratr_value = (ratr_value >> 12); 1855 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 1856 if ((1 << shortgi_rate) & tmp_ratr_value) 1857 break; 1858 } 1859 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 1860 (shortgi_rate << 4) | (shortgi_rate); 1861 } 1862 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 1863 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 1864 rtl_read_dword(rtlpriv, REG_ARFR0)); 1865} 1866 1867static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, 1868 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 1869{ 1870 struct rtl_priv *rtlpriv = rtl_priv(hw); 1871 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1872 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1873 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1874 struct rtl_sta_info *sta_entry = NULL; 1875 u32 ratr_bitmap; 1876 u8 ratr_index; 1877 u8 curtxbw_40mhz = (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; 1878 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1879 1 : 0; 1880 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1881 1 : 0; 1882 enum wireless_mode wirelessmode = 0; 1883 bool shortgi = false; 1884 u32 value[2]; 1885 u8 macid = 0; 1886 u8 mimo_ps = IEEE80211_SMPS_OFF; 1887 1888 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 1889 mimo_ps = sta_entry->mimo_ps; 1890 wirelessmode = sta_entry->wireless_mode; 1891 if (mac->opmode == NL80211_IFTYPE_STATION) 1892 curtxbw_40mhz = mac->bw_40; 1893 else if (mac->opmode == NL80211_IFTYPE_AP || 1894 mac->opmode == NL80211_IFTYPE_ADHOC) 1895 macid = sta->aid + 1; 1896 1897 if (rtlhal->current_bandtype == BAND_ON_5G) 1898 ratr_bitmap = sta->deflink.supp_rates[1] << 4; 1899 else 1900 ratr_bitmap = sta->deflink.supp_rates[0]; 1901 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | 1902 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 1903 switch (wirelessmode) { 1904 case WIRELESS_MODE_B: 1905 ratr_index = RATR_INX_WIRELESS_B; 1906 if (ratr_bitmap & 0x0000000c) 1907 ratr_bitmap &= 0x0000000d; 1908 else 1909 ratr_bitmap &= 0x0000000f; 1910 break; 1911 case WIRELESS_MODE_G: 1912 ratr_index = RATR_INX_WIRELESS_GB; 1913 1914 if (rssi_level == 1) 1915 ratr_bitmap &= 0x00000f00; 1916 else if (rssi_level == 2) 1917 ratr_bitmap &= 0x00000ff0; 1918 else 1919 ratr_bitmap &= 0x00000ff5; 1920 break; 1921 case WIRELESS_MODE_A: 1922 ratr_index = RATR_INX_WIRELESS_G; 1923 ratr_bitmap &= 0x00000ff0; 1924 break; 1925 case WIRELESS_MODE_N_24G: 1926 case WIRELESS_MODE_N_5G: 1927 if (wirelessmode == WIRELESS_MODE_N_24G) 1928 ratr_index = RATR_INX_WIRELESS_NGB; 1929 else 1930 ratr_index = RATR_INX_WIRELESS_NG; 1931 if (mimo_ps == IEEE80211_SMPS_STATIC) { 1932 if (rssi_level == 1) 1933 ratr_bitmap &= 0x00070000; 1934 else if (rssi_level == 2) 1935 ratr_bitmap &= 0x0007f000; 1936 else 1937 ratr_bitmap &= 0x0007f005; 1938 } else { 1939 if (rtlphy->rf_type == RF_1T2R || 1940 rtlphy->rf_type == RF_1T1R) { 1941 if (curtxbw_40mhz) { 1942 if (rssi_level == 1) 1943 ratr_bitmap &= 0x000f0000; 1944 else if (rssi_level == 2) 1945 ratr_bitmap &= 0x000ff000; 1946 else 1947 ratr_bitmap &= 0x000ff015; 1948 } else { 1949 if (rssi_level == 1) 1950 ratr_bitmap &= 0x000f0000; 1951 else if (rssi_level == 2) 1952 ratr_bitmap &= 0x000ff000; 1953 else 1954 ratr_bitmap &= 0x000ff005; 1955 } 1956 } else { 1957 if (curtxbw_40mhz) { 1958 if (rssi_level == 1) 1959 ratr_bitmap &= 0x0f0f0000; 1960 else if (rssi_level == 2) 1961 ratr_bitmap &= 0x0f0ff000; 1962 else 1963 ratr_bitmap &= 0x0f0ff015; 1964 } else { 1965 if (rssi_level == 1) 1966 ratr_bitmap &= 0x0f0f0000; 1967 else if (rssi_level == 2) 1968 ratr_bitmap &= 0x0f0ff000; 1969 else 1970 ratr_bitmap &= 0x0f0ff005; 1971 } 1972 } 1973 } 1974 if ((curtxbw_40mhz && curshortgi_40mhz) || 1975 (!curtxbw_40mhz && curshortgi_20mhz)) { 1976 1977 if (macid == 0) 1978 shortgi = true; 1979 else if (macid == 1) 1980 shortgi = false; 1981 } 1982 break; 1983 default: 1984 ratr_index = RATR_INX_WIRELESS_NGB; 1985 1986 if (rtlphy->rf_type == RF_1T2R) 1987 ratr_bitmap &= 0x000ff0ff; 1988 else 1989 ratr_bitmap &= 0x0f0ff0ff; 1990 break; 1991 } 1992 1993 value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28); 1994 value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 1995 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, 1996 "ratr_bitmap :%x value0:%x value1:%x\n", 1997 ratr_bitmap, value[0], value[1]); 1998 rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value); 1999 if (macid != 0) 2000 sta_entry->ratr_index = ratr_index; 2001} 2002 2003void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw, 2004 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 2005{ 2006 struct rtl_priv *rtlpriv = rtl_priv(hw); 2007 2008 if (rtlpriv->dm.useramask) 2009 rtl92de_update_hal_rate_mask(hw, sta, rssi_level, update_bw); 2010 else 2011 rtl92de_update_hal_rate_table(hw, sta); 2012} 2013 2014void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw) 2015{ 2016 struct rtl_priv *rtlpriv = rtl_priv(hw); 2017 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2018 u16 sifs_timer; 2019 2020 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2021 &mac->slot_time); 2022 if (!mac->ht_enable) 2023 sifs_timer = 0x0a0a; 2024 else 2025 sifs_timer = 0x1010; 2026 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2027} 2028 2029bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2030{ 2031 struct rtl_priv *rtlpriv = rtl_priv(hw); 2032 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2033 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2034 enum rf_pwrstate e_rfpowerstate_toset; 2035 u8 u1tmp; 2036 bool actuallyset = false; 2037 unsigned long flag; 2038 2039 if (rtlpci->being_init_adapter) 2040 return false; 2041 if (ppsc->swrf_processing) 2042 return false; 2043 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2044 if (ppsc->rfchange_inprogress) { 2045 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2046 return false; 2047 } else { 2048 ppsc->rfchange_inprogress = true; 2049 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2050 } 2051 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv, 2052 REG_MAC_PINMUX_CFG) & ~(BIT(3))); 2053 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 2054 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; 2055 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) { 2056 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2057 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2058 e_rfpowerstate_toset = ERFON; 2059 ppsc->hwradiooff = false; 2060 actuallyset = true; 2061 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) { 2062 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2063 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 2064 e_rfpowerstate_toset = ERFOFF; 2065 ppsc->hwradiooff = true; 2066 actuallyset = true; 2067 } 2068 if (actuallyset) { 2069 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2070 ppsc->rfchange_inprogress = false; 2071 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2072 } else { 2073 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 2074 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2075 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2076 ppsc->rfchange_inprogress = false; 2077 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2078 } 2079 *valid = 1; 2080 return !ppsc->hwradiooff; 2081} 2082 2083void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, 2084 u8 *p_macaddr, bool is_group, u8 enc_algo, 2085 bool is_wepkey, bool clear_all) 2086{ 2087 struct rtl_priv *rtlpriv = rtl_priv(hw); 2088 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2089 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2090 u8 *macaddr = p_macaddr; 2091 u32 entry_id; 2092 bool is_pairwise = false; 2093 static u8 cam_const_addr[4][6] = { 2094 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2095 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2096 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2097 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2098 }; 2099 static u8 cam_const_broad[] = { 2100 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2101 }; 2102 2103 if (clear_all) { 2104 u8 idx; 2105 u8 cam_offset = 0; 2106 u8 clear_number = 5; 2107 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2108 for (idx = 0; idx < clear_number; idx++) { 2109 rtl_cam_mark_invalid(hw, cam_offset + idx); 2110 rtl_cam_empty_entry(hw, cam_offset + idx); 2111 2112 if (idx < 5) { 2113 memset(rtlpriv->sec.key_buf[idx], 0, 2114 MAX_KEY_LEN); 2115 rtlpriv->sec.key_len[idx] = 0; 2116 } 2117 } 2118 } else { 2119 switch (enc_algo) { 2120 case WEP40_ENCRYPTION: 2121 enc_algo = CAM_WEP40; 2122 break; 2123 case WEP104_ENCRYPTION: 2124 enc_algo = CAM_WEP104; 2125 break; 2126 case TKIP_ENCRYPTION: 2127 enc_algo = CAM_TKIP; 2128 break; 2129 case AESCCMP_ENCRYPTION: 2130 enc_algo = CAM_AES; 2131 break; 2132 default: 2133 pr_err("switch case %#x not processed\n", 2134 enc_algo); 2135 enc_algo = CAM_TKIP; 2136 break; 2137 } 2138 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2139 macaddr = cam_const_addr[key_index]; 2140 entry_id = key_index; 2141 } else { 2142 if (is_group) { 2143 macaddr = cam_const_broad; 2144 entry_id = key_index; 2145 } else { 2146 if (mac->opmode == NL80211_IFTYPE_AP) { 2147 entry_id = rtl_cam_get_free_entry(hw, 2148 p_macaddr); 2149 if (entry_id >= TOTAL_CAM_ENTRY) { 2150 pr_err("Can not find free hw security cam entry\n"); 2151 return; 2152 } 2153 } else { 2154 entry_id = CAM_PAIRWISE_KEY_POSITION; 2155 } 2156 key_index = PAIRWISE_KEYIDX; 2157 is_pairwise = true; 2158 } 2159 } 2160 if (rtlpriv->sec.key_len[key_index] == 0) { 2161 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2162 "delete one entry, entry_id is %d\n", 2163 entry_id); 2164 if (mac->opmode == NL80211_IFTYPE_AP) 2165 rtl_cam_del_entry(hw, p_macaddr); 2166 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2167 } else { 2168 rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, 2169 "The insert KEY length is %d\n", 2170 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); 2171 rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, 2172 "The insert KEY is %x %x\n", 2173 rtlpriv->sec.key_buf[0][0], 2174 rtlpriv->sec.key_buf[0][1]); 2175 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2176 "add one entry\n"); 2177 if (is_pairwise) { 2178 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, 2179 "Pairwise Key content", 2180 rtlpriv->sec.pairwise_key, 2181 rtlpriv-> 2182 sec.key_len[PAIRWISE_KEYIDX]); 2183 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2184 "set Pairwise key\n"); 2185 rtl_cam_add_one_entry(hw, macaddr, key_index, 2186 entry_id, enc_algo, 2187 CAM_CONFIG_NO_USEDK, 2188 rtlpriv-> 2189 sec.key_buf[key_index]); 2190 } else { 2191 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, 2192 "set group key\n"); 2193 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2194 rtl_cam_add_one_entry(hw, 2195 rtlefuse->dev_addr, 2196 PAIRWISE_KEYIDX, 2197 CAM_PAIRWISE_KEY_POSITION, 2198 enc_algo, CAM_CONFIG_NO_USEDK, 2199 rtlpriv->sec.key_buf[entry_id]); 2200 } 2201 rtl_cam_add_one_entry(hw, macaddr, key_index, 2202 entry_id, enc_algo, 2203 CAM_CONFIG_NO_USEDK, 2204 rtlpriv->sec.key_buf 2205 [entry_id]); 2206 } 2207 } 2208 } 2209} 2210 2211void rtl92de_suspend(struct ieee80211_hw *hw) 2212{ 2213 struct rtl_priv *rtlpriv = rtl_priv(hw); 2214 2215 rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv, 2216 REG_MAC_PHY_CTRL_NORMAL); 2217} 2218 2219void rtl92de_resume(struct ieee80211_hw *hw) 2220{ 2221 struct rtl_priv *rtlpriv = rtl_priv(hw); 2222 2223 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL, 2224 rtlpriv->rtlhal.macphyctl_reg); 2225} 2226