1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2009-2013  Realtek Corporation.*/
3
4#ifndef __RTL8723E_PWRSEQ_H__
5#define __RTL8723E_PWRSEQ_H__
6
7#include "../pwrseqcmd.h"
8/* Check document WM-20110607-Paul-RTL8188EE_Power_Architecture-R02.vsd
9 *	There are 6 HW Power States:
10 *	0: POFF--Power Off
11 *	1: PDN--Power Down
12 *	2: CARDEMU--Card Emulation
13 *	3: ACT--Active Mode
14 *	4: LPS--Low Power State
15 *	5: SUS--Suspend
16 *
17 *	The transision from different states are defined below
18 *	TRANS_CARDEMU_TO_ACT
19 *	TRANS_ACT_TO_CARDEMU
20 *	TRANS_CARDEMU_TO_SUS
21 *	TRANS_SUS_TO_CARDEMU
22 *	TRANS_CARDEMU_TO_PDN
23 *	TRANS_ACT_TO_LPS
24 *	TRANS_LPS_TO_ACT
25 *
26 *	TRANS_END
27 *	PWR SEQ Version: rtl8188ee_PwrSeq_V09.h
28 */
29
30#define	RTL8188EE_TRANS_CARDEMU_TO_ACT_STEPS	10
31#define	RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS	10
32#define	RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS	10
33#define	RTL8188EE_TRANS_SUS_TO_CARDEMU_STEPS	10
34#define	RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS	10
35#define	RTL8188EE_TRANS_PDN_TO_CARDEMU_STEPS	10
36#define	RTL8188EE_TRANS_ACT_TO_LPS_STEPS		15
37#define	RTL8188EE_TRANS_LPS_TO_ACT_STEPS		15
38#define	RTL8188EE_TRANS_END_STEPS		1
39
40/* The following macros have the following format:
41 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value
42 *   comments },
43 */
44#define RTL8188EE_TRANS_CARDEMU_TO_ACT					\
45	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
46	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)		\
47	/* wait till 0x04[17] = 1    power ready*/},			\
48	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
49	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0		\
50	/* 0x02[1:0] = 0	reset BB*/},				\
51	{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
52	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)			\
53	/*0x24[23] = 2b'01 schmit trigger */},				\
54	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
55	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0			\
56	/* 0x04[15] = 0 disable HWPDN (control by DRV)*/},		\
57	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
58	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0		\
59	/*0x04[12:11] = 2b'00 disable WL suspend*/},			\
60	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
61	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)			\
62	/*0x04[8] = 1 polling until return 0*/},			\
63	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
64	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0			\
65	/*wait till 0x04[8] = 0*/},					\
66	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
67	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0			\
68	/*LDO normal mode*/},						\
69	{0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
70	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)			\
71	/*SDIO Driving*/},
72
73#define RTL8188EE_TRANS_ACT_TO_CARDEMU					\
74	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
75	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0			\
76	/*0x1F[7:0] = 0 turn off RF*/},					\
77	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
78	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)			\
79	/*LDO Sleep mode*/},						\
80	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
81	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)			\
82	/*0x04[9] = 1 turn off MAC by HW state machine*/},		\
83	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
84	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0			\
85	/*wait till 0x04[9] = 0 polling until return 0 to disable*/},
86
87#define RTL8188EE_TRANS_CARDEMU_TO_SUS					\
88	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
89	PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,				\
90	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)		\
91	/*0x04[12:11] = 2b'01enable WL suspend*/},			\
92	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
93	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)	\
94	/*0x04[12:11] = 2b'11enable WL suspend for PCIe*/},		\
95	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
96	PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,				\
97	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7)			\
98	/*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */},\
99	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
100	PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,				\
101	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0			\
102	/*Clear SIC_EN register 0x40[12] = 1'b0 */},			\
103	{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
104	PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,				\
105	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)			\
106	/*Set USB suspend enable local register  0xfe10[4]=1 */},	\
107	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
108	PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)		\
109	/*Set SDIO suspend local register*/},				\
110	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
111	PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0			\
112	/*wait power state to suspend*/},
113
114#define RTL8188EE_TRANS_SUS_TO_CARDEMU					\
115	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
116	PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0			\
117	/*Set SDIO suspend local register*/},				\
118	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
119	PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)		\
120	/*wait power state to suspend*/},				\
121	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
122	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0		\
123	/*0x04[12:11] = 2b'00 disable WL suspend*/},
124
125#define RTL8188EE_TRANS_CARDEMU_TO_CARDDIS				\
126	{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
127	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)			\
128	/*0x24[23] = 2b'01 schmit trigger */},				\
129	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
130	PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,				\
131	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)	\
132	/*0x04[12:11] = 2b'01 enable WL suspend*/},			\
133	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
134	PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,				\
135	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0			\
136	/*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */},\
137	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
138	PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,				\
139	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0			\
140	/*Clear SIC_EN register 0x40[12] = 1'b0 */},			\
141	{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,	\
142	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)			\
143	/*Set USB suspend enable local register  0xfe10[4]=1 */},	\
144	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
145	PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)		\
146	/*Set SDIO suspend local register*/},				\
147	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
148	PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0			\
149	/*wait power state to suspend*/},
150
151#define RTL8188EE_TRANS_CARDDIS_TO_CARDEMU				\
152	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
153	PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0			\
154	/*Set SDIO suspend local register*/},				\
155	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
156	PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)		\
157	/*wait power state to suspend*/},				\
158	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
159	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0		\
160	/*0x04[12:11] = 2b'00 disable WL suspend*/},
161
162#define RTL8188EE_TRANS_CARDEMU_TO_PDN					\
163	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
164	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0/* 0x04[16] = 0*/},	\
165	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
166	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)			\
167	/* 0x04[15] = 1*/},
168
169#define RTL8188EE_TRANS_PDN_TO_CARDEMU					\
170	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
171	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0/* 0x04[15] = 0*/},
172
173#define RTL8188EE_TRANS_ACT_TO_LPS					\
174	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
175	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F			\
176	/*Tx Pause*/},							\
177	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
178	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0			\
179	/*Should be zero if no packet is transmitting*/},		\
180	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
181	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0			\
182	/*Should be zero if no packet is transmitting*/},		\
183	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
184	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0			\
185	/*Should be zero if no packet is transmitting*/},		\
186	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
187	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0			\
188	/*Should be zero if no packet is transmitting*/},		\
189	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
190	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0			\
191	/*CCK and OFDM are disabled,and clock are gated*/},		\
192	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
193	PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US		\
194	/*Delay 1us*/},							\
195	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
196	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F			\
197	/*Reset MAC TRX*/},						\
198	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
199	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0			\
200	/*check if removed later*/},					\
201	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
202	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)			\
203	/*Respond TxOK to scheduler*/},
204
205
206#define RTL8188EE_TRANS_LPS_TO_ACT					\
207	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
208	PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84			\
209	/*SDIO RPWM*/},							\
210	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,	\
211	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84			\
212	/*USB RPWM*/},							\
213	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
214	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84			\
215	/*PCIe RPWM*/},							\
216	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
217	PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS		\
218	/*Delay*/},							\
219	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
220	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0			\
221	/*.	0x08[4] = 0		 switch TSF to 40M*/},		\
222	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
223	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0			\
224	/*Polling 0x109[7]=0  TSF in 40M*/},				\
225	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
226	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0		\
227	/*.	0x29[7:6] = 2b'00	 enable BB clock*/},		\
228	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
229	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)			\
230	/*.	0x101[1] = 1*/},					\
231	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
232	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF			\
233	/*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/},		\
234	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
235	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)	\
236	/*.	0x02[1:0] = 2b'11	 enable BB macro*/},		\
237	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
238	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0			\
239	/*.	0x522 = 0*/},
240
241#define RTL8188EE_TRANS_END		\
242	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
243	0, PWR_CMD_END, 0, 0}
244
245extern struct wlan_pwr_cfg rtl8188ee_power_on_flow
246		[RTL8188EE_TRANS_CARDEMU_TO_ACT_STEPS +
247		 RTL8188EE_TRANS_END_STEPS];
248extern struct wlan_pwr_cfg rtl8188ee_radio_off_flow
249		[RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
250		 RTL8188EE_TRANS_END_STEPS];
251extern struct wlan_pwr_cfg rtl8188ee_card_disable_flow
252		[RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
253		 RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS +
254		 RTL8188EE_TRANS_END_STEPS];
255extern struct wlan_pwr_cfg rtl8188ee_card_enable_flow
256		[RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
257		 RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS +
258		 RTL8188EE_TRANS_END_STEPS];
259extern struct wlan_pwr_cfg rtl8188ee_suspend_flow
260		[RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
261		 RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS +
262		 RTL8188EE_TRANS_END_STEPS];
263extern struct wlan_pwr_cfg rtl8188ee_resume_flow
264		[RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
265		 RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS +
266		 RTL8188EE_TRANS_END_STEPS];
267extern struct wlan_pwr_cfg rtl8188ee_hwpdn_flow
268		[RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS +
269		 RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS +
270		 RTL8188EE_TRANS_END_STEPS];
271extern struct wlan_pwr_cfg rtl8188ee_enter_lps_flow
272		[RTL8188EE_TRANS_ACT_TO_LPS_STEPS +
273		 RTL8188EE_TRANS_END_STEPS];
274extern struct wlan_pwr_cfg rtl8188ee_leave_lps_flow
275		[RTL8188EE_TRANS_LPS_TO_ACT_STEPS +
276		 RTL8188EE_TRANS_END_STEPS];
277
278/* RTL8723 Power Configuration CMDs for PCIe interface */
279#define RTL8188EE_NIC_PWR_ON_FLOW	rtl8188ee_power_on_flow
280#define RTL8188EE_NIC_RF_OFF_FLOW	rtl8188ee_radio_off_flow
281#define RTL8188EE_NIC_DISABLE_FLOW	rtl8188ee_card_disable_flow
282#define RTL8188EE_NIC_ENABLE_FLOW	rtl8188ee_card_enable_flow
283#define RTL8188EE_NIC_SUSPEND_FLOW	rtl8188ee_suspend_flow
284#define RTL8188EE_NIC_RESUME_FLOW	rtl8188ee_resume_flow
285#define RTL8188EE_NIC_PDN_FLOW		rtl8188ee_hwpdn_flow
286#define RTL8188EE_NIC_LPS_ENTER_FLOW	rtl8188ee_enter_lps_flow
287#define RTL8188EE_NIC_LPS_LEAVE_FLOW	rtl8188ee_leave_lps_flow
288
289#endif
290