1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2009-2013  Realtek Corporation.*/
3
4#ifndef __RTL92C_PHY_H__
5#define __RTL92C_PHY_H__
6
7/* MAX_TX_COUNT must always set to 4, otherwise read efuse
8 * table secquence will be wrong.
9 */
10#define		MAX_TX_COUNT				4
11
12#define MAX_PRECMD_CNT				16
13#define MAX_RFDEPENDCMD_CNT		16
14#define MAX_POSTCMD_CNT				16
15
16#define MAX_DOZE_WAITING_TIMES_9x	64
17
18#define RT_CANNOT_IO(hw)			false
19#define HIGHPOWER_RADIOA_ARRAYLEN	22
20
21#define IQK_ADDA_REG_NUM			16
22#define IQK_BB_REG_NUM				9
23#define MAX_TOLERANCE				5
24#define	IQK_DELAY_TIME				10
25#define	INDEX_MAPPING_NUM	15
26
27#define	APK_BB_REG_NUM				5
28#define	APK_AFE_REG_NUM				16
29#define	APK_CURVE_REG_NUM			4
30#define	PATH_NUM					2
31
32#define LOOP_LIMIT					5
33#define MAX_STALL_TIME				50
34#define ANTENNADIVERSITYVALUE		0x80
35#define MAX_TXPWR_IDX_NMODE_92S		63
36#define RESET_CNT_LIMIT				3
37
38#define IQK_ADDA_REG_NUM			16
39#define IQK_MAC_REG_NUM				4
40
41#define RF6052_MAX_PATH				2
42
43#define CT_OFFSET_MAC_ADDR			0X16
44
45#define CT_OFFSET_CCK_TX_PWR_IDX			0x5A
46#define CT_OFFSET_HT401S_TX_PWR_IDX			0x60
47#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF	0x66
48#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF		0x69
49#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF		0x6C
50
51#define CT_OFFSET_HT40_MAX_PWR_OFFSET		0x6F
52#define CT_OFFSET_HT20_MAX_PWR_OFFSET		0x72
53
54#define CT_OFFSET_CHANNEL_PLAH				0x75
55#define CT_OFFSET_THERMAL_METER				0x78
56#define CT_OFFSET_RF_OPTION					0x79
57#define CT_OFFSET_VERSION					0x7E
58#define CT_OFFSET_CUSTOMER_ID				0x7F
59
60#define RTL92C_MAX_PATH_NUM					2
61
62enum swchnlcmd_id {
63	CMDID_END,
64	CMDID_SET_TXPOWEROWER_LEVEL,
65	CMDID_BBREGWRITE10,
66	CMDID_WRITEPORT_ULONG,
67	CMDID_WRITEPORT_USHORT,
68	CMDID_WRITEPORT_UCHAR,
69	CMDID_RF_WRITEREG,
70};
71
72struct swchnlcmd {
73	enum swchnlcmd_id cmdid;
74	u32 para1;
75	u32 para2;
76	u32 msdelay;
77};
78
79enum hw90_block_e {
80	HW90_BLOCK_MAC = 0,
81	HW90_BLOCK_PHY0 = 1,
82	HW90_BLOCK_PHY1 = 2,
83	HW90_BLOCK_RF = 3,
84	HW90_BLOCK_MAXIMUM = 4,
85};
86
87enum baseband_config_type {
88	BASEBAND_CONFIG_PHY_REG = 0,
89	BASEBAND_CONFIG_AGC_TAB = 1,
90};
91
92enum ra_offset_area {
93	RA_OFFSET_LEGACY_OFDM1,
94	RA_OFFSET_LEGACY_OFDM2,
95	RA_OFFSET_HT_OFDM1,
96	RA_OFFSET_HT_OFDM2,
97	RA_OFFSET_HT_OFDM3,
98	RA_OFFSET_HT_OFDM4,
99	RA_OFFSET_HT_CCK,
100};
101
102enum antenna_path {
103	ANTENNA_NONE,
104	ANTENNA_D,
105	ANTENNA_C,
106	ANTENNA_CD,
107	ANTENNA_B,
108	ANTENNA_BD,
109	ANTENNA_BC,
110	ANTENNA_BCD,
111	ANTENNA_A,
112	ANTENNA_AD,
113	ANTENNA_AC,
114	ANTENNA_ACD,
115	ANTENNA_AB,
116	ANTENNA_ABD,
117	ANTENNA_ABC,
118	ANTENNA_ABCD
119};
120
121struct r_antenna_select_ofdm {
122	u32 r_tx_antenna:4;
123	u32 r_ant_l:4;
124	u32 r_ant_non_ht:4;
125	u32 r_ant_ht1:4;
126	u32 r_ant_ht2:4;
127	u32 r_ant_ht_s1:4;
128	u32 r_ant_non_ht_s1:4;
129	u32 ofdm_txsc:2;
130	u32 reserved:2;
131};
132
133struct r_antenna_select_cck {
134	u8 r_cckrx_enable_2:2;
135	u8 r_cckrx_enable:2;
136	u8 r_ccktx_enable:4;
137};
138
139struct efuse_contents {
140	u8 mac_addr[ETH_ALEN];
141	u8 cck_tx_power_idx[6];
142	u8 ht40_1s_tx_power_idx[6];
143	u8 ht40_2s_tx_power_idx_diff[3];
144	u8 ht20_tx_power_idx_diff[3];
145	u8 ofdm_tx_power_idx_diff[3];
146	u8 ht40_max_power_offset[3];
147	u8 ht20_max_power_offset[3];
148	u8 channel_plan;
149	u8 thermal_meter;
150	u8 rf_option[5];
151	u8 version;
152	u8 oem_id;
153	u8 regulatory;
154};
155
156struct tx_power_struct {
157	u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
158	u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
159	u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
160	u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
161	u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
162	u8 legacy_ht_txpowerdiff;
163	u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
164	u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
165	u8 pwrgroup_cnt;
166	u32 mcs_original_offset[4][16];
167};
168
169enum _ANT_DIV_TYPE {
170	NO_ANTDIV				= 0xFF,
171	CG_TRX_HW_ANTDIV		= 0x01,
172	CGCS_RX_HW_ANTDIV		= 0x02,
173	FIXED_HW_ANTDIV         = 0x03,
174	CG_TRX_SMART_ANTDIV		= 0x04,
175	CGCS_RX_SW_ANTDIV		= 0x05,
176};
177
178u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw,
179			    u32 regaddr, u32 bitmask);
180void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw,
181			   u32 regaddr, u32 bitmask, u32 data);
182u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw,
183			    enum radio_path rfpath, u32 regaddr,
184			    u32 bitmask);
185void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw,
186			   enum radio_path rfpath, u32 regaddr,
187			   u32 bitmask, u32 data);
188bool rtl88e_phy_mac_config(struct ieee80211_hw *hw);
189bool rtl88e_phy_bb_config(struct ieee80211_hw *hw);
190bool rtl88e_phy_rf_config(struct ieee80211_hw *hw);
191void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
192void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw,
193				  long *powerlevel);
194void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
195void rtl88e_phy_scan_operation_backup(struct ieee80211_hw *hw,
196				      u8 operation);
197void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
198void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw,
199			    enum nl80211_channel_type ch_type);
200void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw);
201u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw);
202void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
203void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw);
204void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
205bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
206					  enum radio_path rfpath);
207bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
208bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw,
209				   enum rf_pwrstate rfpwr_state);
210
211#endif
212