1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 4 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> 5 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 6 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 7 8 Based on the original rt2800pci.c and rt2800usb.c. 9 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 10 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 11 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 12 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 13 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 14 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 15 <http://rt2x00.serialmonkey.com> 16 17 */ 18 19/* 20 Module: rt2800lib 21 Abstract: rt2800 generic device routines. 22 */ 23 24#include <linux/crc-ccitt.h> 25#include <linux/kernel.h> 26#include <linux/module.h> 27#include <linux/slab.h> 28 29#include "rt2x00.h" 30#include "rt2800lib.h" 31#include "rt2800.h" 32 33static bool modparam_watchdog; 34module_param_named(watchdog, modparam_watchdog, bool, S_IRUGO); 35MODULE_PARM_DESC(watchdog, "Enable watchdog to detect tx/rx hangs and reset hardware if detected"); 36 37/* 38 * Register access. 39 * All access to the CSR registers will go through the methods 40 * rt2800_register_read and rt2800_register_write. 41 * BBP and RF register require indirect register access, 42 * and use the CSR registers BBPCSR and RFCSR to achieve this. 43 * These indirect registers work with busy bits, 44 * and we will try maximal REGISTER_BUSY_COUNT times to access 45 * the register while taking a REGISTER_BUSY_DELAY us delay 46 * between each attampt. When the busy bit is still set at that time, 47 * the access attempt is considered to have failed, 48 * and we will print an error. 49 * The _lock versions must be used if you already hold the csr_mutex 50 */ 51#define WAIT_FOR_BBP(__dev, __reg) \ 52 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 53#define WAIT_FOR_RFCSR(__dev, __reg) \ 54 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) 55#define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \ 56 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \ 57 (__reg)) 58#define WAIT_FOR_RF(__dev, __reg) \ 59 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) 60#define WAIT_FOR_MCU(__dev, __reg) \ 61 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 62 H2M_MAILBOX_CSR_OWNER, (__reg)) 63 64static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) 65{ 66 /* check for rt2872 on SoC */ 67 if (!rt2x00_is_soc(rt2x00dev) || 68 !rt2x00_rt(rt2x00dev, RT2872)) 69 return false; 70 71 /* we know for sure that these rf chipsets are used on rt305x boards */ 72 if (rt2x00_rf(rt2x00dev, RF3020) || 73 rt2x00_rf(rt2x00dev, RF3021) || 74 rt2x00_rf(rt2x00dev, RF3022)) 75 return true; 76 77 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); 78 return false; 79} 80 81static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 82 const unsigned int word, const u8 value) 83{ 84 u32 reg; 85 86 mutex_lock(&rt2x00dev->csr_mutex); 87 88 /* 89 * Wait until the BBP becomes available, afterwards we 90 * can safely write the new data into the register. 91 */ 92 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 93 reg = 0; 94 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); 95 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 96 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 97 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); 98 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 99 100 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 101 } 102 103 mutex_unlock(&rt2x00dev->csr_mutex); 104} 105 106static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word) 107{ 108 u32 reg; 109 u8 value; 110 111 mutex_lock(&rt2x00dev->csr_mutex); 112 113 /* 114 * Wait until the BBP becomes available, afterwards we 115 * can safely write the read request into the register. 116 * After the data has been written, we wait until hardware 117 * returns the correct value, if at any time the register 118 * doesn't become available in time, reg will be 0xffffffff 119 * which means we return 0xff to the caller. 120 */ 121 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 122 reg = 0; 123 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 124 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 125 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); 126 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 127 128 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 129 130 WAIT_FOR_BBP(rt2x00dev, ®); 131 } 132 133 value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); 134 135 mutex_unlock(&rt2x00dev->csr_mutex); 136 137 return value; 138} 139 140static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 141 const unsigned int word, const u8 value) 142{ 143 u32 reg; 144 145 mutex_lock(&rt2x00dev->csr_mutex); 146 147 /* 148 * Wait until the RFCSR becomes available, afterwards we 149 * can safely write the new data into the register. 150 */ 151 switch (rt2x00dev->chip.rt) { 152 case RT6352: 153 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 154 reg = 0; 155 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); 156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 157 word); 158 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); 159 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 160 161 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 162 } 163 break; 164 165 default: 166 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 167 reg = 0; 168 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); 169 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 170 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); 171 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 172 173 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 174 } 175 break; 176 } 177 178 mutex_unlock(&rt2x00dev->csr_mutex); 179} 180 181static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 182 const unsigned int reg, const u8 value) 183{ 184 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value); 185} 186 187static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev, 188 const unsigned int reg, const u8 value) 189{ 190 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value); 191 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value); 192} 193 194static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev, 195 const unsigned int reg, const u8 value) 196{ 197 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value); 198 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value); 199} 200 201static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev, 202 const u8 reg, const u8 value) 203{ 204 rt2800_bbp_write(rt2x00dev, 158, reg); 205 rt2800_bbp_write(rt2x00dev, 159, value); 206} 207 208static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg) 209{ 210 rt2800_bbp_write(rt2x00dev, 158, reg); 211 return rt2800_bbp_read(rt2x00dev, 159); 212} 213 214static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev, 215 const u8 reg, const u8 value) 216{ 217 rt2800_bbp_write(rt2x00dev, 195, reg); 218 rt2800_bbp_write(rt2x00dev, 196, value); 219} 220 221static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 222 const unsigned int word) 223{ 224 u32 reg; 225 u8 value; 226 227 mutex_lock(&rt2x00dev->csr_mutex); 228 229 /* 230 * Wait until the RFCSR becomes available, afterwards we 231 * can safely write the read request into the register. 232 * After the data has been written, we wait until hardware 233 * returns the correct value, if at any time the register 234 * doesn't become available in time, reg will be 0xffffffff 235 * which means we return 0xff to the caller. 236 */ 237 switch (rt2x00dev->chip.rt) { 238 case RT6352: 239 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 240 reg = 0; 241 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 242 word); 243 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); 244 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 245 246 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 247 248 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®); 249 } 250 251 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620); 252 break; 253 254 default: 255 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 256 reg = 0; 257 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 258 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); 259 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 260 261 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 262 263 WAIT_FOR_RFCSR(rt2x00dev, ®); 264 } 265 266 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); 267 break; 268 } 269 270 mutex_unlock(&rt2x00dev->csr_mutex); 271 272 return value; 273} 274 275static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 276 const unsigned int reg) 277{ 278 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6))); 279} 280 281static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 282 const unsigned int word, const u32 value) 283{ 284 u32 reg; 285 286 mutex_lock(&rt2x00dev->csr_mutex); 287 288 /* 289 * Wait until the RF becomes available, afterwards we 290 * can safely write the new data into the register. 291 */ 292 if (WAIT_FOR_RF(rt2x00dev, ®)) { 293 reg = 0; 294 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); 295 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); 296 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); 297 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); 298 299 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); 300 rt2x00_rf_write(rt2x00dev, word, value); 301 } 302 303 mutex_unlock(&rt2x00dev->csr_mutex); 304} 305 306static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { 307 [EEPROM_CHIP_ID] = 0x0000, 308 [EEPROM_VERSION] = 0x0001, 309 [EEPROM_MAC_ADDR_0] = 0x0002, 310 [EEPROM_MAC_ADDR_1] = 0x0003, 311 [EEPROM_MAC_ADDR_2] = 0x0004, 312 [EEPROM_NIC_CONF0] = 0x001a, 313 [EEPROM_NIC_CONF1] = 0x001b, 314 [EEPROM_FREQ] = 0x001d, 315 [EEPROM_LED_AG_CONF] = 0x001e, 316 [EEPROM_LED_ACT_CONF] = 0x001f, 317 [EEPROM_LED_POLARITY] = 0x0020, 318 [EEPROM_NIC_CONF2] = 0x0021, 319 [EEPROM_LNA] = 0x0022, 320 [EEPROM_RSSI_BG] = 0x0023, 321 [EEPROM_RSSI_BG2] = 0x0024, 322 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ 323 [EEPROM_RSSI_A] = 0x0025, 324 [EEPROM_RSSI_A2] = 0x0026, 325 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ 326 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, 327 [EEPROM_TXPOWER_DELTA] = 0x0028, 328 [EEPROM_TXPOWER_BG1] = 0x0029, 329 [EEPROM_TXPOWER_BG2] = 0x0030, 330 [EEPROM_TSSI_BOUND_BG1] = 0x0037, 331 [EEPROM_TSSI_BOUND_BG2] = 0x0038, 332 [EEPROM_TSSI_BOUND_BG3] = 0x0039, 333 [EEPROM_TSSI_BOUND_BG4] = 0x003a, 334 [EEPROM_TSSI_BOUND_BG5] = 0x003b, 335 [EEPROM_TXPOWER_A1] = 0x003c, 336 [EEPROM_TXPOWER_A2] = 0x0053, 337 [EEPROM_TXPOWER_INIT] = 0x0068, 338 [EEPROM_TSSI_BOUND_A1] = 0x006a, 339 [EEPROM_TSSI_BOUND_A2] = 0x006b, 340 [EEPROM_TSSI_BOUND_A3] = 0x006c, 341 [EEPROM_TSSI_BOUND_A4] = 0x006d, 342 [EEPROM_TSSI_BOUND_A5] = 0x006e, 343 [EEPROM_TXPOWER_BYRATE] = 0x006f, 344 [EEPROM_BBP_START] = 0x0078, 345}; 346 347static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { 348 [EEPROM_CHIP_ID] = 0x0000, 349 [EEPROM_VERSION] = 0x0001, 350 [EEPROM_MAC_ADDR_0] = 0x0002, 351 [EEPROM_MAC_ADDR_1] = 0x0003, 352 [EEPROM_MAC_ADDR_2] = 0x0004, 353 [EEPROM_NIC_CONF0] = 0x001a, 354 [EEPROM_NIC_CONF1] = 0x001b, 355 [EEPROM_NIC_CONF2] = 0x001c, 356 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, 357 [EEPROM_FREQ] = 0x0022, 358 [EEPROM_LED_AG_CONF] = 0x0023, 359 [EEPROM_LED_ACT_CONF] = 0x0024, 360 [EEPROM_LED_POLARITY] = 0x0025, 361 [EEPROM_LNA] = 0x0026, 362 [EEPROM_EXT_LNA2] = 0x0027, 363 [EEPROM_RSSI_BG] = 0x0028, 364 [EEPROM_RSSI_BG2] = 0x0029, 365 [EEPROM_RSSI_A] = 0x002a, 366 [EEPROM_RSSI_A2] = 0x002b, 367 [EEPROM_TXPOWER_BG1] = 0x0030, 368 [EEPROM_TXPOWER_BG2] = 0x0037, 369 [EEPROM_EXT_TXPOWER_BG3] = 0x003e, 370 [EEPROM_TSSI_BOUND_BG1] = 0x0045, 371 [EEPROM_TSSI_BOUND_BG2] = 0x0046, 372 [EEPROM_TSSI_BOUND_BG3] = 0x0047, 373 [EEPROM_TSSI_BOUND_BG4] = 0x0048, 374 [EEPROM_TSSI_BOUND_BG5] = 0x0049, 375 [EEPROM_TXPOWER_A1] = 0x004b, 376 [EEPROM_TXPOWER_A2] = 0x0065, 377 [EEPROM_EXT_TXPOWER_A3] = 0x007f, 378 [EEPROM_TSSI_BOUND_A1] = 0x009a, 379 [EEPROM_TSSI_BOUND_A2] = 0x009b, 380 [EEPROM_TSSI_BOUND_A3] = 0x009c, 381 [EEPROM_TSSI_BOUND_A4] = 0x009d, 382 [EEPROM_TSSI_BOUND_A5] = 0x009e, 383 [EEPROM_TXPOWER_BYRATE] = 0x00a0, 384}; 385 386static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, 387 const enum rt2800_eeprom_word word) 388{ 389 const unsigned int *map; 390 unsigned int index; 391 392 if (WARN_ONCE(word >= EEPROM_WORD_COUNT, 393 "%s: invalid EEPROM word %d\n", 394 wiphy_name(rt2x00dev->hw->wiphy), word)) 395 return 0; 396 397 if (rt2x00_rt(rt2x00dev, RT3593) || 398 rt2x00_rt(rt2x00dev, RT3883)) 399 map = rt2800_eeprom_map_ext; 400 else 401 map = rt2800_eeprom_map; 402 403 index = map[word]; 404 405 /* Index 0 is valid only for EEPROM_CHIP_ID. 406 * Otherwise it means that the offset of the 407 * given word is not initialized in the map, 408 * or that the field is not usable on the 409 * actual chipset. 410 */ 411 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, 412 "%s: invalid access of EEPROM word %d\n", 413 wiphy_name(rt2x00dev->hw->wiphy), word); 414 415 return index; 416} 417 418static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, 419 const enum rt2800_eeprom_word word) 420{ 421 unsigned int index; 422 423 index = rt2800_eeprom_word_index(rt2x00dev, word); 424 return rt2x00_eeprom_addr(rt2x00dev, index); 425} 426 427static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, 428 const enum rt2800_eeprom_word word) 429{ 430 unsigned int index; 431 432 index = rt2800_eeprom_word_index(rt2x00dev, word); 433 return rt2x00_eeprom_read(rt2x00dev, index); 434} 435 436static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, 437 const enum rt2800_eeprom_word word, u16 data) 438{ 439 unsigned int index; 440 441 index = rt2800_eeprom_word_index(rt2x00dev, word); 442 rt2x00_eeprom_write(rt2x00dev, index, data); 443} 444 445static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, 446 const enum rt2800_eeprom_word array, 447 unsigned int offset) 448{ 449 unsigned int index; 450 451 index = rt2800_eeprom_word_index(rt2x00dev, array); 452 return rt2x00_eeprom_read(rt2x00dev, index + offset); 453} 454 455static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) 456{ 457 u32 reg; 458 int i, count; 459 460 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 461 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); 462 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); 463 rt2x00_set_field32(®, WLAN_CLK_EN, 0); 464 rt2x00_set_field32(®, WLAN_EN, 1); 465 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 466 467 udelay(REGISTER_BUSY_DELAY); 468 469 count = 0; 470 do { 471 /* 472 * Check PLL_LD & XTAL_RDY. 473 */ 474 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 475 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 476 if (rt2x00_get_field32(reg, PLL_LD) && 477 rt2x00_get_field32(reg, XTAL_RDY)) 478 break; 479 udelay(REGISTER_BUSY_DELAY); 480 } 481 482 if (i >= REGISTER_BUSY_COUNT) { 483 484 if (count >= 10) 485 return -EIO; 486 487 rt2800_register_write(rt2x00dev, 0x58, 0x018); 488 udelay(REGISTER_BUSY_DELAY); 489 rt2800_register_write(rt2x00dev, 0x58, 0x418); 490 udelay(REGISTER_BUSY_DELAY); 491 rt2800_register_write(rt2x00dev, 0x58, 0x618); 492 udelay(REGISTER_BUSY_DELAY); 493 count++; 494 } else { 495 count = 0; 496 } 497 498 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 499 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); 500 rt2x00_set_field32(®, WLAN_CLK_EN, 1); 501 rt2x00_set_field32(®, WLAN_RESET, 1); 502 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 503 udelay(10); 504 rt2x00_set_field32(®, WLAN_RESET, 0); 505 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 506 udelay(10); 507 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); 508 } while (count != 0); 509 510 return 0; 511} 512 513void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 514 const u8 command, const u8 token, 515 const u8 arg0, const u8 arg1) 516{ 517 u32 reg; 518 519 /* 520 * SOC devices don't support MCU requests. 521 */ 522 if (rt2x00_is_soc(rt2x00dev)) 523 return; 524 525 mutex_lock(&rt2x00dev->csr_mutex); 526 527 /* 528 * Wait until the MCU becomes available, afterwards we 529 * can safely write the new data into the register. 530 */ 531 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 532 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 533 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 534 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 535 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 536 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); 537 538 reg = 0; 539 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 540 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); 541 } 542 543 mutex_unlock(&rt2x00dev->csr_mutex); 544} 545EXPORT_SYMBOL_GPL(rt2800_mcu_request); 546 547int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) 548{ 549 unsigned int i = 0; 550 u32 reg; 551 552 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 553 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 554 if (reg && reg != ~0) 555 return 0; 556 msleep(1); 557 } 558 559 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 560 return -EBUSY; 561} 562EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); 563 564int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 565{ 566 unsigned int i; 567 u32 reg; 568 569 /* 570 * Some devices are really slow to respond here. Wait a whole second 571 * before timing out. 572 */ 573 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 574 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 575 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 576 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 577 return 0; 578 579 msleep(10); 580 } 581 582 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); 583 return -EACCES; 584} 585EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 586 587void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) 588{ 589 u32 reg; 590 591 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 592 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 593 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 594 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 595 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 596 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 597 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 598} 599EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); 600 601void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, 602 unsigned short *txwi_size, 603 unsigned short *rxwi_size) 604{ 605 switch (rt2x00dev->chip.rt) { 606 case RT3593: 607 case RT3883: 608 *txwi_size = TXWI_DESC_SIZE_4WORDS; 609 *rxwi_size = RXWI_DESC_SIZE_5WORDS; 610 break; 611 612 case RT5592: 613 case RT6352: 614 *txwi_size = TXWI_DESC_SIZE_5WORDS; 615 *rxwi_size = RXWI_DESC_SIZE_6WORDS; 616 break; 617 618 default: 619 *txwi_size = TXWI_DESC_SIZE_4WORDS; 620 *rxwi_size = RXWI_DESC_SIZE_4WORDS; 621 break; 622 } 623} 624EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size); 625 626static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) 627{ 628 u16 fw_crc; 629 u16 crc; 630 631 /* 632 * The last 2 bytes in the firmware array are the crc checksum itself, 633 * this means that we should never pass those 2 bytes to the crc 634 * algorithm. 635 */ 636 fw_crc = (data[len - 2] << 8 | data[len - 1]); 637 638 /* 639 * Use the crc ccitt algorithm. 640 * This will return the same value as the legacy driver which 641 * used bit ordering reversion on the both the firmware bytes 642 * before input input as well as on the final output. 643 * Obviously using crc ccitt directly is much more efficient. 644 */ 645 crc = crc_ccitt(~0, data, len - 2); 646 647 /* 648 * There is a small difference between the crc-itu-t + bitrev and 649 * the crc-ccitt crc calculation. In the latter method the 2 bytes 650 * will be swapped, use swab16 to convert the crc to the correct 651 * value. 652 */ 653 crc = swab16(crc); 654 655 return fw_crc == crc; 656} 657 658int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, 659 const u8 *data, const size_t len) 660{ 661 size_t offset = 0; 662 size_t fw_len; 663 bool multiple; 664 665 /* 666 * PCI(e) & SOC devices require firmware with a length 667 * of 8kb. USB devices require firmware files with a length 668 * of 4kb. Certain USB chipsets however require different firmware, 669 * which Ralink only provides attached to the original firmware 670 * file. Thus for USB devices, firmware files have a length 671 * which is a multiple of 4kb. The firmware for rt3290 chip also 672 * have a length which is a multiple of 4kb. 673 */ 674 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) 675 fw_len = 4096; 676 else 677 fw_len = 8192; 678 679 multiple = true; 680 /* 681 * Validate the firmware length 682 */ 683 if (len != fw_len && (!multiple || (len % fw_len) != 0)) 684 return FW_BAD_LENGTH; 685 686 /* 687 * Check if the chipset requires one of the upper parts 688 * of the firmware. 689 */ 690 if (rt2x00_is_usb(rt2x00dev) && 691 !rt2x00_rt(rt2x00dev, RT2860) && 692 !rt2x00_rt(rt2x00dev, RT2872) && 693 !rt2x00_rt(rt2x00dev, RT3070) && 694 ((len / fw_len) == 1)) 695 return FW_BAD_VERSION; 696 697 /* 698 * 8kb firmware files must be checked as if it were 699 * 2 separate firmware files. 700 */ 701 while (offset < len) { 702 if (!rt2800_check_firmware_crc(data + offset, fw_len)) 703 return FW_BAD_CRC; 704 705 offset += fw_len; 706 } 707 708 return FW_OK; 709} 710EXPORT_SYMBOL_GPL(rt2800_check_firmware); 711 712int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, 713 const u8 *data, const size_t len) 714{ 715 unsigned int i; 716 u32 reg; 717 int retval; 718 719 if (rt2x00_rt(rt2x00dev, RT3290)) { 720 retval = rt2800_enable_wlan_rt3290(rt2x00dev); 721 if (retval) 722 return -EBUSY; 723 } 724 725 /* 726 * If driver doesn't wake up firmware here, 727 * rt2800_load_firmware will hang forever when interface is up again. 728 */ 729 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 730 731 /* 732 * Wait for stable hardware. 733 */ 734 if (rt2800_wait_csr_ready(rt2x00dev)) 735 return -EBUSY; 736 737 if (rt2x00_is_pci(rt2x00dev)) { 738 if (rt2x00_rt(rt2x00dev, RT3290) || 739 rt2x00_rt(rt2x00dev, RT3572) || 740 rt2x00_rt(rt2x00dev, RT5390) || 741 rt2x00_rt(rt2x00dev, RT5392)) { 742 reg = rt2800_register_read(rt2x00dev, AUX_CTRL); 743 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); 744 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); 745 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 746 } 747 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 748 } 749 750 rt2800_disable_wpdma(rt2x00dev); 751 752 /* 753 * Write firmware to the device. 754 */ 755 rt2800_drv_write_firmware(rt2x00dev, data, len); 756 757 /* 758 * Wait for device to stabilize. 759 */ 760 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 761 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL); 762 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 763 break; 764 msleep(1); 765 } 766 767 if (i == REGISTER_BUSY_COUNT) { 768 rt2x00_err(rt2x00dev, "PBF system register not ready\n"); 769 return -EBUSY; 770 } 771 772 /* 773 * Disable DMA, will be reenabled later when enabling 774 * the radio. 775 */ 776 rt2800_disable_wpdma(rt2x00dev); 777 778 /* 779 * Initialize firmware. 780 */ 781 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 782 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 783 if (rt2x00_is_usb(rt2x00dev)) { 784 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 785 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 786 } 787 msleep(1); 788 789 return 0; 790} 791EXPORT_SYMBOL_GPL(rt2800_load_firmware); 792 793void rt2800_write_tx_data(struct queue_entry *entry, 794 struct txentry_desc *txdesc) 795{ 796 __le32 *txwi = rt2800_drv_get_txwi(entry); 797 u32 word; 798 int i; 799 800 /* 801 * Initialize TX Info descriptor 802 */ 803 word = rt2x00_desc_read(txwi, 0); 804 rt2x00_set_field32(&word, TXWI_W0_FRAG, 805 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 806 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 807 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); 808 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 809 rt2x00_set_field32(&word, TXWI_W0_TS, 810 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 811 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 812 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 813 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, 814 txdesc->u.ht.mpdu_density); 815 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); 816 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); 817 rt2x00_set_field32(&word, TXWI_W0_BW, 818 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 819 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 820 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 821 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); 822 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 823 rt2x00_desc_write(txwi, 0, word); 824 825 word = rt2x00_desc_read(txwi, 1); 826 rt2x00_set_field32(&word, TXWI_W1_ACK, 827 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 828 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 829 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 830 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); 831 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 832 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 833 txdesc->key_idx : txdesc->u.ht.wcid); 834 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 835 txdesc->length); 836 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); 837 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); 838 rt2x00_desc_write(txwi, 1, word); 839 840 /* 841 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert 842 * the IV from the IVEIV register when TXD_W3_WIV is set to 0. 843 * When TXD_W3_WIV is set to 1 it will use the IV data 844 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 845 * crypto entry in the registers should be used to encrypt the frame. 846 * 847 * Nulify all remaining words as well, we don't know how to program them. 848 */ 849 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) 850 _rt2x00_desc_write(txwi, i, 0); 851} 852EXPORT_SYMBOL_GPL(rt2800_write_tx_data); 853 854static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) 855{ 856 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); 857 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); 858 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); 859 u16 eeprom; 860 u8 offset0; 861 u8 offset1; 862 u8 offset2; 863 864 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 865 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 866 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); 867 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); 868 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 869 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); 870 } else { 871 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 872 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); 873 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); 874 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 875 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); 876 } 877 878 /* 879 * Convert the value from the descriptor into the RSSI value 880 * If the value in the descriptor is 0, it is considered invalid 881 * and the default (extremely low) rssi value is assumed 882 */ 883 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; 884 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; 885 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; 886 887 /* 888 * mac80211 only accepts a single RSSI value. Calculating the 889 * average doesn't deliver a fair answer either since -60:-60 would 890 * be considered equally good as -50:-70 while the second is the one 891 * which gives less energy... 892 */ 893 rssi0 = max(rssi0, rssi1); 894 return (int)max(rssi0, rssi2); 895} 896 897void rt2800_process_rxwi(struct queue_entry *entry, 898 struct rxdone_entry_desc *rxdesc) 899{ 900 __le32 *rxwi = (__le32 *) entry->skb->data; 901 u32 word; 902 903 word = rt2x00_desc_read(rxwi, 0); 904 905 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); 906 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); 907 908 word = rt2x00_desc_read(rxwi, 1); 909 910 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) 911 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI; 912 913 if (rt2x00_get_field32(word, RXWI_W1_BW)) 914 rxdesc->bw = RATE_INFO_BW_40; 915 916 /* 917 * Detect RX rate, always use MCS as signal type. 918 */ 919 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 920 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); 921 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); 922 923 /* 924 * Mask of 0x8 bit to remove the short preamble flag. 925 */ 926 if (rxdesc->rate_mode == RATE_MODE_CCK) 927 rxdesc->signal &= ~0x8; 928 929 word = rt2x00_desc_read(rxwi, 2); 930 931 /* 932 * Convert descriptor AGC value to RSSI value. 933 */ 934 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); 935 /* 936 * Remove RXWI descriptor from start of the buffer. 937 */ 938 skb_pull(entry->skb, entry->queue->winfo_size); 939} 940EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 941 942static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc, 943 u32 status, enum nl80211_band band) 944{ 945 u8 flags = 0; 946 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 947 948 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) { 949 case RATE_MODE_HT_GREENFIELD: 950 flags |= IEEE80211_TX_RC_GREEN_FIELD; 951 fallthrough; 952 case RATE_MODE_HT_MIX: 953 flags |= IEEE80211_TX_RC_MCS; 954 break; 955 case RATE_MODE_OFDM: 956 if (band == NL80211_BAND_2GHZ) 957 idx += 4; 958 break; 959 case RATE_MODE_CCK: 960 if (idx >= 8) 961 idx -= 8; 962 break; 963 } 964 965 if (rt2x00_get_field32(status, TX_STA_FIFO_BW)) 966 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 967 968 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI)) 969 flags |= IEEE80211_TX_RC_SHORT_GI; 970 971 skbdesc->tx_rate_idx = idx; 972 skbdesc->tx_rate_flags = flags; 973} 974 975static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg) 976{ 977 __le32 *txwi; 978 u32 word; 979 int wcid, ack, pid; 980 int tx_wcid, tx_ack, tx_pid, is_agg; 981 982 /* 983 * This frames has returned with an IO error, 984 * so the status report is not intended for this 985 * frame. 986 */ 987 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) 988 return false; 989 990 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID); 991 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED); 992 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE); 993 is_agg = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE); 994 995 /* 996 * Validate if this TX status report is intended for 997 * this entry by comparing the WCID/ACK/PID fields. 998 */ 999 txwi = rt2800_drv_get_txwi(entry); 1000 1001 word = rt2x00_desc_read(txwi, 1); 1002 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID); 1003 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK); 1004 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID); 1005 1006 if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) { 1007 rt2x00_dbg(entry->queue->rt2x00dev, 1008 "TX status report missed for queue %d entry %d\n", 1009 entry->queue->qid, entry->entry_idx); 1010 return false; 1011 } 1012 1013 return true; 1014} 1015 1016void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi, 1017 bool match) 1018{ 1019 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1020 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1021 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1022 struct txdone_entry_desc txdesc; 1023 u32 word; 1024 u16 mcs, real_mcs; 1025 int aggr, ampdu, wcid, ack_req; 1026 1027 /* 1028 * Obtain the status about this packet. 1029 */ 1030 txdesc.flags = 0; 1031 word = rt2x00_desc_read(txwi, 0); 1032 1033 mcs = rt2x00_get_field32(word, TXWI_W0_MCS); 1034 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); 1035 1036 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 1037 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); 1038 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID); 1039 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED); 1040 1041 /* 1042 * If a frame was meant to be sent as a single non-aggregated MPDU 1043 * but ended up in an aggregate the used tx rate doesn't correlate 1044 * with the one specified in the TXWI as the whole aggregate is sent 1045 * with the same rate. 1046 * 1047 * For example: two frames are sent to rt2x00, the first one sets 1048 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 1049 * and requests MCS15. If the hw aggregates both frames into one 1050 * AMDPU the tx status for both frames will contain MCS7 although 1051 * the frame was sent successfully. 1052 * 1053 * Hence, replace the requested rate with the real tx rate to not 1054 * confuse the rate control algortihm by providing clearly wrong 1055 * data. 1056 * 1057 * FIXME: if we do not find matching entry, we tell that frame was 1058 * posted without any retries. We need to find a way to fix that 1059 * and provide retry count. 1060 */ 1061 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) { 1062 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band); 1063 mcs = real_mcs; 1064 } 1065 1066 if (aggr == 1 || ampdu == 1) 1067 __set_bit(TXDONE_AMPDU, &txdesc.flags); 1068 1069 if (!ack_req) 1070 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags); 1071 1072 /* 1073 * Ralink has a retry mechanism using a global fallback 1074 * table. We setup this fallback table to try the immediate 1075 * lower rate for all rates. In the TX_STA_FIFO, the MCS field 1076 * always contains the MCS used for the last transmission, be 1077 * it successful or not. 1078 */ 1079 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { 1080 /* 1081 * Transmission succeeded. The number of retries is 1082 * mcs - real_mcs 1083 */ 1084 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 1085 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 1086 } else { 1087 /* 1088 * Transmission failed. The number of retries is 1089 * always 7 in this case (for a total number of 8 1090 * frames sent). 1091 */ 1092 __set_bit(TXDONE_FAILURE, &txdesc.flags); 1093 txdesc.retry = rt2x00dev->long_retry; 1094 } 1095 1096 /* 1097 * the frame was retried at least once 1098 * -> hw used fallback rates 1099 */ 1100 if (txdesc.retry) 1101 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 1102 1103 if (!match) { 1104 /* RCU assures non-null sta will not be freed by mac80211. */ 1105 rcu_read_lock(); 1106 if (likely(wcid >= WCID_START && wcid <= WCID_END)) 1107 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START]; 1108 else 1109 skbdesc->sta = NULL; 1110 rt2x00lib_txdone_nomatch(entry, &txdesc); 1111 rcu_read_unlock(); 1112 } else { 1113 rt2x00lib_txdone(entry, &txdesc); 1114 } 1115} 1116EXPORT_SYMBOL_GPL(rt2800_txdone_entry); 1117 1118void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota) 1119{ 1120 struct data_queue *queue; 1121 struct queue_entry *entry; 1122 u32 reg; 1123 u8 qid; 1124 bool match; 1125 1126 while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, ®)) { 1127 /* 1128 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is 1129 * guaranteed to be one of the TX QIDs . 1130 */ 1131 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE); 1132 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid); 1133 1134 if (unlikely(rt2x00queue_empty(queue))) { 1135 rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n", 1136 qid); 1137 break; 1138 } 1139 1140 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1141 1142 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1143 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) { 1144 rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n", 1145 entry->entry_idx, qid); 1146 break; 1147 } 1148 1149 match = rt2800_txdone_entry_check(entry, reg); 1150 rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match); 1151 } 1152} 1153EXPORT_SYMBOL_GPL(rt2800_txdone); 1154 1155static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev, 1156 struct queue_entry *entry) 1157{ 1158 bool ret; 1159 unsigned long tout; 1160 1161 if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1162 return false; 1163 1164 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags)) 1165 tout = msecs_to_jiffies(50); 1166 else 1167 tout = msecs_to_jiffies(2000); 1168 1169 ret = time_after(jiffies, entry->last_action + tout); 1170 if (unlikely(ret)) 1171 rt2x00_dbg(entry->queue->rt2x00dev, 1172 "TX status timeout for entry %d in queue %d\n", 1173 entry->entry_idx, entry->queue->qid); 1174 return ret; 1175} 1176 1177bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev) 1178{ 1179 struct data_queue *queue; 1180 struct queue_entry *entry; 1181 1182 tx_queue_for_each(rt2x00dev, queue) { 1183 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1184 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1185 return true; 1186 } 1187 1188 return false; 1189} 1190EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout); 1191 1192/* 1193 * test if there is an entry in any TX queue for which DMA is done 1194 * but the TX status has not been returned yet 1195 */ 1196bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev) 1197{ 1198 struct data_queue *queue; 1199 1200 tx_queue_for_each(rt2x00dev, queue) { 1201 if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) != 1202 rt2x00queue_get_entry(queue, Q_INDEX_DONE)) 1203 return true; 1204 } 1205 return false; 1206} 1207EXPORT_SYMBOL_GPL(rt2800_txstatus_pending); 1208 1209void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev) 1210{ 1211 struct data_queue *queue; 1212 struct queue_entry *entry; 1213 1214 /* 1215 * Process any trailing TX status reports for IO failures, 1216 * we loop until we find the first non-IO error entry. This 1217 * can either be a frame which is free, is being uploaded, 1218 * or has completed the upload but didn't have an entry 1219 * in the TX_STAT_FIFO register yet. 1220 */ 1221 tx_queue_for_each(rt2x00dev, queue) { 1222 while (!rt2x00queue_empty(queue)) { 1223 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1224 1225 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1226 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1227 break; 1228 1229 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) || 1230 rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1231 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE); 1232 else 1233 break; 1234 } 1235 } 1236} 1237EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus); 1238 1239static int rt2800_check_hung(struct data_queue *queue) 1240{ 1241 unsigned int cur_idx = rt2800_drv_get_dma_done(queue); 1242 1243 if (queue->wd_idx != cur_idx) 1244 queue->wd_count = 0; 1245 else 1246 queue->wd_count++; 1247 1248 return queue->wd_count > 16; 1249} 1250 1251static void rt2800_update_survey(struct rt2x00_dev *rt2x00dev) 1252{ 1253 struct ieee80211_channel *chan = rt2x00dev->hw->conf.chandef.chan; 1254 struct rt2x00_chan_survey *chan_survey = 1255 &rt2x00dev->chan_survey[chan->hw_value]; 1256 1257 chan_survey->time_idle += rt2800_register_read(rt2x00dev, CH_IDLE_STA); 1258 chan_survey->time_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA); 1259 chan_survey->time_ext_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 1260} 1261 1262void rt2800_watchdog(struct rt2x00_dev *rt2x00dev) 1263{ 1264 struct data_queue *queue; 1265 bool hung_tx = false; 1266 bool hung_rx = false; 1267 1268 if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) 1269 return; 1270 1271 rt2800_update_survey(rt2x00dev); 1272 1273 queue_for_each(rt2x00dev, queue) { 1274 switch (queue->qid) { 1275 case QID_AC_VO: 1276 case QID_AC_VI: 1277 case QID_AC_BE: 1278 case QID_AC_BK: 1279 case QID_MGMT: 1280 if (rt2x00queue_empty(queue)) 1281 continue; 1282 hung_tx = rt2800_check_hung(queue); 1283 break; 1284 case QID_RX: 1285 /* For station mode we should reactive at least 1286 * beacons. TODO: need to find good way detect 1287 * RX hung for AP mode. 1288 */ 1289 if (rt2x00dev->intf_sta_count == 0) 1290 continue; 1291 hung_rx = rt2800_check_hung(queue); 1292 break; 1293 default: 1294 break; 1295 } 1296 } 1297 1298 if (hung_tx) 1299 rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n"); 1300 1301 if (hung_rx) 1302 rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n"); 1303 1304 if (hung_tx || hung_rx) 1305 ieee80211_restart_hw(rt2x00dev->hw); 1306} 1307EXPORT_SYMBOL_GPL(rt2800_watchdog); 1308 1309static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev, 1310 unsigned int index) 1311{ 1312 return HW_BEACON_BASE(index); 1313} 1314 1315static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev, 1316 unsigned int index) 1317{ 1318 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index)); 1319} 1320 1321static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) 1322{ 1323 struct data_queue *queue = rt2x00dev->bcn; 1324 struct queue_entry *entry; 1325 int i, bcn_num = 0; 1326 u64 off, reg = 0; 1327 u32 bssid_dw1; 1328 1329 /* 1330 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers. 1331 */ 1332 for (i = 0; i < queue->limit; i++) { 1333 entry = &queue->entries[i]; 1334 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags)) 1335 continue; 1336 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx); 1337 reg |= off << (8 * bcn_num); 1338 bcn_num++; 1339 } 1340 1341 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); 1342 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); 1343 1344 /* 1345 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. 1346 */ 1347 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1); 1348 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, 1349 bcn_num > 0 ? bcn_num - 1 : 0); 1350 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); 1351} 1352 1353void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 1354{ 1355 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1356 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1357 unsigned int beacon_base; 1358 unsigned int padding_len; 1359 u32 orig_reg, reg; 1360 const int txwi_desc_size = entry->queue->winfo_size; 1361 1362 /* 1363 * Disable beaconing while we are reloading the beacon data, 1364 * otherwise we might be sending out invalid data. 1365 */ 1366 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1367 orig_reg = reg; 1368 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1369 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1370 1371 /* 1372 * Add space for the TXWI in front of the skb. 1373 */ 1374 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); 1375 1376 /* 1377 * Register descriptor details in skb frame descriptor. 1378 */ 1379 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 1380 skbdesc->desc = entry->skb->data; 1381 skbdesc->desc_len = txwi_desc_size; 1382 1383 /* 1384 * Add the TXWI for the beacon to the skb. 1385 */ 1386 rt2800_write_tx_data(entry, txdesc); 1387 1388 /* 1389 * Dump beacon to userspace through debugfs. 1390 */ 1391 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); 1392 1393 /* 1394 * Write entire beacon with TXWI and padding to register. 1395 */ 1396 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1397 if (padding_len && skb_pad(entry->skb, padding_len)) { 1398 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 1399 /* skb freed by skb_pad() on failure */ 1400 entry->skb = NULL; 1401 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1402 return; 1403 } 1404 1405 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx); 1406 1407 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1408 entry->skb->len + padding_len); 1409 __set_bit(ENTRY_BCN_ENABLED, &entry->flags); 1410 1411 /* 1412 * Change global beacons settings. 1413 */ 1414 rt2800_update_beacons_setup(rt2x00dev); 1415 1416 /* 1417 * Restore beaconing state. 1418 */ 1419 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1420 1421 /* 1422 * Clean up beacon skb. 1423 */ 1424 dev_kfree_skb_any(entry->skb); 1425 entry->skb = NULL; 1426} 1427EXPORT_SYMBOL_GPL(rt2800_write_beacon); 1428 1429static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, 1430 unsigned int index) 1431{ 1432 int i; 1433 const int txwi_desc_size = rt2x00dev->bcn->winfo_size; 1434 unsigned int beacon_base; 1435 1436 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index); 1437 1438 /* 1439 * For the Beacon base registers we only need to clear 1440 * the whole TXWI which (when set to 0) will invalidate 1441 * the entire beacon. 1442 */ 1443 for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) 1444 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 1445} 1446 1447void rt2800_clear_beacon(struct queue_entry *entry) 1448{ 1449 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1450 u32 orig_reg, reg; 1451 1452 /* 1453 * Disable beaconing while we are reloading the beacon data, 1454 * otherwise we might be sending out invalid data. 1455 */ 1456 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1457 reg = orig_reg; 1458 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1459 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1460 1461 /* 1462 * Clear beacon. 1463 */ 1464 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx); 1465 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags); 1466 1467 /* 1468 * Change global beacons settings. 1469 */ 1470 rt2800_update_beacons_setup(rt2x00dev); 1471 /* 1472 * Restore beaconing state. 1473 */ 1474 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1475} 1476EXPORT_SYMBOL_GPL(rt2800_clear_beacon); 1477 1478#ifdef CONFIG_RT2X00_LIB_DEBUGFS 1479const struct rt2x00debug rt2800_rt2x00debug = { 1480 .owner = THIS_MODULE, 1481 .csr = { 1482 .read = rt2800_register_read, 1483 .write = rt2800_register_write, 1484 .flags = RT2X00DEBUGFS_OFFSET, 1485 .word_base = CSR_REG_BASE, 1486 .word_size = sizeof(u32), 1487 .word_count = CSR_REG_SIZE / sizeof(u32), 1488 }, 1489 .eeprom = { 1490 /* NOTE: The local EEPROM access functions can't 1491 * be used here, use the generic versions instead. 1492 */ 1493 .read = rt2x00_eeprom_read, 1494 .write = rt2x00_eeprom_write, 1495 .word_base = EEPROM_BASE, 1496 .word_size = sizeof(u16), 1497 .word_count = EEPROM_SIZE / sizeof(u16), 1498 }, 1499 .bbp = { 1500 .read = rt2800_bbp_read, 1501 .write = rt2800_bbp_write, 1502 .word_base = BBP_BASE, 1503 .word_size = sizeof(u8), 1504 .word_count = BBP_SIZE / sizeof(u8), 1505 }, 1506 .rf = { 1507 .read = rt2x00_rf_read, 1508 .write = rt2800_rf_write, 1509 .word_base = RF_BASE, 1510 .word_size = sizeof(u32), 1511 .word_count = RF_SIZE / sizeof(u32), 1512 }, 1513 .rfcsr = { 1514 .read = rt2800_rfcsr_read, 1515 .write = rt2800_rfcsr_write, 1516 .word_base = RFCSR_BASE, 1517 .word_size = sizeof(u8), 1518 .word_count = RFCSR_SIZE / sizeof(u8), 1519 }, 1520}; 1521EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); 1522#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1523 1524int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) 1525{ 1526 u32 reg; 1527 1528 if (rt2x00_rt(rt2x00dev, RT3290)) { 1529 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 1530 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); 1531 } else { 1532 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 1533 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); 1534 } 1535} 1536EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 1537 1538#ifdef CONFIG_RT2X00_LIB_LEDS 1539static void rt2800_brightness_set(struct led_classdev *led_cdev, 1540 enum led_brightness brightness) 1541{ 1542 struct rt2x00_led *led = 1543 container_of(led_cdev, struct rt2x00_led, led_dev); 1544 unsigned int enabled = brightness != LED_OFF; 1545 unsigned int bg_mode = 1546 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); 1547 unsigned int polarity = 1548 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1549 EEPROM_FREQ_LED_POLARITY); 1550 unsigned int ledmode = 1551 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1552 EEPROM_FREQ_LED_MODE); 1553 u32 reg; 1554 1555 /* Check for SoC (SOC devices don't support MCU requests) */ 1556 if (rt2x00_is_soc(led->rt2x00dev)) { 1557 reg = rt2800_register_read(led->rt2x00dev, LED_CFG); 1558 1559 /* Set LED Polarity */ 1560 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); 1561 1562 /* Set LED Mode */ 1563 if (led->type == LED_TYPE_RADIO) { 1564 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 1565 enabled ? 3 : 0); 1566 } else if (led->type == LED_TYPE_ASSOC) { 1567 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 1568 enabled ? 3 : 0); 1569 } else if (led->type == LED_TYPE_QUALITY) { 1570 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 1571 enabled ? 3 : 0); 1572 } 1573 1574 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 1575 1576 } else { 1577 if (led->type == LED_TYPE_RADIO) { 1578 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1579 enabled ? 0x20 : 0); 1580 } else if (led->type == LED_TYPE_ASSOC) { 1581 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1582 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 1583 } else if (led->type == LED_TYPE_QUALITY) { 1584 /* 1585 * The brightness is divided into 6 levels (0 - 5), 1586 * The specs tell us the following levels: 1587 * 0, 1 ,3, 7, 15, 31 1588 * to determine the level in a simple way we can simply 1589 * work with bitshifting: 1590 * (1 << level) - 1 1591 */ 1592 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 1593 (1 << brightness / (LED_FULL / 6)) - 1, 1594 polarity); 1595 } 1596 } 1597} 1598 1599static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, 1600 struct rt2x00_led *led, enum led_type type) 1601{ 1602 led->rt2x00dev = rt2x00dev; 1603 led->type = type; 1604 led->led_dev.brightness_set = rt2800_brightness_set; 1605 led->flags = LED_INITIALIZED; 1606} 1607#endif /* CONFIG_RT2X00_LIB_LEDS */ 1608 1609/* 1610 * Configuration handlers. 1611 */ 1612static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, 1613 const u8 *address, 1614 int wcid) 1615{ 1616 struct mac_wcid_entry wcid_entry; 1617 u32 offset; 1618 1619 offset = MAC_WCID_ENTRY(wcid); 1620 1621 memset(&wcid_entry, 0xff, sizeof(wcid_entry)); 1622 if (address) 1623 memcpy(wcid_entry.mac, address, ETH_ALEN); 1624 1625 rt2800_register_multiwrite(rt2x00dev, offset, 1626 &wcid_entry, sizeof(wcid_entry)); 1627} 1628 1629static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) 1630{ 1631 u32 offset; 1632 offset = MAC_WCID_ATTR_ENTRY(wcid); 1633 rt2800_register_write(rt2x00dev, offset, 0); 1634} 1635 1636static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, 1637 int wcid, u32 bssidx) 1638{ 1639 u32 offset = MAC_WCID_ATTR_ENTRY(wcid); 1640 u32 reg; 1641 1642 /* 1643 * The BSS Idx numbers is split in a main value of 3 bits, 1644 * and a extended field for adding one additional bit to the value. 1645 */ 1646 reg = rt2800_register_read(rt2x00dev, offset); 1647 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); 1648 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, 1649 (bssidx & 0x8) >> 3); 1650 rt2800_register_write(rt2x00dev, offset, reg); 1651} 1652 1653static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, 1654 struct rt2x00lib_crypto *crypto, 1655 struct ieee80211_key_conf *key) 1656{ 1657 struct mac_iveiv_entry iveiv_entry; 1658 u32 offset; 1659 u32 reg; 1660 1661 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 1662 1663 if (crypto->cmd == SET_KEY) { 1664 reg = rt2800_register_read(rt2x00dev, offset); 1665 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 1666 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 1667 /* 1668 * Both the cipher as the BSS Idx numbers are split in a main 1669 * value of 3 bits, and a extended field for adding one additional 1670 * bit to the value. 1671 */ 1672 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 1673 (crypto->cipher & 0x7)); 1674 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 1675 (crypto->cipher & 0x8) >> 3); 1676 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 1677 rt2800_register_write(rt2x00dev, offset, reg); 1678 } else { 1679 /* Delete the cipher without touching the bssidx */ 1680 reg = rt2800_register_read(rt2x00dev, offset); 1681 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); 1682 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); 1683 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); 1684 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); 1685 rt2800_register_write(rt2x00dev, offset, reg); 1686 } 1687 1688 if (test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags)) 1689 return; 1690 1691 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 1692 1693 memset(&iveiv_entry, 0, sizeof(iveiv_entry)); 1694 if ((crypto->cipher == CIPHER_TKIP) || 1695 (crypto->cipher == CIPHER_TKIP_NO_MIC) || 1696 (crypto->cipher == CIPHER_AES)) 1697 iveiv_entry.iv[3] |= 0x20; 1698 iveiv_entry.iv[3] |= key->keyidx << 6; 1699 rt2800_register_multiwrite(rt2x00dev, offset, 1700 &iveiv_entry, sizeof(iveiv_entry)); 1701} 1702 1703int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, 1704 struct rt2x00lib_crypto *crypto, 1705 struct ieee80211_key_conf *key) 1706{ 1707 struct hw_key_entry key_entry; 1708 struct rt2x00_field32 field; 1709 u32 offset; 1710 u32 reg; 1711 1712 if (crypto->cmd == SET_KEY) { 1713 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; 1714 1715 memcpy(key_entry.key, crypto->key, 1716 sizeof(key_entry.key)); 1717 memcpy(key_entry.tx_mic, crypto->tx_mic, 1718 sizeof(key_entry.tx_mic)); 1719 memcpy(key_entry.rx_mic, crypto->rx_mic, 1720 sizeof(key_entry.rx_mic)); 1721 1722 offset = SHARED_KEY_ENTRY(key->hw_key_idx); 1723 rt2800_register_multiwrite(rt2x00dev, offset, 1724 &key_entry, sizeof(key_entry)); 1725 } 1726 1727 /* 1728 * The cipher types are stored over multiple registers 1729 * starting with SHARED_KEY_MODE_BASE each word will have 1730 * 32 bits and contains the cipher types for 2 bssidx each. 1731 * Using the correct defines correctly will cause overhead, 1732 * so just calculate the correct offset. 1733 */ 1734 field.bit_offset = 4 * (key->hw_key_idx % 8); 1735 field.bit_mask = 0x7 << field.bit_offset; 1736 1737 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 1738 1739 reg = rt2800_register_read(rt2x00dev, offset); 1740 rt2x00_set_field32(®, field, 1741 (crypto->cmd == SET_KEY) * crypto->cipher); 1742 rt2800_register_write(rt2x00dev, offset, reg); 1743 1744 /* 1745 * Update WCID information 1746 */ 1747 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); 1748 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, 1749 crypto->bssidx); 1750 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1751 1752 return 0; 1753} 1754EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1755 1756int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1757 struct rt2x00lib_crypto *crypto, 1758 struct ieee80211_key_conf *key) 1759{ 1760 struct hw_key_entry key_entry; 1761 u32 offset; 1762 1763 if (crypto->cmd == SET_KEY) { 1764 /* 1765 * Allow key configuration only for STAs that are 1766 * known by the hw. 1767 */ 1768 if (crypto->wcid > WCID_END) 1769 return -ENOSPC; 1770 key->hw_key_idx = crypto->wcid; 1771 1772 memcpy(key_entry.key, crypto->key, 1773 sizeof(key_entry.key)); 1774 memcpy(key_entry.tx_mic, crypto->tx_mic, 1775 sizeof(key_entry.tx_mic)); 1776 memcpy(key_entry.rx_mic, crypto->rx_mic, 1777 sizeof(key_entry.rx_mic)); 1778 1779 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 1780 rt2800_register_multiwrite(rt2x00dev, offset, 1781 &key_entry, sizeof(key_entry)); 1782 } 1783 1784 /* 1785 * Update WCID information 1786 */ 1787 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1788 1789 return 0; 1790} 1791EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); 1792 1793static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev) 1794{ 1795 u8 i, max_psdu; 1796 u32 reg; 1797 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1798 1799 for (i = 0; i < 3; i++) 1800 if (drv_data->ampdu_factor_cnt[i] > 0) 1801 break; 1802 1803 max_psdu = min(drv_data->max_psdu, i); 1804 1805 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 1806 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); 1807 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1808} 1809 1810int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1811 struct ieee80211_sta *sta) 1812{ 1813 struct rt2x00_dev *rt2x00dev = hw->priv; 1814 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1815 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1816 int wcid; 1817 1818 /* 1819 * Limit global maximum TX AMPDU length to smallest value of all 1820 * connected stations. In AP mode this can be suboptimal, but we 1821 * do not have a choice if some connected STA is not capable to 1822 * receive the same amount of data like the others. 1823 */ 1824 if (sta->deflink.ht_cap.ht_supported) { 1825 drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]++; 1826 rt2800_set_max_psdu_len(rt2x00dev); 1827 } 1828 1829 /* 1830 * Search for the first free WCID entry and return the corresponding 1831 * index. 1832 */ 1833 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START; 1834 1835 /* 1836 * Store selected wcid even if it is invalid so that we can 1837 * later decide if the STA is uploaded into the hw. 1838 */ 1839 sta_priv->wcid = wcid; 1840 1841 /* 1842 * No space left in the device, however, we can still communicate 1843 * with the STA -> No error. 1844 */ 1845 if (wcid > WCID_END) 1846 return 0; 1847 1848 __set_bit(wcid - WCID_START, drv_data->sta_ids); 1849 drv_data->wcid_to_sta[wcid - WCID_START] = sta; 1850 1851 /* 1852 * Clean up WCID attributes and write STA address to the device. 1853 */ 1854 rt2800_delete_wcid_attr(rt2x00dev, wcid); 1855 rt2800_config_wcid(rt2x00dev, sta->addr, wcid); 1856 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, 1857 rt2x00lib_get_bssidx(rt2x00dev, vif)); 1858 return 0; 1859} 1860EXPORT_SYMBOL_GPL(rt2800_sta_add); 1861 1862int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1863 struct ieee80211_sta *sta) 1864{ 1865 struct rt2x00_dev *rt2x00dev = hw->priv; 1866 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1867 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1868 int wcid = sta_priv->wcid; 1869 1870 if (sta->deflink.ht_cap.ht_supported) { 1871 drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]--; 1872 rt2800_set_max_psdu_len(rt2x00dev); 1873 } 1874 1875 if (wcid > WCID_END) 1876 return 0; 1877 /* 1878 * Remove WCID entry, no need to clean the attributes as they will 1879 * get renewed when the WCID is reused. 1880 */ 1881 rt2800_config_wcid(rt2x00dev, NULL, wcid); 1882 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1883 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1884 1885 return 0; 1886} 1887EXPORT_SYMBOL_GPL(rt2800_sta_remove); 1888 1889void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev) 1890{ 1891 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1892 struct data_queue *queue = rt2x00dev->bcn; 1893 struct queue_entry *entry; 1894 int i, wcid; 1895 1896 for (wcid = WCID_START; wcid < WCID_END; wcid++) { 1897 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1898 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1899 } 1900 1901 for (i = 0; i < queue->limit; i++) { 1902 entry = &queue->entries[i]; 1903 clear_bit(ENTRY_BCN_ASSIGNED, &entry->flags); 1904 } 1905} 1906EXPORT_SYMBOL_GPL(rt2800_pre_reset_hw); 1907 1908void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 1909 const unsigned int filter_flags) 1910{ 1911 u32 reg; 1912 1913 /* 1914 * Start configuration steps. 1915 * Note that the version error will always be dropped 1916 * and broadcast frames will always be accepted since 1917 * there is no filter for it at this time. 1918 */ 1919 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG); 1920 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, 1921 !(filter_flags & FIF_FCSFAIL)); 1922 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, 1923 !(filter_flags & FIF_PLCPFAIL)); 1924 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, 1925 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 1926 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); 1927 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); 1928 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, 1929 !(filter_flags & FIF_ALLMULTI)); 1930 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); 1931 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); 1932 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, 1933 !(filter_flags & FIF_CONTROL)); 1934 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, 1935 !(filter_flags & FIF_CONTROL)); 1936 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, 1937 !(filter_flags & FIF_CONTROL)); 1938 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, 1939 !(filter_flags & FIF_CONTROL)); 1940 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, 1941 !(filter_flags & FIF_CONTROL)); 1942 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, 1943 !(filter_flags & FIF_PSPOLL)); 1944 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); 1945 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 1946 !(filter_flags & FIF_CONTROL)); 1947 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, 1948 !(filter_flags & FIF_CONTROL)); 1949 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); 1950} 1951EXPORT_SYMBOL_GPL(rt2800_config_filter); 1952 1953void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 1954 struct rt2x00intf_conf *conf, const unsigned int flags) 1955{ 1956 u32 reg; 1957 bool update_bssid = false; 1958 1959 if (flags & CONFIG_UPDATE_TYPE) { 1960 /* 1961 * Enable synchronisation. 1962 */ 1963 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1964 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1965 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1966 1967 if (conf->sync == TSF_SYNC_AP_NONE) { 1968 /* 1969 * Tune beacon queue transmit parameters for AP mode 1970 */ 1971 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1972 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); 1973 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); 1974 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1975 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); 1976 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1977 } else { 1978 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1979 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); 1980 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); 1981 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1982 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); 1983 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1984 } 1985 } 1986 1987 if (flags & CONFIG_UPDATE_MAC) { 1988 if (flags & CONFIG_UPDATE_TYPE && 1989 conf->sync == TSF_SYNC_AP_NONE) { 1990 /* 1991 * The BSSID register has to be set to our own mac 1992 * address in AP mode. 1993 */ 1994 memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); 1995 update_bssid = true; 1996 } 1997 1998 if (!is_zero_ether_addr((const u8 *)conf->mac)) { 1999 reg = le32_to_cpu(conf->mac[1]); 2000 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 2001 conf->mac[1] = cpu_to_le32(reg); 2002 } 2003 2004 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 2005 conf->mac, sizeof(conf->mac)); 2006 } 2007 2008 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { 2009 if (!is_zero_ether_addr((const u8 *)conf->bssid)) { 2010 reg = le32_to_cpu(conf->bssid[1]); 2011 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); 2012 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); 2013 conf->bssid[1] = cpu_to_le32(reg); 2014 } 2015 2016 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 2017 conf->bssid, sizeof(conf->bssid)); 2018 } 2019} 2020EXPORT_SYMBOL_GPL(rt2800_config_intf); 2021 2022static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, 2023 struct rt2x00lib_erp *erp) 2024{ 2025 bool any_sta_nongf = !!(erp->ht_opmode & 2026 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 2027 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; 2028 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; 2029 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; 2030 u32 reg; 2031 2032 /* default protection rate for HT20: OFDM 24M */ 2033 mm20_rate = gf20_rate = 0x4004; 2034 2035 /* default protection rate for HT40: duplicate OFDM 24M */ 2036 mm40_rate = gf40_rate = 0x4084; 2037 2038 switch (protection) { 2039 case IEEE80211_HT_OP_MODE_PROTECTION_NONE: 2040 /* 2041 * All STAs in this BSS are HT20/40 but there might be 2042 * STAs not supporting greenfield mode. 2043 * => Disable protection for HT transmissions. 2044 */ 2045 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; 2046 2047 break; 2048 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 2049 /* 2050 * All STAs in this BSS are HT20 or HT20/40 but there 2051 * might be STAs not supporting greenfield mode. 2052 * => Protect all HT40 transmissions. 2053 */ 2054 mm20_mode = gf20_mode = 0; 2055 mm40_mode = gf40_mode = 1; 2056 2057 break; 2058 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 2059 /* 2060 * Nonmember protection: 2061 * According to 802.11n we _should_ protect all 2062 * HT transmissions (but we don't have to). 2063 * 2064 * But if cts_protection is enabled we _shall_ protect 2065 * all HT transmissions using a CCK rate. 2066 * 2067 * And if any station is non GF we _shall_ protect 2068 * GF transmissions. 2069 * 2070 * We decide to protect everything 2071 * -> fall through to mixed mode. 2072 */ 2073 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 2074 /* 2075 * Legacy STAs are present 2076 * => Protect all HT transmissions. 2077 */ 2078 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1; 2079 2080 /* 2081 * If erp protection is needed we have to protect HT 2082 * transmissions with CCK 11M long preamble. 2083 */ 2084 if (erp->cts_protection) { 2085 /* don't duplicate RTS/CTS in CCK mode */ 2086 mm20_rate = mm40_rate = 0x0003; 2087 gf20_rate = gf40_rate = 0x0003; 2088 } 2089 break; 2090 } 2091 2092 /* check for STAs not supporting greenfield mode */ 2093 if (any_sta_nongf) 2094 gf20_mode = gf40_mode = 1; 2095 2096 /* Update HT protection config */ 2097 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 2098 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); 2099 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); 2100 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 2101 2102 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 2103 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); 2104 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); 2105 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 2106 2107 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 2108 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); 2109 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); 2110 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 2111 2112 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 2113 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); 2114 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); 2115 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 2116} 2117 2118void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, 2119 u32 changed) 2120{ 2121 u32 reg; 2122 2123 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 2124 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 2125 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 2126 !!erp->short_preamble); 2127 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 2128 } 2129 2130 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 2131 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 2132 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 2133 erp->cts_protection ? 2 : 0); 2134 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 2135 } 2136 2137 if (changed & BSS_CHANGED_BASIC_RATES) { 2138 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 2139 0xff0 | erp->basic_rates); 2140 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 2141 } 2142 2143 if (changed & BSS_CHANGED_ERP_SLOT) { 2144 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 2145 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 2146 erp->slot_time); 2147 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 2148 2149 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 2150 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); 2151 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 2152 } 2153 2154 if (changed & BSS_CHANGED_BEACON_INT) { 2155 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 2156 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 2157 erp->beacon_int * 16); 2158 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 2159 } 2160 2161 if (changed & BSS_CHANGED_HT) 2162 rt2800_config_ht_opmode(rt2x00dev, erp); 2163} 2164EXPORT_SYMBOL_GPL(rt2800_config_erp); 2165 2166static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev, 2167 const struct rt2x00_field32 mask) 2168{ 2169 unsigned int i; 2170 u32 reg; 2171 2172 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 2173 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 2174 if (!rt2x00_get_field32(reg, mask)) 2175 return 0; 2176 2177 udelay(REGISTER_BUSY_DELAY); 2178 } 2179 2180 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n"); 2181 return -EACCES; 2182} 2183 2184static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 2185{ 2186 unsigned int i; 2187 u8 value; 2188 2189 /* 2190 * BBP was enabled after firmware was loaded, 2191 * but we need to reactivate it now. 2192 */ 2193 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 2194 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 2195 msleep(1); 2196 2197 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 2198 value = rt2800_bbp_read(rt2x00dev, 0); 2199 if ((value != 0xff) && (value != 0x00)) 2200 return 0; 2201 udelay(REGISTER_BUSY_DELAY); 2202 } 2203 2204 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 2205 return -EACCES; 2206} 2207 2208static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) 2209{ 2210 u32 reg; 2211 u16 eeprom; 2212 u8 led_ctrl, led_g_mode, led_r_mode; 2213 2214 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 2215 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 2216 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); 2217 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); 2218 } else { 2219 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); 2220 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); 2221 } 2222 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 2223 2224 reg = rt2800_register_read(rt2x00dev, LED_CFG); 2225 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; 2226 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; 2227 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || 2228 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { 2229 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 2230 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); 2231 if (led_ctrl == 0 || led_ctrl > 0x40) { 2232 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); 2233 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); 2234 rt2800_register_write(rt2x00dev, LED_CFG, reg); 2235 } else { 2236 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, 2237 (led_g_mode << 2) | led_r_mode, 1); 2238 } 2239 } 2240} 2241 2242static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, 2243 enum antenna ant) 2244{ 2245 u32 reg; 2246 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; 2247 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; 2248 2249 if (rt2x00_is_pci(rt2x00dev)) { 2250 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR); 2251 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); 2252 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 2253 } else if (rt2x00_is_usb(rt2x00dev)) 2254 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, 2255 eesk_pin, 0); 2256 2257 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2258 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 2259 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); 2260 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2261} 2262 2263void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 2264{ 2265 u8 r1; 2266 u8 r3; 2267 u16 eeprom; 2268 2269 r1 = rt2800_bbp_read(rt2x00dev, 1); 2270 r3 = rt2800_bbp_read(rt2x00dev, 3); 2271 2272 if (rt2x00_rt(rt2x00dev, RT3572) && 2273 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2274 rt2800_config_3572bt_ant(rt2x00dev); 2275 2276 /* 2277 * Configure the TX antenna. 2278 */ 2279 switch (ant->tx_chain_num) { 2280 case 1: 2281 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 2282 break; 2283 case 2: 2284 if (rt2x00_rt(rt2x00dev, RT3572) && 2285 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2286 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); 2287 else 2288 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2289 break; 2290 case 3: 2291 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2292 break; 2293 } 2294 2295 /* 2296 * Configure the RX antenna. 2297 */ 2298 switch (ant->rx_chain_num) { 2299 case 1: 2300 if (rt2x00_rt(rt2x00dev, RT3070) || 2301 rt2x00_rt(rt2x00dev, RT3090) || 2302 rt2x00_rt(rt2x00dev, RT3352) || 2303 rt2x00_rt(rt2x00dev, RT3390)) { 2304 eeprom = rt2800_eeprom_read(rt2x00dev, 2305 EEPROM_NIC_CONF1); 2306 if (rt2x00_get_field16(eeprom, 2307 EEPROM_NIC_CONF1_ANT_DIVERSITY)) 2308 rt2800_set_ant_diversity(rt2x00dev, 2309 rt2x00dev->default_ant.rx); 2310 } 2311 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 2312 break; 2313 case 2: 2314 if (rt2x00_rt(rt2x00dev, RT3572) && 2315 rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2316 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); 2317 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2318 rt2x00dev->curr_band == NL80211_BAND_5GHZ); 2319 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); 2320 } else { 2321 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 2322 } 2323 break; 2324 case 3: 2325 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 2326 break; 2327 } 2328 2329 rt2800_bbp_write(rt2x00dev, 3, r3); 2330 rt2800_bbp_write(rt2x00dev, 1, r1); 2331 2332 if (rt2x00_rt(rt2x00dev, RT3593) || 2333 rt2x00_rt(rt2x00dev, RT3883)) { 2334 if (ant->rx_chain_num == 1) 2335 rt2800_bbp_write(rt2x00dev, 86, 0x00); 2336 else 2337 rt2800_bbp_write(rt2x00dev, 86, 0x46); 2338 } 2339} 2340EXPORT_SYMBOL_GPL(rt2800_config_ant); 2341 2342static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, 2343 struct rt2x00lib_conf *libconf) 2344{ 2345 u16 eeprom; 2346 short lna_gain; 2347 2348 if (libconf->rf.channel <= 14) { 2349 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2350 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); 2351 } else if (libconf->rf.channel <= 64) { 2352 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2353 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); 2354 } else if (libconf->rf.channel <= 128) { 2355 if (rt2x00_rt(rt2x00dev, RT3593) || 2356 rt2x00_rt(rt2x00dev, RT3883)) { 2357 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2358 lna_gain = rt2x00_get_field16(eeprom, 2359 EEPROM_EXT_LNA2_A1); 2360 } else { 2361 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 2362 lna_gain = rt2x00_get_field16(eeprom, 2363 EEPROM_RSSI_BG2_LNA_A1); 2364 } 2365 } else { 2366 if (rt2x00_rt(rt2x00dev, RT3593) || 2367 rt2x00_rt(rt2x00dev, RT3883)) { 2368 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2369 lna_gain = rt2x00_get_field16(eeprom, 2370 EEPROM_EXT_LNA2_A2); 2371 } else { 2372 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 2373 lna_gain = rt2x00_get_field16(eeprom, 2374 EEPROM_RSSI_A2_LNA_A2); 2375 } 2376 } 2377 2378 rt2x00dev->lna_gain = lna_gain; 2379} 2380 2381static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev) 2382{ 2383 return clk_get_rate(rt2x00dev->clk) == 20000000; 2384} 2385 2386#define FREQ_OFFSET_BOUND 0x5f 2387 2388static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev) 2389{ 2390 u8 freq_offset, prev_freq_offset; 2391 u8 rfcsr, prev_rfcsr; 2392 2393 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); 2394 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); 2395 2396 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 2397 prev_rfcsr = rfcsr; 2398 2399 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); 2400 if (rfcsr == prev_rfcsr) 2401 return; 2402 2403 if (rt2x00_is_usb(rt2x00dev)) { 2404 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff, 2405 freq_offset, prev_rfcsr); 2406 return; 2407 } 2408 2409 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE); 2410 while (prev_freq_offset != freq_offset) { 2411 if (prev_freq_offset < freq_offset) 2412 prev_freq_offset++; 2413 else 2414 prev_freq_offset--; 2415 2416 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset); 2417 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 2418 2419 usleep_range(1000, 1500); 2420 } 2421} 2422 2423static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, 2424 struct ieee80211_conf *conf, 2425 struct rf_channel *rf, 2426 struct channel_info *info) 2427{ 2428 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 2429 2430 if (rt2x00dev->default_ant.tx_chain_num == 1) 2431 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 2432 2433 if (rt2x00dev->default_ant.rx_chain_num == 1) { 2434 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 2435 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2436 } else if (rt2x00dev->default_ant.rx_chain_num == 2) 2437 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2438 2439 if (rf->channel > 14) { 2440 /* 2441 * When TX power is below 0, we should increase it by 7 to 2442 * make it a positive value (Minimum value is -7). 2443 * However this means that values between 0 and 7 have 2444 * double meaning, and we should set a 7DBm boost flag. 2445 */ 2446 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 2447 (info->default_power1 >= 0)); 2448 2449 if (info->default_power1 < 0) 2450 info->default_power1 += 7; 2451 2452 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); 2453 2454 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 2455 (info->default_power2 >= 0)); 2456 2457 if (info->default_power2 < 0) 2458 info->default_power2 += 7; 2459 2460 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); 2461 } else { 2462 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); 2463 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); 2464 } 2465 2466 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 2467 2468 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2469 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2470 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2471 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2472 2473 udelay(200); 2474 2475 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2476 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2477 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 2478 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2479 2480 udelay(200); 2481 2482 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2483 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2484 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2485 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2486} 2487 2488static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, 2489 struct ieee80211_conf *conf, 2490 struct rf_channel *rf, 2491 struct channel_info *info) 2492{ 2493 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2494 u8 rfcsr, calib_tx, calib_rx; 2495 2496 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2497 2498 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2499 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); 2500 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2501 2502 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2503 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2504 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2505 2506 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2507 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); 2508 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2509 2510 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2511 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); 2512 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2513 2514 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2515 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2516 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2517 rt2x00dev->default_ant.rx_chain_num <= 1); 2518 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 2519 rt2x00dev->default_ant.rx_chain_num <= 2); 2520 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2521 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2522 rt2x00dev->default_ant.tx_chain_num <= 1); 2523 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 2524 rt2x00dev->default_ant.tx_chain_num <= 2); 2525 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2526 2527 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2528 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2529 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2530 2531 if (rt2x00_rt(rt2x00dev, RT3390)) { 2532 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; 2533 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; 2534 } else { 2535 if (conf_is_ht40(conf)) { 2536 calib_tx = drv_data->calibration_bw40; 2537 calib_rx = drv_data->calibration_bw40; 2538 } else { 2539 calib_tx = drv_data->calibration_bw20; 2540 calib_rx = drv_data->calibration_bw20; 2541 } 2542 } 2543 2544 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24); 2545 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); 2546 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); 2547 2548 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 2549 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); 2550 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2551 2552 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2553 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2554 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2555 2556 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2557 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2558 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2559 2560 usleep_range(1000, 1500); 2561 2562 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2563 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2564} 2565 2566static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, 2567 struct ieee80211_conf *conf, 2568 struct rf_channel *rf, 2569 struct channel_info *info) 2570{ 2571 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2572 u8 rfcsr; 2573 u32 reg; 2574 2575 if (rf->channel <= 14) { 2576 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2577 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2578 } else { 2579 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2580 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2581 } 2582 2583 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2584 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 2585 2586 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2587 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2588 if (rf->channel <= 14) 2589 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); 2590 else 2591 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); 2592 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2593 2594 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5); 2595 if (rf->channel <= 14) 2596 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); 2597 else 2598 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); 2599 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); 2600 2601 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2602 if (rf->channel <= 14) { 2603 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); 2604 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2605 info->default_power1); 2606 } else { 2607 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); 2608 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2609 (info->default_power1 & 0x3) | 2610 ((info->default_power1 & 0xC) << 1)); 2611 } 2612 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2613 2614 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2615 if (rf->channel <= 14) { 2616 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); 2617 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2618 info->default_power2); 2619 } else { 2620 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); 2621 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2622 (info->default_power2 & 0x3) | 2623 ((info->default_power2 & 0xC) << 1)); 2624 } 2625 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2626 2627 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2628 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2629 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2630 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2631 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2632 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2633 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2634 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2635 if (rf->channel <= 14) { 2636 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2637 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2638 } 2639 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2640 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2641 } else { 2642 switch (rt2x00dev->default_ant.tx_chain_num) { 2643 case 1: 2644 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2645 fallthrough; 2646 case 2: 2647 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2648 break; 2649 } 2650 2651 switch (rt2x00dev->default_ant.rx_chain_num) { 2652 case 1: 2653 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2654 fallthrough; 2655 case 2: 2656 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2657 break; 2658 } 2659 } 2660 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2661 2662 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2663 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2664 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2665 2666 if (conf_is_ht40(conf)) { 2667 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40); 2668 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40); 2669 } else { 2670 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20); 2671 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20); 2672 } 2673 2674 if (rf->channel <= 14) { 2675 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 2676 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 2677 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2678 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 2679 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 2680 rfcsr = 0x4c; 2681 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2682 drv_data->txmixer_gain_24g); 2683 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2684 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2685 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 2686 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 2687 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 2688 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 2689 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 2690 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 2691 } else { 2692 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2693 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); 2694 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); 2695 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); 2696 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0); 2697 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2698 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 2699 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2700 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 2701 rt2800_rfcsr_write(rt2x00dev, 15, 0x43); 2702 rfcsr = 0x7a; 2703 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2704 drv_data->txmixer_gain_5g); 2705 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2706 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2707 if (rf->channel <= 64) { 2708 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); 2709 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); 2710 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 2711 } else if (rf->channel <= 128) { 2712 rt2800_rfcsr_write(rt2x00dev, 19, 0x74); 2713 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); 2714 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2715 } else { 2716 rt2800_rfcsr_write(rt2x00dev, 19, 0x72); 2717 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); 2718 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2719 } 2720 rt2800_rfcsr_write(rt2x00dev, 26, 0x87); 2721 rt2800_rfcsr_write(rt2x00dev, 27, 0x01); 2722 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); 2723 } 2724 2725 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2726 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 2727 if (rf->channel <= 14) 2728 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 2729 else 2730 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); 2731 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2732 2733 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2734 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2735 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2736} 2737 2738static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, 2739 struct ieee80211_conf *conf, 2740 struct rf_channel *rf, 2741 struct channel_info *info) 2742{ 2743 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2744 u8 txrx_agc_fc; 2745 u8 txrx_h20m; 2746 u8 rfcsr; 2747 u8 bbp; 2748 const bool txbf_enabled = false; /* TODO */ 2749 2750 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ 2751 bbp = rt2800_bbp_read(rt2x00dev, 109); 2752 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); 2753 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); 2754 rt2800_bbp_write(rt2x00dev, 109, bbp); 2755 2756 bbp = rt2800_bbp_read(rt2x00dev, 110); 2757 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); 2758 rt2800_bbp_write(rt2x00dev, 110, bbp); 2759 2760 if (rf->channel <= 14) { 2761 /* Restore BBP 25 & 26 for 2.4 GHz */ 2762 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2763 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2764 } else { 2765 /* Hard code BBP 25 & 26 for 5GHz */ 2766 2767 /* Enable IQ Phase correction */ 2768 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2769 /* Setup IQ Phase correction value */ 2770 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2771 } 2772 2773 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2774 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); 2775 2776 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2777 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); 2778 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2779 2780 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2781 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); 2782 if (rf->channel <= 14) 2783 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); 2784 else 2785 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); 2786 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2787 2788 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53); 2789 if (rf->channel <= 14) { 2790 rfcsr = 0; 2791 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2792 info->default_power1 & 0x1f); 2793 } else { 2794 if (rt2x00_is_usb(rt2x00dev)) 2795 rfcsr = 0x40; 2796 2797 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2798 ((info->default_power1 & 0x18) << 1) | 2799 (info->default_power1 & 7)); 2800 } 2801 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); 2802 2803 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55); 2804 if (rf->channel <= 14) { 2805 rfcsr = 0; 2806 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2807 info->default_power2 & 0x1f); 2808 } else { 2809 if (rt2x00_is_usb(rt2x00dev)) 2810 rfcsr = 0x40; 2811 2812 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2813 ((info->default_power2 & 0x18) << 1) | 2814 (info->default_power2 & 7)); 2815 } 2816 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); 2817 2818 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54); 2819 if (rf->channel <= 14) { 2820 rfcsr = 0; 2821 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2822 info->default_power3 & 0x1f); 2823 } else { 2824 if (rt2x00_is_usb(rt2x00dev)) 2825 rfcsr = 0x40; 2826 2827 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2828 ((info->default_power3 & 0x18) << 1) | 2829 (info->default_power3 & 7)); 2830 } 2831 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); 2832 2833 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2834 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2835 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2836 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2837 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2838 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2839 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2840 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2841 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2842 2843 switch (rt2x00dev->default_ant.tx_chain_num) { 2844 case 3: 2845 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2846 fallthrough; 2847 case 2: 2848 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2849 fallthrough; 2850 case 1: 2851 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2852 break; 2853 } 2854 2855 switch (rt2x00dev->default_ant.rx_chain_num) { 2856 case 3: 2857 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2858 fallthrough; 2859 case 2: 2860 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2861 fallthrough; 2862 case 1: 2863 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2864 break; 2865 } 2866 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2867 2868 rt2800_freq_cal_mode1(rt2x00dev); 2869 2870 if (conf_is_ht40(conf)) { 2871 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, 2872 RFCSR24_TX_AGC_FC); 2873 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40, 2874 RFCSR24_TX_H20M); 2875 } else { 2876 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20, 2877 RFCSR24_TX_AGC_FC); 2878 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20, 2879 RFCSR24_TX_H20M); 2880 } 2881 2882 /* NOTE: the reference driver does not writes the new value 2883 * back to RFCSR 32 2884 */ 2885 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32); 2886 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); 2887 2888 if (rf->channel <= 14) 2889 rfcsr = 0xa0; 2890 else 2891 rfcsr = 0x80; 2892 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2893 2894 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2895 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); 2896 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); 2897 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2898 2899 /* Band selection */ 2900 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 2901 if (rf->channel <= 14) 2902 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 2903 else 2904 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 2905 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 2906 2907 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34); 2908 if (rf->channel <= 14) 2909 rfcsr = 0x3c; 2910 else 2911 rfcsr = 0x20; 2912 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 2913 2914 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2915 if (rf->channel <= 14) 2916 rfcsr = 0x1a; 2917 else 2918 rfcsr = 0x12; 2919 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2920 2921 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2922 if (rf->channel >= 1 && rf->channel <= 14) 2923 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2924 else if (rf->channel >= 36 && rf->channel <= 64) 2925 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2926 else if (rf->channel >= 100 && rf->channel <= 128) 2927 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2928 else 2929 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2930 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2931 2932 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2933 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 2934 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2935 2936 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 2937 2938 if (rf->channel <= 14) { 2939 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 2940 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2941 } else { 2942 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8); 2943 rt2800_rfcsr_write(rt2x00dev, 13, 0x23); 2944 } 2945 2946 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2947 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); 2948 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2949 2950 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2951 if (rf->channel <= 14) { 2952 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); 2953 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); 2954 } else { 2955 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4); 2956 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2); 2957 } 2958 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2959 2960 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2961 if (rf->channel <= 14) 2962 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); 2963 else 2964 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2); 2965 2966 if (txbf_enabled) 2967 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1); 2968 2969 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2970 2971 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 2972 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); 2973 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2974 2975 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 2976 if (rf->channel <= 14) 2977 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); 2978 else 2979 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f); 2980 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr); 2981 2982 if (rf->channel <= 14) { 2983 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 2984 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 2985 } else { 2986 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 2987 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 2988 } 2989 2990 /* Initiate VCO calibration */ 2991 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2992 if (rf->channel <= 14) { 2993 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2994 } else { 2995 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1); 2996 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1); 2997 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1); 2998 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1); 2999 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1); 3000 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3001 } 3002 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3003 3004 if (rf->channel >= 1 && rf->channel <= 14) { 3005 rfcsr = 0x23; 3006 if (txbf_enabled) 3007 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3008 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3009 3010 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 3011 } else if (rf->channel >= 36 && rf->channel <= 64) { 3012 rfcsr = 0x36; 3013 if (txbf_enabled) 3014 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3015 rt2800_rfcsr_write(rt2x00dev, 39, 0x36); 3016 3017 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb); 3018 } else if (rf->channel >= 100 && rf->channel <= 128) { 3019 rfcsr = 0x32; 3020 if (txbf_enabled) 3021 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3022 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3023 3024 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3); 3025 } else { 3026 rfcsr = 0x30; 3027 if (txbf_enabled) 3028 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 3029 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3030 3031 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b); 3032 } 3033} 3034 3035static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev, 3036 struct ieee80211_conf *conf, 3037 struct rf_channel *rf, 3038 struct channel_info *info) 3039{ 3040 u8 rfcsr; 3041 u8 bbp; 3042 u8 pwr1, pwr2, pwr3; 3043 3044 const bool txbf_enabled = false; /* TODO */ 3045 3046 /* TODO: add band selection */ 3047 3048 if (rf->channel <= 14) 3049 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 3050 else if (rf->channel < 132) 3051 rt2800_rfcsr_write(rt2x00dev, 6, 0x80); 3052 else 3053 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 3054 3055 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3056 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3057 3058 if (rf->channel <= 14) 3059 rt2800_rfcsr_write(rt2x00dev, 11, 0x46); 3060 else 3061 rt2800_rfcsr_write(rt2x00dev, 11, 0x48); 3062 3063 if (rf->channel <= 14) 3064 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a); 3065 else 3066 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 3067 3068 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 3069 3070 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3071 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 3072 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 3073 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 3074 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 3075 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3076 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3077 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3078 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3079 3080 switch (rt2x00dev->default_ant.tx_chain_num) { 3081 case 3: 3082 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 3083 fallthrough; 3084 case 2: 3085 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3086 fallthrough; 3087 case 1: 3088 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3089 break; 3090 } 3091 3092 switch (rt2x00dev->default_ant.rx_chain_num) { 3093 case 3: 3094 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 3095 fallthrough; 3096 case 2: 3097 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3098 fallthrough; 3099 case 1: 3100 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3101 break; 3102 } 3103 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3104 3105 rt2800_freq_cal_mode1(rt2x00dev); 3106 3107 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 3108 if (!conf_is_ht40(conf)) 3109 rfcsr &= ~(0x06); 3110 else 3111 rfcsr |= 0x06; 3112 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3113 3114 if (rf->channel <= 14) 3115 rt2800_rfcsr_write(rt2x00dev, 31, 0xa0); 3116 else 3117 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3118 3119 if (conf_is_ht40(conf)) 3120 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3121 else 3122 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8); 3123 3124 if (rf->channel <= 14) 3125 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 3126 else 3127 rt2800_rfcsr_write(rt2x00dev, 34, 0x20); 3128 3129 /* loopback RF_BS */ 3130 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 3131 if (rf->channel <= 14) 3132 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 3133 else 3134 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 3135 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 3136 3137 if (rf->channel <= 14) 3138 rfcsr = 0x23; 3139 else if (rf->channel < 100) 3140 rfcsr = 0x36; 3141 else if (rf->channel < 132) 3142 rfcsr = 0x32; 3143 else 3144 rfcsr = 0x30; 3145 3146 if (txbf_enabled) 3147 rfcsr |= 0x40; 3148 3149 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3150 3151 if (rf->channel <= 14) 3152 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 3153 else 3154 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 3155 3156 if (rf->channel <= 14) 3157 rfcsr = 0xbb; 3158 else if (rf->channel < 100) 3159 rfcsr = 0xeb; 3160 else if (rf->channel < 132) 3161 rfcsr = 0xb3; 3162 else 3163 rfcsr = 0x9b; 3164 rt2800_rfcsr_write(rt2x00dev, 45, rfcsr); 3165 3166 if (rf->channel <= 14) 3167 rfcsr = 0x8e; 3168 else 3169 rfcsr = 0x8a; 3170 3171 if (txbf_enabled) 3172 rfcsr |= 0x20; 3173 3174 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3175 3176 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 3177 3178 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 3179 if (rf->channel <= 14) 3180 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 3181 else 3182 rt2800_rfcsr_write(rt2x00dev, 51, 0x51); 3183 3184 rfcsr = rt2800_rfcsr_read(rt2x00dev, 52); 3185 if (rf->channel <= 14) 3186 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 3187 else 3188 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 3189 3190 if (rf->channel <= 14) { 3191 pwr1 = info->default_power1 & 0x1f; 3192 pwr2 = info->default_power2 & 0x1f; 3193 pwr3 = info->default_power3 & 0x1f; 3194 } else { 3195 pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) | 3196 (info->default_power1 & 0x7); 3197 pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) | 3198 (info->default_power2 & 0x7); 3199 pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) | 3200 (info->default_power3 & 0x7); 3201 } 3202 3203 rt2800_rfcsr_write(rt2x00dev, 53, pwr1); 3204 rt2800_rfcsr_write(rt2x00dev, 54, pwr2); 3205 rt2800_rfcsr_write(rt2x00dev, 55, pwr3); 3206 3207 rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n", 3208 rf->channel, pwr1, pwr2, pwr3); 3209 3210 bbp = (info->default_power1 >> 5) | 3211 ((info->default_power2 & 0xe0) >> 1); 3212 rt2800_bbp_write(rt2x00dev, 109, bbp); 3213 3214 bbp = rt2800_bbp_read(rt2x00dev, 110); 3215 bbp &= 0x0f; 3216 bbp |= (info->default_power3 & 0xe0) >> 1; 3217 rt2800_bbp_write(rt2x00dev, 110, bbp); 3218 3219 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 3220 if (rf->channel <= 14) 3221 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 3222 else 3223 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e); 3224 3225 /* Enable RF tuning */ 3226 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3227 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3228 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3229 3230 udelay(2000); 3231 3232 bbp = rt2800_bbp_read(rt2x00dev, 49); 3233 /* clear update flag */ 3234 rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe); 3235 rt2800_bbp_write(rt2x00dev, 49, bbp); 3236 3237 /* TODO: add calibration for TxBF */ 3238} 3239 3240#define POWER_BOUND 0x27 3241#define POWER_BOUND_5G 0x2b 3242 3243static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, 3244 struct ieee80211_conf *conf, 3245 struct rf_channel *rf, 3246 struct channel_info *info) 3247{ 3248 u8 rfcsr; 3249 3250 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3251 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3252 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3253 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 3254 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3255 3256 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3257 if (info->default_power1 > POWER_BOUND) 3258 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 3259 else 3260 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3261 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3262 3263 rt2800_freq_cal_mode1(rt2x00dev); 3264 3265 if (rf->channel <= 14) { 3266 if (rf->channel == 6) 3267 rt2800_bbp_write(rt2x00dev, 68, 0x0c); 3268 else 3269 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 3270 3271 if (rf->channel >= 1 && rf->channel <= 6) 3272 rt2800_bbp_write(rt2x00dev, 59, 0x0f); 3273 else if (rf->channel >= 7 && rf->channel <= 11) 3274 rt2800_bbp_write(rt2x00dev, 59, 0x0e); 3275 else if (rf->channel >= 12 && rf->channel <= 14) 3276 rt2800_bbp_write(rt2x00dev, 59, 0x0d); 3277 } 3278} 3279 3280static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, 3281 struct ieee80211_conf *conf, 3282 struct rf_channel *rf, 3283 struct channel_info *info) 3284{ 3285 u8 rfcsr; 3286 3287 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3288 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3289 3290 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 3291 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 3292 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 3293 3294 if (info->default_power1 > POWER_BOUND) 3295 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND); 3296 else 3297 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1); 3298 3299 if (info->default_power2 > POWER_BOUND) 3300 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND); 3301 else 3302 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); 3303 3304 rt2800_freq_cal_mode1(rt2x00dev); 3305 3306 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3307 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3308 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3309 3310 if ( rt2x00dev->default_ant.tx_chain_num == 2 ) 3311 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3312 else 3313 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 3314 3315 if ( rt2x00dev->default_ant.rx_chain_num == 2 ) 3316 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3317 else 3318 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 3319 3320 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3321 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3322 3323 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3324 3325 rt2800_rfcsr_write(rt2x00dev, 31, 80); 3326} 3327 3328static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 3329 struct ieee80211_conf *conf, 3330 struct rf_channel *rf, 3331 struct channel_info *info) 3332{ 3333 u8 rfcsr; 3334 int idx = rf->channel-1; 3335 3336 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3337 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3338 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3339 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 3340 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3341 3342 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3343 if (info->default_power1 > POWER_BOUND) 3344 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 3345 else 3346 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3347 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3348 3349 if (rt2x00_rt(rt2x00dev, RT5392)) { 3350 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3351 if (info->default_power2 > POWER_BOUND) 3352 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); 3353 else 3354 rt2x00_set_field8(&rfcsr, RFCSR50_TX, 3355 info->default_power2); 3356 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3357 } 3358 3359 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3360 if (rt2x00_rt(rt2x00dev, RT5392)) { 3361 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3362 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3363 } 3364 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3365 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3366 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3367 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3368 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3369 3370 rt2800_freq_cal_mode1(rt2x00dev); 3371 3372 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 3373 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3374 /* r55/r59 value array of channel 1~14 */ 3375 static const u8 r55_bt_rev[] = {0x83, 0x83, 3376 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, 3377 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; 3378 static const u8 r59_bt_rev[] = {0x0e, 0x0e, 3379 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, 3380 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; 3381 3382 rt2800_rfcsr_write(rt2x00dev, 55, 3383 r55_bt_rev[idx]); 3384 rt2800_rfcsr_write(rt2x00dev, 59, 3385 r59_bt_rev[idx]); 3386 } else { 3387 static const u8 r59_bt[] = {0x8b, 0x8b, 0x8b, 3388 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, 3389 0x88, 0x88, 0x86, 0x85, 0x84}; 3390 3391 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); 3392 } 3393 } else { 3394 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3395 static const u8 r55_nonbt_rev[] = {0x23, 0x23, 3396 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, 3397 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; 3398 static const u8 r59_nonbt_rev[] = {0x07, 0x07, 3399 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 3400 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; 3401 3402 rt2800_rfcsr_write(rt2x00dev, 55, 3403 r55_nonbt_rev[idx]); 3404 rt2800_rfcsr_write(rt2x00dev, 59, 3405 r59_nonbt_rev[idx]); 3406 } else if (rt2x00_rt(rt2x00dev, RT5390) || 3407 rt2x00_rt(rt2x00dev, RT5392) || 3408 rt2x00_rt(rt2x00dev, RT6352)) { 3409 static const u8 r59_non_bt[] = {0x8f, 0x8f, 3410 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 3411 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; 3412 3413 rt2800_rfcsr_write(rt2x00dev, 59, 3414 r59_non_bt[idx]); 3415 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 3416 static const u8 r59_non_bt[] = {0x0b, 0x0b, 3417 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a, 3418 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06}; 3419 3420 rt2800_rfcsr_write(rt2x00dev, 59, 3421 r59_non_bt[idx]); 3422 } 3423 } 3424} 3425 3426static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, 3427 struct ieee80211_conf *conf, 3428 struct rf_channel *rf, 3429 struct channel_info *info) 3430{ 3431 u8 rfcsr, ep_reg; 3432 u32 reg; 3433 int power_bound; 3434 3435 /* TODO */ 3436 const bool is_11b = false; 3437 const bool is_type_ep = false; 3438 3439 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 3440 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3441 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); 3442 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 3443 3444 /* Order of values on rf_channel entry: N, K, mod, R */ 3445 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); 3446 3447 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9); 3448 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); 3449 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); 3450 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); 3451 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); 3452 3453 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3454 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); 3455 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); 3456 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3457 3458 if (rf->channel <= 14) { 3459 rt2800_rfcsr_write(rt2x00dev, 10, 0x90); 3460 /* FIXME: RF11 owerwrite ? */ 3461 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A); 3462 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 3463 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3464 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3465 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A); 3466 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 3467 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3468 rt2800_rfcsr_write(rt2x00dev, 36, 0x80); 3469 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 3470 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 3471 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B); 3472 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D); 3473 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B); 3474 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5); 3475 rt2800_rfcsr_write(rt2x00dev, 43, 0x72); 3476 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E); 3477 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2); 3478 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B); 3479 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 3480 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E); 3481 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 3482 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 3483 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1); 3484 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 3485 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 3486 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 3487 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 3488 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 3489 3490 /* TODO RF27 <- tssi */ 3491 3492 rfcsr = rf->channel <= 10 ? 0x07 : 0x06; 3493 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 3494 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr); 3495 3496 if (is_11b) { 3497 /* CCK */ 3498 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8); 3499 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0); 3500 if (is_type_ep) 3501 rt2800_rfcsr_write(rt2x00dev, 55, 0x06); 3502 else 3503 rt2800_rfcsr_write(rt2x00dev, 55, 0x47); 3504 } else { 3505 /* OFDM */ 3506 if (is_type_ep) 3507 rt2800_rfcsr_write(rt2x00dev, 55, 0x03); 3508 else 3509 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 3510 } 3511 3512 power_bound = POWER_BOUND; 3513 ep_reg = 0x2; 3514 } else { 3515 rt2800_rfcsr_write(rt2x00dev, 10, 0x97); 3516 /* FIMXE: RF11 overwrite */ 3517 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 3518 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF); 3519 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3520 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 3521 rt2800_rfcsr_write(rt2x00dev, 37, 0x04); 3522 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 3523 rt2800_rfcsr_write(rt2x00dev, 40, 0x42); 3524 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB); 3525 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7); 3526 rt2800_rfcsr_write(rt2x00dev, 45, 0x41); 3527 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 3528 rt2800_rfcsr_write(rt2x00dev, 57, 0x77); 3529 rt2800_rfcsr_write(rt2x00dev, 60, 0x05); 3530 rt2800_rfcsr_write(rt2x00dev, 61, 0x01); 3531 3532 /* TODO RF27 <- tssi */ 3533 3534 if (rf->channel >= 36 && rf->channel <= 64) { 3535 3536 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E); 3537 rt2800_rfcsr_write(rt2x00dev, 13, 0x22); 3538 rt2800_rfcsr_write(rt2x00dev, 22, 0x60); 3539 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F); 3540 if (rf->channel <= 50) 3541 rt2800_rfcsr_write(rt2x00dev, 24, 0x09); 3542 else if (rf->channel >= 52) 3543 rt2800_rfcsr_write(rt2x00dev, 24, 0x07); 3544 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C); 3545 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B); 3546 rt2800_rfcsr_write(rt2x00dev, 44, 0X40); 3547 rt2800_rfcsr_write(rt2x00dev, 46, 0X00); 3548 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE); 3549 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C); 3550 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8); 3551 if (rf->channel <= 50) { 3552 rt2800_rfcsr_write(rt2x00dev, 55, 0x06), 3553 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3); 3554 } else if (rf->channel >= 52) { 3555 rt2800_rfcsr_write(rt2x00dev, 55, 0x04); 3556 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3557 } 3558 3559 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3560 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F); 3561 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3562 3563 } else if (rf->channel >= 100 && rf->channel <= 165) { 3564 3565 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E); 3566 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3567 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3568 if (rf->channel <= 153) { 3569 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C); 3570 rt2800_rfcsr_write(rt2x00dev, 24, 0x06); 3571 } else if (rf->channel >= 155) { 3572 rt2800_rfcsr_write(rt2x00dev, 23, 0x38); 3573 rt2800_rfcsr_write(rt2x00dev, 24, 0x05); 3574 } 3575 if (rf->channel <= 138) { 3576 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A); 3577 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B); 3578 rt2800_rfcsr_write(rt2x00dev, 44, 0x20); 3579 rt2800_rfcsr_write(rt2x00dev, 46, 0x18); 3580 } else if (rf->channel >= 140) { 3581 rt2800_rfcsr_write(rt2x00dev, 39, 0x18); 3582 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B); 3583 rt2800_rfcsr_write(rt2x00dev, 44, 0x10); 3584 rt2800_rfcsr_write(rt2x00dev, 46, 0X08); 3585 } 3586 if (rf->channel <= 124) 3587 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC); 3588 else if (rf->channel >= 126) 3589 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC); 3590 if (rf->channel <= 138) 3591 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3592 else if (rf->channel >= 140) 3593 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3594 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB); 3595 if (rf->channel <= 138) 3596 rt2800_rfcsr_write(rt2x00dev, 55, 0x01); 3597 else if (rf->channel >= 140) 3598 rt2800_rfcsr_write(rt2x00dev, 55, 0x00); 3599 if (rf->channel <= 128) 3600 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3601 else if (rf->channel >= 130) 3602 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB); 3603 if (rf->channel <= 116) 3604 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D); 3605 else if (rf->channel >= 118) 3606 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3607 if (rf->channel <= 138) 3608 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F); 3609 else if (rf->channel >= 140) 3610 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C); 3611 if (rf->channel <= 116) 3612 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D); 3613 else if (rf->channel >= 118) 3614 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3615 } 3616 3617 power_bound = POWER_BOUND_5G; 3618 ep_reg = 0x3; 3619 } 3620 3621 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3622 if (info->default_power1 > power_bound) 3623 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); 3624 else 3625 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3626 if (is_type_ep) 3627 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); 3628 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3629 3630 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3631 if (info->default_power2 > power_bound) 3632 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); 3633 else 3634 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2); 3635 if (is_type_ep) 3636 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); 3637 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3638 3639 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3640 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3641 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3642 3643 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 3644 rt2x00dev->default_ant.tx_chain_num >= 1); 3645 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 3646 rt2x00dev->default_ant.tx_chain_num == 2); 3647 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3648 3649 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 3650 rt2x00dev->default_ant.rx_chain_num >= 1); 3651 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 3652 rt2x00dev->default_ant.rx_chain_num == 2); 3653 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3654 3655 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3656 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4); 3657 3658 if (conf_is_ht40(conf)) 3659 rt2800_rfcsr_write(rt2x00dev, 30, 0x16); 3660 else 3661 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 3662 3663 if (!is_11b) { 3664 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3665 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3666 } 3667 3668 /* TODO proper frequency adjustment */ 3669 rt2800_freq_cal_mode1(rt2x00dev); 3670 3671 /* TODO merge with others */ 3672 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3673 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3674 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3675 3676 /* BBP settings */ 3677 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3678 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3679 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3680 3681 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18); 3682 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08); 3683 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38); 3684 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92); 3685 3686 /* GLRT band configuration */ 3687 rt2800_bbp_write(rt2x00dev, 195, 128); 3688 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0); 3689 rt2800_bbp_write(rt2x00dev, 195, 129); 3690 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E); 3691 rt2800_bbp_write(rt2x00dev, 195, 130); 3692 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28); 3693 rt2800_bbp_write(rt2x00dev, 195, 131); 3694 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20); 3695 rt2800_bbp_write(rt2x00dev, 195, 133); 3696 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F); 3697 rt2800_bbp_write(rt2x00dev, 195, 124); 3698 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); 3699} 3700 3701static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev, 3702 struct ieee80211_conf *conf, 3703 struct rf_channel *rf, 3704 struct channel_info *info) 3705{ 3706 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 3707 u8 rx_agc_fc, tx_agc_fc; 3708 u8 rfcsr; 3709 3710 /* Frequeny plan setting */ 3711 /* Rdiv setting (set 0x03 if Xtal==20) 3712 * R13[1:0] 3713 */ 3714 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 3715 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620, 3716 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0); 3717 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 3718 3719 /* N setting 3720 * R20[7:0] in rf->rf1 3721 * R21[0] always 0 3722 */ 3723 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 3724 rfcsr = (rf->rf1 & 0x00ff); 3725 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 3726 3727 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3728 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0); 3729 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3730 3731 /* K setting (always 0) 3732 * R16[3:0] (RF PLL freq selection) 3733 */ 3734 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3735 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0); 3736 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3737 3738 /* D setting (always 0) 3739 * R22[2:0] (D=15, R22[2:0]=<111>) 3740 */ 3741 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 3742 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0); 3743 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 3744 3745 /* Ksd setting 3746 * Ksd: R17<7:0> in rf->rf2 3747 * R18<7:0> in rf->rf3 3748 * R19<1:0> in rf->rf4 3749 */ 3750 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 3751 rfcsr = rf->rf2; 3752 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 3753 3754 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 3755 rfcsr = rf->rf3; 3756 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 3757 3758 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19); 3759 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4); 3760 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr); 3761 3762 /* Default: XO=20MHz , SDM mode */ 3763 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3764 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80); 3765 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3766 3767 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3768 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1); 3769 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3770 3771 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3772 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620, 3773 rt2x00dev->default_ant.tx_chain_num != 1); 3774 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3775 3776 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 3777 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620, 3778 rt2x00dev->default_ant.tx_chain_num != 1); 3779 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620, 3780 rt2x00dev->default_ant.rx_chain_num != 1); 3781 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 3782 3783 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42); 3784 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620, 3785 rt2x00dev->default_ant.tx_chain_num != 1); 3786 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 3787 3788 /* RF for DC Cal BW */ 3789 if (conf_is_ht40(conf)) { 3790 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 3791 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 3792 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 3793 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 3794 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 3795 } else { 3796 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20); 3797 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20); 3798 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00); 3799 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20); 3800 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20); 3801 } 3802 3803 if (conf_is_ht40(conf)) { 3804 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08); 3805 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08); 3806 } else { 3807 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28); 3808 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28); 3809 } 3810 3811 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28); 3812 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40, 3813 conf_is_ht40(conf) && (rf->channel == 11)); 3814 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr); 3815 3816 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) { 3817 if (conf_is_ht40(conf)) { 3818 rx_agc_fc = drv_data->rx_calibration_bw40; 3819 tx_agc_fc = drv_data->tx_calibration_bw40; 3820 } else { 3821 rx_agc_fc = drv_data->rx_calibration_bw20; 3822 tx_agc_fc = drv_data->tx_calibration_bw20; 3823 } 3824 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 3825 rfcsr &= (~0x3F); 3826 rfcsr |= rx_agc_fc; 3827 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr); 3828 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 3829 rfcsr &= (~0x3F); 3830 rfcsr |= rx_agc_fc; 3831 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr); 3832 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6); 3833 rfcsr &= (~0x3F); 3834 rfcsr |= rx_agc_fc; 3835 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr); 3836 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7); 3837 rfcsr &= (~0x3F); 3838 rfcsr |= rx_agc_fc; 3839 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr); 3840 3841 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 3842 rfcsr &= (~0x3F); 3843 rfcsr |= tx_agc_fc; 3844 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr); 3845 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 3846 rfcsr &= (~0x3F); 3847 rfcsr |= tx_agc_fc; 3848 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr); 3849 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58); 3850 rfcsr &= (~0x3F); 3851 rfcsr |= tx_agc_fc; 3852 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr); 3853 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59); 3854 rfcsr &= (~0x3F); 3855 rfcsr |= tx_agc_fc; 3856 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr); 3857 } 3858 3859 if (conf_is_ht40(conf)) { 3860 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10); 3861 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f); 3862 } else { 3863 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a); 3864 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40); 3865 } 3866} 3867 3868static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev, 3869 struct ieee80211_channel *chan, 3870 int power_level) 3871{ 3872 int cur_channel = rt2x00dev->rf_channel; 3873 u16 eeprom, chan_power, rate_power, target_power; 3874 u16 tx_power[2]; 3875 s8 *power_group[2]; 3876 u32 mac_sys_ctrl; 3877 u32 cnt, reg; 3878 u8 bbp; 3879 3880 if (WARN_ON(cur_channel < 1 || cur_channel > 14)) 3881 return; 3882 3883 /* get per chain power, 2 chains in total, unit is 0.5dBm */ 3884 power_level = (power_level - 3) * 2; 3885 3886 /* We can't get the accurate TX power. Based on some tests, the real 3887 * TX power is approximately equal to channel_power + (max)rate_power. 3888 * Usually max rate_power is the gain of the OFDM 6M rate. The antenna 3889 * gain and externel PA gain are not included as we are unable to 3890 * obtain these values. 3891 */ 3892 rate_power = rt2800_eeprom_read_from_array(rt2x00dev, 3893 EEPROM_TXPOWER_BYRATE, 1); 3894 rate_power &= 0x3f; 3895 power_level -= rate_power; 3896 if (power_level < 1) 3897 power_level = 1; 3898 3899 power_group[0] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 3900 power_group[1] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 3901 for (cnt = 0; cnt < 2; cnt++) { 3902 chan_power = power_group[cnt][cur_channel - 1]; 3903 if (chan_power >= 0x20 || chan_power == 0) 3904 chan_power = 0x10; 3905 tx_power[cnt] = power_level < chan_power ? power_level : chan_power; 3906 } 3907 3908 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); 3909 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, tx_power[0]); 3910 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, tx_power[1]); 3911 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, 0x2f); 3912 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, 0x2f); 3913 3914 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 3915 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) { 3916 /* init base power by eeprom target power */ 3917 target_power = rt2800_eeprom_read(rt2x00dev, 3918 EEPROM_TXPOWER_INIT); 3919 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); 3920 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); 3921 } 3922 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg); 3923 3924 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 3925 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); 3926 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 3927 3928 /* Save MAC SYS CTRL registers */ 3929 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 3930 /* Disable Tx/Rx */ 3931 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 3932 /* Check MAC Tx/Rx idle */ 3933 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY))) 3934 rt2x00_warn(rt2x00dev, "RF busy while configuring ALC\n"); 3935 3936 if (chan->center_freq > 2457) { 3937 bbp = rt2800_bbp_read(rt2x00dev, 30); 3938 bbp = 0x40; 3939 rt2800_bbp_write(rt2x00dev, 30, bbp); 3940 rt2800_rfcsr_write(rt2x00dev, 39, 0); 3941 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3942 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb); 3943 else 3944 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b); 3945 } else { 3946 bbp = rt2800_bbp_read(rt2x00dev, 30); 3947 bbp = 0x1f; 3948 rt2800_bbp_write(rt2x00dev, 30, bbp); 3949 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 3950 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3951 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb); 3952 else 3953 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); 3954 } 3955 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl); 3956 3957 rt2800_vco_calibration(rt2x00dev); 3958} 3959 3960static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, 3961 const unsigned int word, 3962 const u8 value) 3963{ 3964 u8 chain, reg; 3965 3966 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { 3967 reg = rt2800_bbp_read(rt2x00dev, 27); 3968 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); 3969 rt2800_bbp_write(rt2x00dev, 27, reg); 3970 3971 rt2800_bbp_write(rt2x00dev, word, value); 3972 } 3973} 3974 3975static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) 3976{ 3977 u8 cal; 3978 3979 /* TX0 IQ Gain */ 3980 rt2800_bbp_write(rt2x00dev, 158, 0x2c); 3981 if (channel <= 14) 3982 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G); 3983 else if (channel >= 36 && channel <= 64) 3984 cal = rt2x00_eeprom_byte(rt2x00dev, 3985 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G); 3986 else if (channel >= 100 && channel <= 138) 3987 cal = rt2x00_eeprom_byte(rt2x00dev, 3988 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G); 3989 else if (channel >= 140 && channel <= 165) 3990 cal = rt2x00_eeprom_byte(rt2x00dev, 3991 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G); 3992 else 3993 cal = 0; 3994 rt2800_bbp_write(rt2x00dev, 159, cal); 3995 3996 /* TX0 IQ Phase */ 3997 rt2800_bbp_write(rt2x00dev, 158, 0x2d); 3998 if (channel <= 14) 3999 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G); 4000 else if (channel >= 36 && channel <= 64) 4001 cal = rt2x00_eeprom_byte(rt2x00dev, 4002 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G); 4003 else if (channel >= 100 && channel <= 138) 4004 cal = rt2x00_eeprom_byte(rt2x00dev, 4005 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G); 4006 else if (channel >= 140 && channel <= 165) 4007 cal = rt2x00_eeprom_byte(rt2x00dev, 4008 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G); 4009 else 4010 cal = 0; 4011 rt2800_bbp_write(rt2x00dev, 159, cal); 4012 4013 /* TX1 IQ Gain */ 4014 rt2800_bbp_write(rt2x00dev, 158, 0x4a); 4015 if (channel <= 14) 4016 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G); 4017 else if (channel >= 36 && channel <= 64) 4018 cal = rt2x00_eeprom_byte(rt2x00dev, 4019 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G); 4020 else if (channel >= 100 && channel <= 138) 4021 cal = rt2x00_eeprom_byte(rt2x00dev, 4022 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G); 4023 else if (channel >= 140 && channel <= 165) 4024 cal = rt2x00_eeprom_byte(rt2x00dev, 4025 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G); 4026 else 4027 cal = 0; 4028 rt2800_bbp_write(rt2x00dev, 159, cal); 4029 4030 /* TX1 IQ Phase */ 4031 rt2800_bbp_write(rt2x00dev, 158, 0x4b); 4032 if (channel <= 14) 4033 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G); 4034 else if (channel >= 36 && channel <= 64) 4035 cal = rt2x00_eeprom_byte(rt2x00dev, 4036 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G); 4037 else if (channel >= 100 && channel <= 138) 4038 cal = rt2x00_eeprom_byte(rt2x00dev, 4039 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G); 4040 else if (channel >= 140 && channel <= 165) 4041 cal = rt2x00_eeprom_byte(rt2x00dev, 4042 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G); 4043 else 4044 cal = 0; 4045 rt2800_bbp_write(rt2x00dev, 159, cal); 4046 4047 /* FIXME: possible RX0, RX1 callibration ? */ 4048 4049 /* RF IQ compensation control */ 4050 rt2800_bbp_write(rt2x00dev, 158, 0x04); 4051 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL); 4052 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 4053 4054 /* RF IQ imbalance compensation control */ 4055 rt2800_bbp_write(rt2x00dev, 158, 0x03); 4056 cal = rt2x00_eeprom_byte(rt2x00dev, 4057 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL); 4058 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 4059} 4060 4061static s8 rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev, 4062 unsigned int channel, 4063 s8 txpower) 4064{ 4065 if (rt2x00_rt(rt2x00dev, RT3593) || 4066 rt2x00_rt(rt2x00dev, RT3883)) 4067 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC); 4068 4069 if (channel <= 14) 4070 return clamp_t(s8, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER); 4071 4072 if (rt2x00_rt(rt2x00dev, RT3593) || 4073 rt2x00_rt(rt2x00dev, RT3883)) 4074 return clamp_t(s8, txpower, MIN_A_TXPOWER_3593, 4075 MAX_A_TXPOWER_3593); 4076 else 4077 return clamp_t(s8, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER); 4078} 4079 4080static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev, 4081 struct rf_channel *rf) 4082{ 4083 u8 bbp; 4084 4085 bbp = (rf->channel > 14) ? 0x48 : 0x38; 4086 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp); 4087 4088 rt2800_bbp_write(rt2x00dev, 69, 0x12); 4089 4090 if (rf->channel <= 14) { 4091 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4092 } else { 4093 /* Disable CCK packet detection */ 4094 rt2800_bbp_write(rt2x00dev, 70, 0x00); 4095 } 4096 4097 rt2800_bbp_write(rt2x00dev, 73, 0x10); 4098 4099 if (rf->channel > 14) { 4100 rt2800_bbp_write(rt2x00dev, 62, 0x1d); 4101 rt2800_bbp_write(rt2x00dev, 63, 0x1d); 4102 rt2800_bbp_write(rt2x00dev, 64, 0x1d); 4103 } else { 4104 rt2800_bbp_write(rt2x00dev, 62, 0x2d); 4105 rt2800_bbp_write(rt2x00dev, 63, 0x2d); 4106 rt2800_bbp_write(rt2x00dev, 64, 0x2d); 4107 } 4108} 4109 4110static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 4111 struct ieee80211_conf *conf, 4112 struct rf_channel *rf, 4113 struct channel_info *info) 4114{ 4115 u32 reg; 4116 u32 tx_pin; 4117 u8 bbp, rfcsr; 4118 4119 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4120 info->default_power1); 4121 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4122 info->default_power2); 4123 if (rt2x00dev->default_ant.tx_chain_num > 2) 4124 info->default_power3 = 4125 rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4126 info->default_power3); 4127 4128 switch (rt2x00dev->chip.rt) { 4129 case RT3883: 4130 rt3883_bbp_adjust(rt2x00dev, rf); 4131 break; 4132 } 4133 4134 switch (rt2x00dev->chip.rf) { 4135 case RF2020: 4136 case RF3020: 4137 case RF3021: 4138 case RF3022: 4139 case RF3320: 4140 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 4141 break; 4142 case RF3052: 4143 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 4144 break; 4145 case RF3053: 4146 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info); 4147 break; 4148 case RF3290: 4149 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 4150 break; 4151 case RF3322: 4152 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); 4153 break; 4154 case RF3853: 4155 rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info); 4156 break; 4157 case RF3070: 4158 case RF5350: 4159 case RF5360: 4160 case RF5362: 4161 case RF5370: 4162 case RF5372: 4163 case RF5390: 4164 case RF5392: 4165 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 4166 break; 4167 case RF5592: 4168 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); 4169 break; 4170 case RF7620: 4171 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info); 4172 break; 4173 default: 4174 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 4175 } 4176 4177 if (rt2x00_rf(rt2x00dev, RF3070) || 4178 rt2x00_rf(rt2x00dev, RF3290) || 4179 rt2x00_rf(rt2x00dev, RF3322) || 4180 rt2x00_rf(rt2x00dev, RF5350) || 4181 rt2x00_rf(rt2x00dev, RF5360) || 4182 rt2x00_rf(rt2x00dev, RF5362) || 4183 rt2x00_rf(rt2x00dev, RF5370) || 4184 rt2x00_rf(rt2x00dev, RF5372) || 4185 rt2x00_rf(rt2x00dev, RF5390) || 4186 rt2x00_rf(rt2x00dev, RF5392)) { 4187 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 4188 if (rt2x00_rf(rt2x00dev, RF3322)) { 4189 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M, 4190 conf_is_ht40(conf)); 4191 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M, 4192 conf_is_ht40(conf)); 4193 } else { 4194 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 4195 conf_is_ht40(conf)); 4196 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 4197 conf_is_ht40(conf)); 4198 } 4199 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 4200 4201 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 4202 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 4203 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 4204 } 4205 4206 /* 4207 * Change BBP settings 4208 */ 4209 4210 if (rt2x00_rt(rt2x00dev, RT3352)) { 4211 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4212 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4213 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4214 4215 rt2800_bbp_write(rt2x00dev, 27, 0x0); 4216 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 4217 rt2800_bbp_write(rt2x00dev, 27, 0x20); 4218 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 4219 rt2800_bbp_write(rt2x00dev, 86, 0x38); 4220 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 4221 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 4222 if (rf->channel > 14) { 4223 /* Disable CCK Packet detection on 5GHz */ 4224 rt2800_bbp_write(rt2x00dev, 70, 0x00); 4225 } else { 4226 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4227 } 4228 4229 if (conf_is_ht40(conf)) 4230 rt2800_bbp_write(rt2x00dev, 105, 0x04); 4231 else 4232 rt2800_bbp_write(rt2x00dev, 105, 0x34); 4233 4234 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4235 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4236 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4237 rt2800_bbp_write(rt2x00dev, 77, 0x98); 4238 } else if (rt2x00_rt(rt2x00dev, RT3883)) { 4239 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4240 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4241 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4242 4243 if (rt2x00dev->default_ant.rx_chain_num > 1) 4244 rt2800_bbp_write(rt2x00dev, 86, 0x46); 4245 else 4246 rt2800_bbp_write(rt2x00dev, 86, 0); 4247 } else { 4248 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4249 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4250 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4251 if (rt2x00_rt(rt2x00dev, RT6352)) 4252 rt2800_bbp_write(rt2x00dev, 86, 0x38); 4253 else 4254 rt2800_bbp_write(rt2x00dev, 86, 0); 4255 } 4256 4257 if (rf->channel <= 14) { 4258 if (!rt2x00_rt(rt2x00dev, RT5390) && 4259 !rt2x00_rt(rt2x00dev, RT5392) && 4260 !rt2x00_rt(rt2x00dev, RT6352)) { 4261 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 4262 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4263 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4264 rt2800_bbp_write(rt2x00dev, 75, 0x46); 4265 } else { 4266 if (rt2x00_rt(rt2x00dev, RT3593)) 4267 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4268 else 4269 rt2800_bbp_write(rt2x00dev, 82, 0x84); 4270 rt2800_bbp_write(rt2x00dev, 75, 0x50); 4271 } 4272 if (rt2x00_rt(rt2x00dev, RT3593) || 4273 rt2x00_rt(rt2x00dev, RT3883)) 4274 rt2800_bbp_write(rt2x00dev, 83, 0x8a); 4275 } 4276 4277 } else { 4278 if (rt2x00_rt(rt2x00dev, RT3572)) 4279 rt2800_bbp_write(rt2x00dev, 82, 0x94); 4280 else if (rt2x00_rt(rt2x00dev, RT3593) || 4281 rt2x00_rt(rt2x00dev, RT3883)) 4282 rt2800_bbp_write(rt2x00dev, 82, 0x82); 4283 else if (!rt2x00_rt(rt2x00dev, RT6352)) 4284 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 4285 4286 if (rt2x00_rt(rt2x00dev, RT3593) || 4287 rt2x00_rt(rt2x00dev, RT3883)) 4288 rt2800_bbp_write(rt2x00dev, 83, 0x9a); 4289 4290 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) 4291 rt2800_bbp_write(rt2x00dev, 75, 0x46); 4292 else 4293 rt2800_bbp_write(rt2x00dev, 75, 0x50); 4294 } 4295 4296 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG); 4297 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); 4298 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); 4299 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); 4300 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 4301 4302 if (rt2x00_rt(rt2x00dev, RT3572)) 4303 rt2800_rfcsr_write(rt2x00dev, 8, 0); 4304 4305 if (rt2x00_rt(rt2x00dev, RT6352)) { 4306 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 4307 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); 4308 } else { 4309 tx_pin = 0; 4310 } 4311 4312 switch (rt2x00dev->default_ant.tx_chain_num) { 4313 case 3: 4314 /* Turn on tertiary PAs */ 4315 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 4316 rf->channel > 14); 4317 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 4318 rf->channel <= 14); 4319 fallthrough; 4320 case 2: 4321 /* Turn on secondary PAs */ 4322 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 4323 rf->channel > 14); 4324 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 4325 rf->channel <= 14); 4326 fallthrough; 4327 case 1: 4328 /* Turn on primary PAs */ 4329 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 4330 rf->channel > 14); 4331 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) 4332 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 4333 else 4334 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 4335 rf->channel <= 14); 4336 break; 4337 } 4338 4339 switch (rt2x00dev->default_ant.rx_chain_num) { 4340 case 3: 4341 /* Turn on tertiary LNAs */ 4342 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); 4343 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); 4344 fallthrough; 4345 case 2: 4346 /* Turn on secondary LNAs */ 4347 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); 4348 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); 4349 fallthrough; 4350 case 1: 4351 /* Turn on primary LNAs */ 4352 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); 4353 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); 4354 break; 4355 } 4356 4357 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 4358 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 4359 4360 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 4361 4362 if (rt2x00_rt(rt2x00dev, RT3572)) { 4363 rt2800_rfcsr_write(rt2x00dev, 8, 0x80); 4364 4365 /* AGC init */ 4366 if (rf->channel <= 14) 4367 reg = 0x1c + (2 * rt2x00dev->lna_gain); 4368 else 4369 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 4370 4371 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4372 } 4373 4374 if (rt2x00_rt(rt2x00dev, RT3593)) { 4375 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 4376 4377 /* Band selection */ 4378 if (rt2x00_is_usb(rt2x00dev) || 4379 rt2x00_is_pcie(rt2x00dev)) { 4380 /* GPIO #8 controls all paths */ 4381 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); 4382 if (rf->channel <= 14) 4383 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); 4384 else 4385 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); 4386 } 4387 4388 /* LNA PE control. */ 4389 if (rt2x00_is_usb(rt2x00dev)) { 4390 /* GPIO #4 controls PE0 and PE1, 4391 * GPIO #7 controls PE2 4392 */ 4393 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 4394 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 4395 4396 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 4397 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 4398 } else if (rt2x00_is_pcie(rt2x00dev)) { 4399 /* GPIO #4 controls PE0, PE1 and PE2 */ 4400 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 4401 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 4402 } 4403 4404 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 4405 4406 /* AGC init */ 4407 if (rf->channel <= 14) 4408 reg = 0x1c + 2 * rt2x00dev->lna_gain; 4409 else 4410 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 4411 4412 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4413 4414 usleep_range(1000, 1500); 4415 } 4416 4417 if (rt2x00_rt(rt2x00dev, RT3883)) { 4418 if (!conf_is_ht40(conf)) 4419 rt2800_bbp_write(rt2x00dev, 105, 0x34); 4420 else 4421 rt2800_bbp_write(rt2x00dev, 105, 0x04); 4422 4423 /* AGC init */ 4424 if (rf->channel <= 14) 4425 reg = 0x2e + rt2x00dev->lna_gain; 4426 else 4427 reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3); 4428 4429 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4430 4431 usleep_range(1000, 1500); 4432 } 4433 4434 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) { 4435 reg = 0x10; 4436 if (!conf_is_ht40(conf)) { 4437 if (rt2x00_rt(rt2x00dev, RT6352) && 4438 rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 4439 reg |= 0x5; 4440 } else { 4441 reg |= 0xa; 4442 } 4443 } 4444 rt2800_bbp_write(rt2x00dev, 195, 141); 4445 rt2800_bbp_write(rt2x00dev, 196, reg); 4446 4447 /* AGC init. 4448 * Despite the vendor driver using different values here for 4449 * RT6352 chip, we use 0x1c for now. This may have to be changed 4450 * once TSSI got implemented. 4451 */ 4452 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain; 4453 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4454 4455 if (rt2x00_rt(rt2x00dev, RT5592)) 4456 rt2800_iq_calibrate(rt2x00dev, rf->channel); 4457 } 4458 4459 if (rt2x00_rt(rt2x00dev, RT6352)) { 4460 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, 4461 &rt2x00dev->cap_flags)) { 4462 reg = rt2800_register_read(rt2x00dev, RF_CONTROL3); 4463 reg |= 0x00000101; 4464 rt2800_register_write(rt2x00dev, RF_CONTROL3, reg); 4465 4466 reg = rt2800_register_read(rt2x00dev, RF_BYPASS3); 4467 reg |= 0x00000101; 4468 rt2800_register_write(rt2x00dev, RF_BYPASS3, reg); 4469 4470 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73); 4471 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73); 4472 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73); 4473 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 4474 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8); 4475 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4); 4476 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05); 4477 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 4478 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8); 4479 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4); 4480 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05); 4481 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27); 4482 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8); 4483 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4); 4484 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05); 4485 rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00); 4486 4487 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 4488 0x36303636); 4489 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 4490 0x6C6C6B6C); 4491 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 4492 0x6C6C6B6C); 4493 } 4494 } 4495 4496 bbp = rt2800_bbp_read(rt2x00dev, 4); 4497 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 4498 rt2800_bbp_write(rt2x00dev, 4, bbp); 4499 4500 bbp = rt2800_bbp_read(rt2x00dev, 3); 4501 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); 4502 rt2800_bbp_write(rt2x00dev, 3, bbp); 4503 4504 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 4505 if (conf_is_ht40(conf)) { 4506 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 4507 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4508 rt2800_bbp_write(rt2x00dev, 73, 0x16); 4509 } else { 4510 rt2800_bbp_write(rt2x00dev, 69, 0x16); 4511 rt2800_bbp_write(rt2x00dev, 70, 0x08); 4512 rt2800_bbp_write(rt2x00dev, 73, 0x11); 4513 } 4514 } 4515 4516 usleep_range(1000, 1500); 4517 4518 /* 4519 * Clear channel statistic counters 4520 */ 4521 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 4522 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 4523 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 4524 4525 /* 4526 * Clear update flag 4527 */ 4528 if (rt2x00_rt(rt2x00dev, RT3352) || 4529 rt2x00_rt(rt2x00dev, RT5350)) { 4530 bbp = rt2800_bbp_read(rt2x00dev, 49); 4531 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); 4532 rt2800_bbp_write(rt2x00dev, 49, bbp); 4533 } 4534} 4535 4536static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 4537{ 4538 u8 tssi_bounds[9]; 4539 u8 current_tssi; 4540 u16 eeprom; 4541 u8 step; 4542 int i; 4543 4544 /* 4545 * First check if temperature compensation is supported. 4546 */ 4547 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 4548 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC)) 4549 return 0; 4550 4551 /* 4552 * Read TSSI boundaries for temperature compensation from 4553 * the EEPROM. 4554 * 4555 * Array idx 0 1 2 3 4 5 6 7 8 4556 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 4557 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 4558 */ 4559 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 4560 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1); 4561 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4562 EEPROM_TSSI_BOUND_BG1_MINUS4); 4563 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4564 EEPROM_TSSI_BOUND_BG1_MINUS3); 4565 4566 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2); 4567 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4568 EEPROM_TSSI_BOUND_BG2_MINUS2); 4569 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4570 EEPROM_TSSI_BOUND_BG2_MINUS1); 4571 4572 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3); 4573 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4574 EEPROM_TSSI_BOUND_BG3_REF); 4575 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4576 EEPROM_TSSI_BOUND_BG3_PLUS1); 4577 4578 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4); 4579 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4580 EEPROM_TSSI_BOUND_BG4_PLUS2); 4581 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4582 EEPROM_TSSI_BOUND_BG4_PLUS3); 4583 4584 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5); 4585 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4586 EEPROM_TSSI_BOUND_BG5_PLUS4); 4587 4588 step = rt2x00_get_field16(eeprom, 4589 EEPROM_TSSI_BOUND_BG5_AGC_STEP); 4590 } else { 4591 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1); 4592 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4593 EEPROM_TSSI_BOUND_A1_MINUS4); 4594 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4595 EEPROM_TSSI_BOUND_A1_MINUS3); 4596 4597 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2); 4598 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4599 EEPROM_TSSI_BOUND_A2_MINUS2); 4600 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4601 EEPROM_TSSI_BOUND_A2_MINUS1); 4602 4603 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3); 4604 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4605 EEPROM_TSSI_BOUND_A3_REF); 4606 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4607 EEPROM_TSSI_BOUND_A3_PLUS1); 4608 4609 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4); 4610 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4611 EEPROM_TSSI_BOUND_A4_PLUS2); 4612 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4613 EEPROM_TSSI_BOUND_A4_PLUS3); 4614 4615 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5); 4616 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4617 EEPROM_TSSI_BOUND_A5_PLUS4); 4618 4619 step = rt2x00_get_field16(eeprom, 4620 EEPROM_TSSI_BOUND_A5_AGC_STEP); 4621 } 4622 4623 /* 4624 * Check if temperature compensation is supported. 4625 */ 4626 if (tssi_bounds[4] == 0xff || step == 0xff) 4627 return 0; 4628 4629 /* 4630 * Read current TSSI (BBP 49). 4631 */ 4632 current_tssi = rt2800_bbp_read(rt2x00dev, 49); 4633 4634 /* 4635 * Compare TSSI value (BBP49) with the compensation boundaries 4636 * from the EEPROM and increase or decrease tx power. 4637 */ 4638 for (i = 0; i <= 3; i++) { 4639 if (current_tssi > tssi_bounds[i]) 4640 break; 4641 } 4642 4643 if (i == 4) { 4644 for (i = 8; i >= 5; i--) { 4645 if (current_tssi < tssi_bounds[i]) 4646 break; 4647 } 4648 } 4649 4650 return (i - 4) * step; 4651} 4652 4653static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, 4654 enum nl80211_band band) 4655{ 4656 u16 eeprom; 4657 u8 comp_en; 4658 u8 comp_type; 4659 int comp_value = 0; 4660 4661 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA); 4662 4663 /* 4664 * HT40 compensation not required. 4665 */ 4666 if (eeprom == 0xffff || 4667 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4668 return 0; 4669 4670 if (band == NL80211_BAND_2GHZ) { 4671 comp_en = rt2x00_get_field16(eeprom, 4672 EEPROM_TXPOWER_DELTA_ENABLE_2G); 4673 if (comp_en) { 4674 comp_type = rt2x00_get_field16(eeprom, 4675 EEPROM_TXPOWER_DELTA_TYPE_2G); 4676 comp_value = rt2x00_get_field16(eeprom, 4677 EEPROM_TXPOWER_DELTA_VALUE_2G); 4678 if (!comp_type) 4679 comp_value = -comp_value; 4680 } 4681 } else { 4682 comp_en = rt2x00_get_field16(eeprom, 4683 EEPROM_TXPOWER_DELTA_ENABLE_5G); 4684 if (comp_en) { 4685 comp_type = rt2x00_get_field16(eeprom, 4686 EEPROM_TXPOWER_DELTA_TYPE_5G); 4687 comp_value = rt2x00_get_field16(eeprom, 4688 EEPROM_TXPOWER_DELTA_VALUE_5G); 4689 if (!comp_type) 4690 comp_value = -comp_value; 4691 } 4692 } 4693 4694 return comp_value; 4695} 4696 4697static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, 4698 int power_level, int max_power) 4699{ 4700 int delta; 4701 4702 if (rt2x00_has_cap_power_limit(rt2x00dev)) 4703 return 0; 4704 4705 /* 4706 * XXX: We don't know the maximum transmit power of our hardware since 4707 * the EEPROM doesn't expose it. We only know that we are calibrated 4708 * to 100% tx power. 4709 * 4710 * Hence, we assume the regulatory limit that cfg80211 calulated for 4711 * the current channel is our maximum and if we are requested to lower 4712 * the value we just reduce our tx power accordingly. 4713 */ 4714 delta = power_level - max_power; 4715 return min(delta, 0); 4716} 4717 4718static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, 4719 enum nl80211_band band, int power_level, 4720 u8 txpower, int delta) 4721{ 4722 u16 eeprom; 4723 u8 criterion; 4724 u8 eirp_txpower; 4725 u8 eirp_txpower_criterion; 4726 u8 reg_limit; 4727 4728 if (rt2x00_rt(rt2x00dev, RT3593)) 4729 return min_t(u8, txpower, 0xc); 4730 4731 if (rt2x00_rt(rt2x00dev, RT3883)) 4732 return min_t(u8, txpower, 0xf); 4733 4734 if (rt2x00_has_cap_power_limit(rt2x00dev)) { 4735 /* 4736 * Check if eirp txpower exceed txpower_limit. 4737 * We use OFDM 6M as criterion and its eirp txpower 4738 * is stored at EEPROM_EIRP_MAX_TX_POWER. 4739 * .11b data rate need add additional 4dbm 4740 * when calculating eirp txpower. 4741 */ 4742 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4743 EEPROM_TXPOWER_BYRATE, 4744 1); 4745 criterion = rt2x00_get_field16(eeprom, 4746 EEPROM_TXPOWER_BYRATE_RATE0); 4747 4748 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 4749 4750 if (band == NL80211_BAND_2GHZ) 4751 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4752 EEPROM_EIRP_MAX_TX_POWER_2GHZ); 4753 else 4754 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4755 EEPROM_EIRP_MAX_TX_POWER_5GHZ); 4756 4757 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + 4758 (is_rate_b ? 4 : 0) + delta; 4759 4760 reg_limit = (eirp_txpower > power_level) ? 4761 (eirp_txpower - power_level) : 0; 4762 } else 4763 reg_limit = 0; 4764 4765 txpower = max(0, txpower + delta - reg_limit); 4766 return min_t(u8, txpower, 0xc); 4767} 4768 4769 4770enum { 4771 TX_PWR_CFG_0_IDX, 4772 TX_PWR_CFG_1_IDX, 4773 TX_PWR_CFG_2_IDX, 4774 TX_PWR_CFG_3_IDX, 4775 TX_PWR_CFG_4_IDX, 4776 TX_PWR_CFG_5_IDX, 4777 TX_PWR_CFG_6_IDX, 4778 TX_PWR_CFG_7_IDX, 4779 TX_PWR_CFG_8_IDX, 4780 TX_PWR_CFG_9_IDX, 4781 TX_PWR_CFG_0_EXT_IDX, 4782 TX_PWR_CFG_1_EXT_IDX, 4783 TX_PWR_CFG_2_EXT_IDX, 4784 TX_PWR_CFG_3_EXT_IDX, 4785 TX_PWR_CFG_4_EXT_IDX, 4786 TX_PWR_CFG_IDX_COUNT, 4787}; 4788 4789static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, 4790 struct ieee80211_channel *chan, 4791 int power_level) 4792{ 4793 u8 txpower; 4794 u16 eeprom; 4795 u32 regs[TX_PWR_CFG_IDX_COUNT]; 4796 unsigned int offset; 4797 enum nl80211_band band = chan->band; 4798 int delta; 4799 int i; 4800 4801 memset(regs, '\0', sizeof(regs)); 4802 4803 /* TODO: adapt TX power reduction from the rt28xx code */ 4804 4805 /* calculate temperature compensation delta */ 4806 delta = rt2800_get_gain_calibration_delta(rt2x00dev); 4807 4808 if (band == NL80211_BAND_5GHZ) 4809 offset = 16; 4810 else 4811 offset = 0; 4812 4813 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4814 offset += 8; 4815 4816 /* read the next four txpower values */ 4817 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4818 offset); 4819 4820 /* CCK 1MBS,2MBS */ 4821 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4822 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4823 txpower, delta); 4824 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4825 TX_PWR_CFG_0_CCK1_CH0, txpower); 4826 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4827 TX_PWR_CFG_0_CCK1_CH1, txpower); 4828 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4829 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower); 4830 4831 /* CCK 5.5MBS,11MBS */ 4832 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4833 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4834 txpower, delta); 4835 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4836 TX_PWR_CFG_0_CCK5_CH0, txpower); 4837 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4838 TX_PWR_CFG_0_CCK5_CH1, txpower); 4839 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4840 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower); 4841 4842 /* OFDM 6MBS,9MBS */ 4843 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4844 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4845 txpower, delta); 4846 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4847 TX_PWR_CFG_0_OFDM6_CH0, txpower); 4848 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4849 TX_PWR_CFG_0_OFDM6_CH1, txpower); 4850 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4851 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower); 4852 4853 /* OFDM 12MBS,18MBS */ 4854 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4855 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4856 txpower, delta); 4857 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4858 TX_PWR_CFG_0_OFDM12_CH0, txpower); 4859 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4860 TX_PWR_CFG_0_OFDM12_CH1, txpower); 4861 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4862 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); 4863 4864 /* read the next four txpower values */ 4865 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4866 offset + 1); 4867 4868 /* OFDM 24MBS,36MBS */ 4869 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4870 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4871 txpower, delta); 4872 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4873 TX_PWR_CFG_1_OFDM24_CH0, txpower); 4874 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4875 TX_PWR_CFG_1_OFDM24_CH1, txpower); 4876 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4877 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower); 4878 4879 /* OFDM 48MBS */ 4880 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4881 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4882 txpower, delta); 4883 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4884 TX_PWR_CFG_1_OFDM48_CH0, txpower); 4885 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4886 TX_PWR_CFG_1_OFDM48_CH1, txpower); 4887 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4888 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower); 4889 4890 /* OFDM 54MBS */ 4891 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4892 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4893 txpower, delta); 4894 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4895 TX_PWR_CFG_7_OFDM54_CH0, txpower); 4896 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4897 TX_PWR_CFG_7_OFDM54_CH1, txpower); 4898 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4899 TX_PWR_CFG_7_OFDM54_CH2, txpower); 4900 4901 /* read the next four txpower values */ 4902 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4903 offset + 2); 4904 4905 /* MCS 0,1 */ 4906 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4907 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4908 txpower, delta); 4909 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4910 TX_PWR_CFG_1_MCS0_CH0, txpower); 4911 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4912 TX_PWR_CFG_1_MCS0_CH1, txpower); 4913 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4914 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower); 4915 4916 /* MCS 2,3 */ 4917 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4918 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4919 txpower, delta); 4920 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4921 TX_PWR_CFG_1_MCS2_CH0, txpower); 4922 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4923 TX_PWR_CFG_1_MCS2_CH1, txpower); 4924 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4925 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower); 4926 4927 /* MCS 4,5 */ 4928 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4929 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4930 txpower, delta); 4931 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4932 TX_PWR_CFG_2_MCS4_CH0, txpower); 4933 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4934 TX_PWR_CFG_2_MCS4_CH1, txpower); 4935 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4936 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower); 4937 4938 /* MCS 6 */ 4939 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4940 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4941 txpower, delta); 4942 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4943 TX_PWR_CFG_2_MCS6_CH0, txpower); 4944 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4945 TX_PWR_CFG_2_MCS6_CH1, txpower); 4946 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4947 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); 4948 4949 /* read the next four txpower values */ 4950 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4951 offset + 3); 4952 4953 /* MCS 7 */ 4954 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4955 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4956 txpower, delta); 4957 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4958 TX_PWR_CFG_7_MCS7_CH0, txpower); 4959 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4960 TX_PWR_CFG_7_MCS7_CH1, txpower); 4961 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4962 TX_PWR_CFG_7_MCS7_CH2, txpower); 4963 4964 /* MCS 8,9 */ 4965 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4966 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4967 txpower, delta); 4968 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4969 TX_PWR_CFG_2_MCS8_CH0, txpower); 4970 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4971 TX_PWR_CFG_2_MCS8_CH1, txpower); 4972 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4973 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower); 4974 4975 /* MCS 10,11 */ 4976 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4977 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4978 txpower, delta); 4979 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4980 TX_PWR_CFG_2_MCS10_CH0, txpower); 4981 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4982 TX_PWR_CFG_2_MCS10_CH1, txpower); 4983 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4984 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower); 4985 4986 /* MCS 12,13 */ 4987 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4988 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4989 txpower, delta); 4990 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4991 TX_PWR_CFG_3_MCS12_CH0, txpower); 4992 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4993 TX_PWR_CFG_3_MCS12_CH1, txpower); 4994 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4995 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); 4996 4997 /* read the next four txpower values */ 4998 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4999 offset + 4); 5000 5001 /* MCS 14 */ 5002 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 5003 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5004 txpower, delta); 5005 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5006 TX_PWR_CFG_3_MCS14_CH0, txpower); 5007 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5008 TX_PWR_CFG_3_MCS14_CH1, txpower); 5009 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 5010 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower); 5011 5012 /* MCS 15 */ 5013 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 5014 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5015 txpower, delta); 5016 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5017 TX_PWR_CFG_8_MCS15_CH0, txpower); 5018 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5019 TX_PWR_CFG_8_MCS15_CH1, txpower); 5020 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5021 TX_PWR_CFG_8_MCS15_CH2, txpower); 5022 5023 /* MCS 16,17 */ 5024 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 5025 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5026 txpower, delta); 5027 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5028 TX_PWR_CFG_5_MCS16_CH0, txpower); 5029 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5030 TX_PWR_CFG_5_MCS16_CH1, txpower); 5031 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5032 TX_PWR_CFG_5_MCS16_CH2, txpower); 5033 5034 /* MCS 18,19 */ 5035 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 5036 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5037 txpower, delta); 5038 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5039 TX_PWR_CFG_5_MCS18_CH0, txpower); 5040 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5041 TX_PWR_CFG_5_MCS18_CH1, txpower); 5042 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 5043 TX_PWR_CFG_5_MCS18_CH2, txpower); 5044 5045 /* read the next four txpower values */ 5046 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 5047 offset + 5); 5048 5049 /* MCS 20,21 */ 5050 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 5051 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5052 txpower, delta); 5053 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5054 TX_PWR_CFG_6_MCS20_CH0, txpower); 5055 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5056 TX_PWR_CFG_6_MCS20_CH1, txpower); 5057 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5058 TX_PWR_CFG_6_MCS20_CH2, txpower); 5059 5060 /* MCS 22 */ 5061 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 5062 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5063 txpower, delta); 5064 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5065 TX_PWR_CFG_6_MCS22_CH0, txpower); 5066 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5067 TX_PWR_CFG_6_MCS22_CH1, txpower); 5068 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 5069 TX_PWR_CFG_6_MCS22_CH2, txpower); 5070 5071 /* MCS 23 */ 5072 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 5073 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5074 txpower, delta); 5075 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5076 TX_PWR_CFG_8_MCS23_CH0, txpower); 5077 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5078 TX_PWR_CFG_8_MCS23_CH1, txpower); 5079 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 5080 TX_PWR_CFG_8_MCS23_CH2, txpower); 5081 5082 /* read the next four txpower values */ 5083 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 5084 offset + 6); 5085 5086 /* STBC, MCS 0,1 */ 5087 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 5088 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5089 txpower, delta); 5090 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5091 TX_PWR_CFG_3_STBC0_CH0, txpower); 5092 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5093 TX_PWR_CFG_3_STBC0_CH1, txpower); 5094 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 5095 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower); 5096 5097 /* STBC, MCS 2,3 */ 5098 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 5099 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5100 txpower, delta); 5101 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5102 TX_PWR_CFG_3_STBC2_CH0, txpower); 5103 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 5104 TX_PWR_CFG_3_STBC2_CH1, txpower); 5105 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 5106 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower); 5107 5108 /* STBC, MCS 4,5 */ 5109 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 5110 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5111 txpower, delta); 5112 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); 5113 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); 5114 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, 5115 txpower); 5116 5117 /* STBC, MCS 6 */ 5118 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 5119 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5120 txpower, delta); 5121 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); 5122 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); 5123 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, 5124 txpower); 5125 5126 /* read the next four txpower values */ 5127 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 5128 offset + 7); 5129 5130 /* STBC, MCS 7 */ 5131 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 5132 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 5133 txpower, delta); 5134 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5135 TX_PWR_CFG_9_STBC7_CH0, txpower); 5136 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5137 TX_PWR_CFG_9_STBC7_CH1, txpower); 5138 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5139 TX_PWR_CFG_9_STBC7_CH2, txpower); 5140 5141 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]); 5142 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]); 5143 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]); 5144 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]); 5145 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]); 5146 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]); 5147 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]); 5148 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]); 5149 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]); 5150 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]); 5151 5152 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT, 5153 regs[TX_PWR_CFG_0_EXT_IDX]); 5154 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT, 5155 regs[TX_PWR_CFG_1_EXT_IDX]); 5156 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT, 5157 regs[TX_PWR_CFG_2_EXT_IDX]); 5158 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT, 5159 regs[TX_PWR_CFG_3_EXT_IDX]); 5160 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT, 5161 regs[TX_PWR_CFG_4_EXT_IDX]); 5162 5163 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++) 5164 rt2x00_dbg(rt2x00dev, 5165 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n", 5166 (band == NL80211_BAND_5GHZ) ? '5' : '2', 5167 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ? 5168 '4' : '2', 5169 (i > TX_PWR_CFG_9_IDX) ? 5170 (i - TX_PWR_CFG_9_IDX - 1) : i, 5171 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "", 5172 (unsigned long) regs[i]); 5173} 5174 5175static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev, 5176 struct ieee80211_channel *chan, 5177 int power_level) 5178{ 5179 u32 reg, pwreg; 5180 u16 eeprom; 5181 u32 data, gdata; 5182 u8 t, i; 5183 enum nl80211_band band = chan->band; 5184 int delta; 5185 5186 /* Warn user if bw_comp is set in EEPROM */ 5187 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 5188 5189 if (delta) 5190 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n", 5191 delta); 5192 5193 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit 5194 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor 5195 * driver does as well, though it looks kinda wrong. 5196 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe 5197 * the hardware has a problem handling 0x20, and as the code initially 5198 * used a fixed offset between HT20 and HT40 rates they had to work- 5199 * around that issue and most likely just forgot about it later on. 5200 * Maybe we should use rt2800_get_txpower_bw_comp() here as well, 5201 * however, the corresponding EEPROM value is not respected by the 5202 * vendor driver, so maybe this is rather being taken care of the 5203 * TXALC and the driver doesn't need to handle it...? 5204 * Though this is all very awkward, just do as they did, as that's what 5205 * board vendors expected when they populated the EEPROM... 5206 */ 5207 for (i = 0; i < 5; i++) { 5208 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5209 EEPROM_TXPOWER_BYRATE, 5210 i * 2); 5211 5212 data = eeprom; 5213 5214 t = eeprom & 0x3f; 5215 if (t == 32) 5216 t++; 5217 5218 gdata = t; 5219 5220 t = (eeprom & 0x3f00) >> 8; 5221 if (t == 32) 5222 t++; 5223 5224 gdata |= (t << 8); 5225 5226 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5227 EEPROM_TXPOWER_BYRATE, 5228 (i * 2) + 1); 5229 5230 t = eeprom & 0x3f; 5231 if (t == 32) 5232 t++; 5233 5234 gdata |= (t << 16); 5235 5236 t = (eeprom & 0x3f00) >> 8; 5237 if (t == 32) 5238 t++; 5239 5240 gdata |= (t << 24); 5241 data |= (eeprom << 16); 5242 5243 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) { 5244 /* HT20 */ 5245 if (data != 0xffffffff) 5246 rt2800_register_write(rt2x00dev, 5247 TX_PWR_CFG_0 + (i * 4), 5248 data); 5249 } else { 5250 /* HT40 */ 5251 if (gdata != 0xffffffff) 5252 rt2800_register_write(rt2x00dev, 5253 TX_PWR_CFG_0 + (i * 4), 5254 gdata); 5255 } 5256 } 5257 5258 /* Aparently Ralink ran out of space in the BYRATE calibration section 5259 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x 5260 * registers. As recent 2T chips use 8-bit instead of 4-bit values for 5261 * power-offsets more space would be needed. Ralink decided to keep the 5262 * EEPROM layout untouched and rather have some shared values covering 5263 * multiple bitrates. 5264 * Populate the registers not covered by the EEPROM in the same way the 5265 * vendor driver does. 5266 */ 5267 5268 /* For OFDM 54MBS use value from OFDM 48MBS */ 5269 pwreg = 0; 5270 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1); 5271 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS); 5272 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); 5273 5274 /* For MCS 7 use value from MCS 6 */ 5275 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2); 5276 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7); 5277 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); 5278 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg); 5279 5280 /* For MCS 15 use value from MCS 14 */ 5281 pwreg = 0; 5282 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3); 5283 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14); 5284 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); 5285 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg); 5286 5287 /* For STBC MCS 7 use value from STBC MCS 6 */ 5288 pwreg = 0; 5289 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4); 5290 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6); 5291 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); 5292 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg); 5293 5294 rt2800_config_alc_rt6352(rt2x00dev, chan, power_level); 5295 5296 /* TODO: temperature compensation code! */ 5297} 5298 5299/* 5300 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and 5301 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, 5302 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power 5303 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm. 5304 * Reference per rate transmit power values are located in the EEPROM at 5305 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to 5306 * current conditions (i.e. band, bandwidth, temperature, user settings). 5307 */ 5308static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, 5309 struct ieee80211_channel *chan, 5310 int power_level) 5311{ 5312 u8 txpower, r1; 5313 u16 eeprom; 5314 u32 reg, offset; 5315 int i, is_rate_b, delta, power_ctrl; 5316 enum nl80211_band band = chan->band; 5317 5318 /* 5319 * Calculate HT40 compensation. For 40MHz we need to add or subtract 5320 * value read from EEPROM (different for 2GHz and for 5GHz). 5321 */ 5322 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 5323 5324 /* 5325 * Calculate temperature compensation. Depends on measurement of current 5326 * TSSI (Transmitter Signal Strength Indication) we know TX power (due 5327 * to temperature or maybe other factors) is smaller or bigger than 5328 * expected. We adjust it, based on TSSI reference and boundaries values 5329 * provided in EEPROM. 5330 */ 5331 switch (rt2x00dev->chip.rt) { 5332 case RT2860: 5333 case RT2872: 5334 case RT2883: 5335 case RT3070: 5336 case RT3071: 5337 case RT3090: 5338 case RT3572: 5339 delta += rt2800_get_gain_calibration_delta(rt2x00dev); 5340 break; 5341 default: 5342 /* TODO: temperature compensation code for other chips. */ 5343 break; 5344 } 5345 5346 /* 5347 * Decrease power according to user settings, on devices with unknown 5348 * maximum tx power. For other devices we take user power_level into 5349 * consideration on rt2800_compensate_txpower(). 5350 */ 5351 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level, 5352 chan->max_power); 5353 5354 /* 5355 * BBP_R1 controls TX power for all rates, it allow to set the following 5356 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively. 5357 * 5358 * TODO: we do not use +6 dBm option to do not increase power beyond 5359 * regulatory limit, however this could be utilized for devices with 5360 * CAPABILITY_POWER_LIMIT. 5361 */ 5362 if (delta <= -12) { 5363 power_ctrl = 2; 5364 delta += 12; 5365 } else if (delta <= -6) { 5366 power_ctrl = 1; 5367 delta += 6; 5368 } else { 5369 power_ctrl = 0; 5370 } 5371 r1 = rt2800_bbp_read(rt2x00dev, 1); 5372 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); 5373 rt2800_bbp_write(rt2x00dev, 1, r1); 5374 5375 offset = TX_PWR_CFG_0; 5376 5377 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 5378 /* just to be safe */ 5379 if (offset > TX_PWR_CFG_4) 5380 break; 5381 5382 reg = rt2800_register_read(rt2x00dev, offset); 5383 5384 /* read the next four txpower values */ 5385 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5386 EEPROM_TXPOWER_BYRATE, 5387 i); 5388 5389 is_rate_b = i ? 0 : 1; 5390 /* 5391 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 5392 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 5393 * TX_PWR_CFG_4: unknown 5394 */ 5395 txpower = rt2x00_get_field16(eeprom, 5396 EEPROM_TXPOWER_BYRATE_RATE0); 5397 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5398 power_level, txpower, delta); 5399 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); 5400 5401 /* 5402 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 5403 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 5404 * TX_PWR_CFG_4: unknown 5405 */ 5406 txpower = rt2x00_get_field16(eeprom, 5407 EEPROM_TXPOWER_BYRATE_RATE1); 5408 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5409 power_level, txpower, delta); 5410 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); 5411 5412 /* 5413 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, 5414 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 5415 * TX_PWR_CFG_4: unknown 5416 */ 5417 txpower = rt2x00_get_field16(eeprom, 5418 EEPROM_TXPOWER_BYRATE_RATE2); 5419 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5420 power_level, txpower, delta); 5421 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); 5422 5423 /* 5424 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 5425 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 5426 * TX_PWR_CFG_4: unknown 5427 */ 5428 txpower = rt2x00_get_field16(eeprom, 5429 EEPROM_TXPOWER_BYRATE_RATE3); 5430 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5431 power_level, txpower, delta); 5432 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); 5433 5434 /* read the next four txpower values */ 5435 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5436 EEPROM_TXPOWER_BYRATE, 5437 i + 1); 5438 5439 is_rate_b = 0; 5440 /* 5441 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 5442 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 5443 * TX_PWR_CFG_4: unknown 5444 */ 5445 txpower = rt2x00_get_field16(eeprom, 5446 EEPROM_TXPOWER_BYRATE_RATE0); 5447 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5448 power_level, txpower, delta); 5449 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); 5450 5451 /* 5452 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 5453 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 5454 * TX_PWR_CFG_4: unknown 5455 */ 5456 txpower = rt2x00_get_field16(eeprom, 5457 EEPROM_TXPOWER_BYRATE_RATE1); 5458 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5459 power_level, txpower, delta); 5460 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); 5461 5462 /* 5463 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 5464 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 5465 * TX_PWR_CFG_4: unknown 5466 */ 5467 txpower = rt2x00_get_field16(eeprom, 5468 EEPROM_TXPOWER_BYRATE_RATE2); 5469 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5470 power_level, txpower, delta); 5471 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); 5472 5473 /* 5474 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 5475 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 5476 * TX_PWR_CFG_4: unknown 5477 */ 5478 txpower = rt2x00_get_field16(eeprom, 5479 EEPROM_TXPOWER_BYRATE_RATE3); 5480 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5481 power_level, txpower, delta); 5482 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); 5483 5484 rt2800_register_write(rt2x00dev, offset, reg); 5485 5486 /* next TX_PWR_CFG register */ 5487 offset += 4; 5488 } 5489} 5490 5491static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 5492 struct ieee80211_channel *chan, 5493 int power_level) 5494{ 5495 if (rt2x00_rt(rt2x00dev, RT3593) || 5496 rt2x00_rt(rt2x00dev, RT3883)) 5497 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); 5498 else if (rt2x00_rt(rt2x00dev, RT6352)) 5499 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level); 5500 else 5501 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); 5502} 5503 5504void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) 5505{ 5506 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan, 5507 rt2x00dev->tx_power); 5508} 5509EXPORT_SYMBOL_GPL(rt2800_gain_calibration); 5510 5511void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) 5512{ 5513 u32 tx_pin; 5514 u8 rfcsr; 5515 unsigned long min_sleep = 0; 5516 5517 /* 5518 * A voltage-controlled oscillator(VCO) is an electronic oscillator 5519 * designed to be controlled in oscillation frequency by a voltage 5520 * input. Maybe the temperature will affect the frequency of 5521 * oscillation to be shifted. The VCO calibration will be called 5522 * periodically to adjust the frequency to be precision. 5523 */ 5524 5525 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5526 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; 5527 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5528 5529 switch (rt2x00dev->chip.rf) { 5530 case RF2020: 5531 case RF3020: 5532 case RF3021: 5533 case RF3022: 5534 case RF3320: 5535 case RF3052: 5536 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 5537 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 5538 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 5539 break; 5540 case RF3053: 5541 case RF3070: 5542 case RF3290: 5543 case RF3853: 5544 case RF5350: 5545 case RF5360: 5546 case RF5362: 5547 case RF5370: 5548 case RF5372: 5549 case RF5390: 5550 case RF5392: 5551 case RF5592: 5552 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 5553 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 5554 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 5555 min_sleep = 1000; 5556 break; 5557 case RF7620: 5558 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 5559 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 5560 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4); 5561 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1); 5562 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr); 5563 min_sleep = 2000; 5564 break; 5565 default: 5566 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration", 5567 rt2x00dev->chip.rf); 5568 return; 5569 } 5570 5571 if (min_sleep > 0) 5572 usleep_range(min_sleep, min_sleep * 2); 5573 5574 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5575 if (rt2x00dev->rf_channel <= 14) { 5576 switch (rt2x00dev->default_ant.tx_chain_num) { 5577 case 3: 5578 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); 5579 fallthrough; 5580 case 2: 5581 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 5582 fallthrough; 5583 case 1: 5584 default: 5585 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 5586 break; 5587 } 5588 } else { 5589 switch (rt2x00dev->default_ant.tx_chain_num) { 5590 case 3: 5591 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); 5592 fallthrough; 5593 case 2: 5594 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 5595 fallthrough; 5596 case 1: 5597 default: 5598 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); 5599 break; 5600 } 5601 } 5602 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5603 5604 if (rt2x00_rt(rt2x00dev, RT6352)) { 5605 if (rt2x00dev->default_ant.rx_chain_num == 1) { 5606 rt2800_bbp_write(rt2x00dev, 91, 0x07); 5607 rt2800_bbp_write(rt2x00dev, 95, 0x1A); 5608 rt2800_bbp_write(rt2x00dev, 195, 128); 5609 rt2800_bbp_write(rt2x00dev, 196, 0xA0); 5610 rt2800_bbp_write(rt2x00dev, 195, 170); 5611 rt2800_bbp_write(rt2x00dev, 196, 0x12); 5612 rt2800_bbp_write(rt2x00dev, 195, 171); 5613 rt2800_bbp_write(rt2x00dev, 196, 0x10); 5614 } else { 5615 rt2800_bbp_write(rt2x00dev, 91, 0x06); 5616 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 5617 rt2800_bbp_write(rt2x00dev, 195, 128); 5618 rt2800_bbp_write(rt2x00dev, 196, 0xE0); 5619 rt2800_bbp_write(rt2x00dev, 195, 170); 5620 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5621 rt2800_bbp_write(rt2x00dev, 195, 171); 5622 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5623 } 5624 5625 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 5626 rt2800_bbp_write(rt2x00dev, 75, 0x68); 5627 rt2800_bbp_write(rt2x00dev, 76, 0x4C); 5628 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 5629 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 5630 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 5631 } 5632 5633 /* On 11A, We should delay and wait RF/BBP to be stable 5634 * and the appropriate time should be 1000 micro seconds 5635 * 2005/06/05 - On 11G, we also need this delay time. 5636 * Otherwise it's difficult to pass the WHQL. 5637 */ 5638 usleep_range(1000, 1500); 5639 } 5640} 5641EXPORT_SYMBOL_GPL(rt2800_vco_calibration); 5642 5643static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 5644 struct rt2x00lib_conf *libconf) 5645{ 5646 u32 reg; 5647 5648 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5649 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 5650 libconf->conf->short_frame_max_tx_count); 5651 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 5652 libconf->conf->long_frame_max_tx_count); 5653 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5654} 5655 5656static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, 5657 struct rt2x00lib_conf *libconf) 5658{ 5659 enum dev_state state = 5660 (libconf->conf->flags & IEEE80211_CONF_PS) ? 5661 STATE_SLEEP : STATE_AWAKE; 5662 u32 reg; 5663 5664 if (state == STATE_SLEEP) { 5665 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 5666 5667 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5668 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 5669 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 5670 libconf->conf->listen_interval - 1); 5671 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); 5672 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5673 5674 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5675 } else { 5676 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5677 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 5678 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 5679 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); 5680 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5681 5682 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5683 } 5684} 5685 5686void rt2800_config(struct rt2x00_dev *rt2x00dev, 5687 struct rt2x00lib_conf *libconf, 5688 const unsigned int flags) 5689{ 5690 /* Always recalculate LNA gain before changing configuration */ 5691 rt2800_config_lna_gain(rt2x00dev, libconf); 5692 5693 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { 5694 /* 5695 * To provide correct survey data for survey-based ACS algorithm 5696 * we have to save survey data for current channel before switching. 5697 */ 5698 rt2800_update_survey(rt2x00dev); 5699 5700 rt2800_config_channel(rt2x00dev, libconf->conf, 5701 &libconf->rf, &libconf->channel); 5702 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5703 libconf->conf->power_level); 5704 } 5705 if (flags & IEEE80211_CONF_CHANGE_POWER) 5706 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5707 libconf->conf->power_level); 5708 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 5709 rt2800_config_retry_limit(rt2x00dev, libconf); 5710 if (flags & IEEE80211_CONF_CHANGE_PS) 5711 rt2800_config_ps(rt2x00dev, libconf); 5712} 5713EXPORT_SYMBOL_GPL(rt2800_config); 5714 5715/* 5716 * Link tuning 5717 */ 5718void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5719{ 5720 u32 reg; 5721 5722 /* 5723 * Update FCS error count from register. 5724 */ 5725 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 5726 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 5727} 5728EXPORT_SYMBOL_GPL(rt2800_link_stats); 5729 5730static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 5731{ 5732 u8 vgc; 5733 5734 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 5735 if (rt2x00_rt(rt2x00dev, RT3070) || 5736 rt2x00_rt(rt2x00dev, RT3071) || 5737 rt2x00_rt(rt2x00dev, RT3090) || 5738 rt2x00_rt(rt2x00dev, RT3290) || 5739 rt2x00_rt(rt2x00dev, RT3390) || 5740 rt2x00_rt(rt2x00dev, RT3572) || 5741 rt2x00_rt(rt2x00dev, RT3593) || 5742 rt2x00_rt(rt2x00dev, RT5390) || 5743 rt2x00_rt(rt2x00dev, RT5392) || 5744 rt2x00_rt(rt2x00dev, RT5592) || 5745 rt2x00_rt(rt2x00dev, RT6352)) 5746 vgc = 0x1c + (2 * rt2x00dev->lna_gain); 5747 else 5748 vgc = 0x2e + rt2x00dev->lna_gain; 5749 } else { /* 5GHZ band */ 5750 if (rt2x00_rt(rt2x00dev, RT3593) || 5751 rt2x00_rt(rt2x00dev, RT3883)) 5752 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3; 5753 else if (rt2x00_rt(rt2x00dev, RT5592)) 5754 vgc = 0x24 + (2 * rt2x00dev->lna_gain); 5755 else { 5756 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 5757 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; 5758 else 5759 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3; 5760 } 5761 } 5762 5763 return vgc; 5764} 5765 5766static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 5767 struct link_qual *qual, u8 vgc_level) 5768{ 5769 if (qual->vgc_level != vgc_level) { 5770 if (rt2x00_rt(rt2x00dev, RT3572) || 5771 rt2x00_rt(rt2x00dev, RT3593) || 5772 rt2x00_rt(rt2x00dev, RT3883) || 5773 rt2x00_rt(rt2x00dev, RT6352)) { 5774 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, 5775 vgc_level); 5776 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5777 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); 5778 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); 5779 } else { 5780 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 5781 } 5782 5783 qual->vgc_level = vgc_level; 5784 qual->vgc_level_reg = vgc_level; 5785 } 5786} 5787 5788void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5789{ 5790 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); 5791} 5792EXPORT_SYMBOL_GPL(rt2800_reset_tuner); 5793 5794void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 5795 const u32 count) 5796{ 5797 u8 vgc; 5798 5799 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 5800 return; 5801 5802 /* When RSSI is better than a certain threshold, increase VGC 5803 * with a chip specific value in order to improve the balance 5804 * between sensibility and noise isolation. 5805 */ 5806 5807 vgc = rt2800_get_default_vgc(rt2x00dev); 5808 5809 switch (rt2x00dev->chip.rt) { 5810 case RT3572: 5811 case RT3593: 5812 if (qual->rssi > -65) { 5813 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) 5814 vgc += 0x20; 5815 else 5816 vgc += 0x10; 5817 } 5818 break; 5819 5820 case RT3883: 5821 if (qual->rssi > -65) 5822 vgc += 0x10; 5823 break; 5824 5825 case RT5592: 5826 if (qual->rssi > -65) 5827 vgc += 0x20; 5828 break; 5829 5830 default: 5831 if (qual->rssi > -80) 5832 vgc += 0x10; 5833 break; 5834 } 5835 5836 rt2800_set_vgc(rt2x00dev, qual, vgc); 5837} 5838EXPORT_SYMBOL_GPL(rt2800_link_tuner); 5839 5840/* 5841 * Initialization functions. 5842 */ 5843static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 5844{ 5845 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5846 u32 reg; 5847 u16 eeprom; 5848 unsigned int i; 5849 int ret; 5850 5851 rt2800_disable_wpdma(rt2x00dev); 5852 5853 ret = rt2800_drv_init_registers(rt2x00dev); 5854 if (ret) 5855 return ret; 5856 5857 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 5858 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 5859 5860 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 5861 5862 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 5863 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); 5864 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); 5865 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); 5866 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); 5867 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 5868 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 5869 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 5870 5871 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); 5872 5873 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 5874 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); 5875 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 5876 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 5877 5878 if (rt2x00_rt(rt2x00dev, RT3290)) { 5879 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 5880 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { 5881 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); 5882 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 5883 } 5884 5885 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 5886 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { 5887 rt2x00_set_field32(®, LDO0_EN, 1); 5888 rt2x00_set_field32(®, LDO_BGSEL, 3); 5889 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); 5890 } 5891 5892 reg = rt2800_register_read(rt2x00dev, OSC_CTRL); 5893 rt2x00_set_field32(®, OSC_ROSC_EN, 1); 5894 rt2x00_set_field32(®, OSC_CAL_REQ, 1); 5895 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); 5896 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); 5897 5898 reg = rt2800_register_read(rt2x00dev, COEX_CFG0); 5899 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); 5900 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); 5901 5902 reg = rt2800_register_read(rt2x00dev, COEX_CFG2); 5903 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); 5904 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); 5905 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); 5906 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); 5907 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); 5908 5909 reg = rt2800_register_read(rt2x00dev, PLL_CTRL); 5910 rt2x00_set_field32(®, PLL_CONTROL, 1); 5911 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); 5912 } 5913 5914 if (rt2x00_rt(rt2x00dev, RT3071) || 5915 rt2x00_rt(rt2x00dev, RT3090) || 5916 rt2x00_rt(rt2x00dev, RT3290) || 5917 rt2x00_rt(rt2x00dev, RT3390)) { 5918 5919 if (rt2x00_rt(rt2x00dev, RT3290)) 5920 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5921 0x00000404); 5922 else 5923 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5924 0x00000400); 5925 5926 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5927 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 5928 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 5929 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 5930 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5931 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 5932 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5933 0x0000002c); 5934 else 5935 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5936 0x0000000f); 5937 } else { 5938 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5939 } 5940 } else if (rt2x00_rt(rt2x00dev, RT3070)) { 5941 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5942 5943 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 5944 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5945 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); 5946 } else { 5947 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5948 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5949 } 5950 } else if (rt2800_is_305x_soc(rt2x00dev)) { 5951 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5952 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5953 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 5954 } else if (rt2x00_rt(rt2x00dev, RT3352)) { 5955 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5956 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5957 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5958 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 5959 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5960 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5961 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 5962 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5963 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5964 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { 5965 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5966 if (rt2x00_get_field16(eeprom, 5967 EEPROM_NIC_CONF1_DAC_TEST)) 5968 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5969 0x0000001f); 5970 else 5971 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5972 0x0000000f); 5973 } else { 5974 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5975 0x00000000); 5976 } 5977 } else if (rt2x00_rt(rt2x00dev, RT3883)) { 5978 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5979 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5980 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000); 5981 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21); 5982 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40); 5983 } else if (rt2x00_rt(rt2x00dev, RT5390) || 5984 rt2x00_rt(rt2x00dev, RT5392)) { 5985 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5986 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5987 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5988 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5989 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5990 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5991 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5992 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 5993 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5994 } else if (rt2x00_rt(rt2x00dev, RT6352)) { 5995 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401); 5996 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001); 5997 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5998 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000); 5999 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0); 6000 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0); 6001 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C); 6002 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C); 6003 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 6004 0x3630363A); 6005 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT, 6006 0x3630363A); 6007 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 6008 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); 6009 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 6010 } else { 6011 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 6012 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 6013 } 6014 6015 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG); 6016 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 6017 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); 6018 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 6019 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); 6020 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); 6021 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); 6022 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); 6023 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); 6024 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 6025 6026 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG); 6027 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 6028 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 6029 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 6030 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 6031 6032 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 6033 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 6034 if (rt2x00_is_usb(rt2x00dev)) { 6035 drv_data->max_psdu = 3; 6036 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 6037 rt2x00_rt(rt2x00dev, RT2883) || 6038 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) { 6039 drv_data->max_psdu = 2; 6040 } else { 6041 drv_data->max_psdu = 1; 6042 } 6043 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); 6044 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); 6045 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); 6046 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 6047 6048 reg = rt2800_register_read(rt2x00dev, LED_CFG); 6049 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); 6050 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); 6051 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); 6052 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); 6053 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); 6054 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); 6055 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); 6056 rt2800_register_write(rt2x00dev, LED_CFG, reg); 6057 6058 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 6059 6060 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 6061 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); 6062 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); 6063 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); 6064 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 6065 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); 6066 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 6067 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 6068 6069 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 6070 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); 6071 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 6072 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); 6073 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); 6074 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); 6075 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 6076 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 6077 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 6078 6079 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 6080 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); 6081 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); 6082 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); 6083 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 6084 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6085 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6086 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6087 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6088 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6089 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); 6090 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 6091 6092 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 6093 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); 6094 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); 6095 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); 6096 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 6097 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6098 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6099 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6100 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6101 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6102 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); 6103 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 6104 6105 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 6106 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 6107 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); 6108 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); 6109 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6110 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6111 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6112 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6113 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6114 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6115 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); 6116 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 6117 6118 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 6119 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 6120 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); 6121 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); 6122 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6123 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6124 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6125 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 6126 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6127 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 6128 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); 6129 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 6130 6131 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 6132 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 6133 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); 6134 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); 6135 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6136 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6137 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6138 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 6139 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6140 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 6141 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); 6142 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 6143 6144 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 6145 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 6146 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); 6147 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); 6148 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6149 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6150 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6151 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 6152 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6153 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 6154 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); 6155 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 6156 6157 if (rt2x00_is_usb(rt2x00dev)) { 6158 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 6159 6160 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 6161 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 6162 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 6163 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 6164 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 6165 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 6166 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 6167 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 6168 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 6169 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 6170 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 6171 } 6172 6173 /* 6174 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 6175 * although it is reserved. 6176 */ 6177 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG); 6178 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); 6179 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); 6180 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); 6181 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); 6182 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); 6183 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); 6184 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); 6185 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); 6186 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); 6187 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); 6188 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 6189 6190 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; 6191 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); 6192 6193 if (rt2x00_rt(rt2x00dev, RT3883)) { 6194 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008); 6195 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413); 6196 } 6197 6198 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 6199 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); 6200 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, 6201 IEEE80211_MAX_RTS_THRESHOLD); 6202 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); 6203 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 6204 6205 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 6206 6207 /* 6208 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS 6209 * time should be set to 16. However, the original Ralink driver uses 6210 * 16 for both and indeed using a value of 10 for CCK SIFS results in 6211 * connection problems with 11g + CTS protection. Hence, use the same 6212 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. 6213 */ 6214 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 6215 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); 6216 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); 6217 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 6218 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); 6219 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 6220 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 6221 6222 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 6223 6224 /* 6225 * ASIC will keep garbage value after boot, clear encryption keys. 6226 */ 6227 for (i = 0; i < 4; i++) 6228 rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0); 6229 6230 for (i = 0; i < 256; i++) { 6231 rt2800_config_wcid(rt2x00dev, NULL, i); 6232 rt2800_delete_wcid_attr(rt2x00dev, i); 6233 } 6234 6235 /* 6236 * Clear encryption initialization vectors on start, but keep them 6237 * for watchdog reset. Otherwise we will have wrong IVs and not be 6238 * able to keep connections after reset. 6239 */ 6240 if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags)) 6241 for (i = 0; i < 256; i++) 6242 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 6243 6244 /* 6245 * Clear all beacons 6246 */ 6247 for (i = 0; i < 8; i++) 6248 rt2800_clear_beacon_register(rt2x00dev, i); 6249 6250 if (rt2x00_is_usb(rt2x00dev)) { 6251 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6252 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); 6253 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6254 } else if (rt2x00_is_pcie(rt2x00dev)) { 6255 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6256 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); 6257 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6258 } else if (rt2x00_is_soc(rt2x00dev)) { 6259 struct clk *clk = clk_get_sys("bus", NULL); 6260 int rate; 6261 6262 if (IS_ERR(clk)) { 6263 clk = clk_get_sys("cpu", NULL); 6264 6265 if (IS_ERR(clk)) { 6266 rate = 125; 6267 } else { 6268 rate = clk_get_rate(clk) / 3000000; 6269 clk_put(clk); 6270 } 6271 } else { 6272 rate = clk_get_rate(clk) / 1000000; 6273 clk_put(clk); 6274 } 6275 6276 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6277 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, rate); 6278 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6279 } 6280 6281 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0); 6282 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); 6283 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); 6284 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); 6285 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); 6286 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); 6287 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); 6288 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); 6289 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); 6290 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); 6291 6292 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1); 6293 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); 6294 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); 6295 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); 6296 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); 6297 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); 6298 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); 6299 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); 6300 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); 6301 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); 6302 6303 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0); 6304 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); 6305 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); 6306 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); 6307 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); 6308 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); 6309 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); 6310 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); 6311 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); 6312 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); 6313 6314 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1); 6315 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); 6316 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); 6317 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); 6318 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); 6319 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 6320 6321 /* 6322 * Do not force the BA window size, we use the TXWI to set it 6323 */ 6324 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE); 6325 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); 6326 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); 6327 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); 6328 6329 /* 6330 * We must clear the error counters. 6331 * These registers are cleared on read, 6332 * so we may pass a useless variable to store the value. 6333 */ 6334 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 6335 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1); 6336 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2); 6337 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0); 6338 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1); 6339 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2); 6340 6341 /* 6342 * Setup leadtime for pre tbtt interrupt to 6ms 6343 */ 6344 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG); 6345 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); 6346 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); 6347 6348 /* 6349 * Set up channel statistics timer 6350 */ 6351 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG); 6352 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); 6353 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); 6354 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); 6355 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); 6356 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); 6357 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); 6358 6359 return 0; 6360} 6361 6362 6363static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) 6364{ 6365 u8 value; 6366 6367 value = rt2800_bbp_read(rt2x00dev, 4); 6368 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 6369 rt2800_bbp_write(rt2x00dev, 4, value); 6370} 6371 6372static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) 6373{ 6374 rt2800_bbp_write(rt2x00dev, 142, 1); 6375 rt2800_bbp_write(rt2x00dev, 143, 57); 6376} 6377 6378static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) 6379{ 6380 static const u8 glrt_table[] = { 6381 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ 6382 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ 6383 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ 6384 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */ 6385 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */ 6386 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */ 6387 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */ 6388 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */ 6389 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */ 6390 }; 6391 int i; 6392 6393 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) { 6394 rt2800_bbp_write(rt2x00dev, 195, 128 + i); 6395 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]); 6396 } 6397}; 6398 6399static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev) 6400{ 6401 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6402 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6403 rt2800_bbp_write(rt2x00dev, 68, 0x0B); 6404 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6405 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6406 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6407 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6408 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6409 rt2800_bbp_write(rt2x00dev, 83, 0x6A); 6410 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6411 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6412 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6413 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6414 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6415 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6416 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6417} 6418 6419static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) 6420{ 6421 u16 eeprom; 6422 u8 value; 6423 6424 value = rt2800_bbp_read(rt2x00dev, 138); 6425 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 6426 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 6427 value |= 0x20; 6428 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 6429 value &= ~0x02; 6430 rt2800_bbp_write(rt2x00dev, 138, value); 6431} 6432 6433static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev) 6434{ 6435 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6436 6437 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6438 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6439 6440 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6441 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6442 6443 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6444 6445 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6446 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6447 6448 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6449 6450 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6451 6452 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6453 6454 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6455 6456 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6457 6458 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6459 6460 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6461 6462 rt2800_bbp_write(rt2x00dev, 105, 0x01); 6463 6464 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6465} 6466 6467static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev) 6468{ 6469 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6470 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6471 6472 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 6473 rt2800_bbp_write(rt2x00dev, 69, 0x16); 6474 rt2800_bbp_write(rt2x00dev, 73, 0x12); 6475 } else { 6476 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6477 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6478 } 6479 6480 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6481 6482 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6483 6484 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6485 6486 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6487 6488 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 6489 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6490 else 6491 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6492 6493 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6494 6495 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6496 6497 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6498 6499 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6500 6501 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6502 6503 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6504} 6505 6506static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev) 6507{ 6508 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6509 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6510 6511 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6512 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6513 6514 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6515 6516 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6517 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6518 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6519 6520 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6521 6522 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6523 6524 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6525 6526 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6527 6528 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6529 6530 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6531 6532 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 6533 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 6534 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E)) 6535 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6536 else 6537 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6538 6539 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6540 6541 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6542 6543 if (rt2x00_rt(rt2x00dev, RT3071) || 6544 rt2x00_rt(rt2x00dev, RT3090)) 6545 rt2800_disable_unused_dac_adc(rt2x00dev); 6546} 6547 6548static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) 6549{ 6550 u8 value; 6551 6552 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6553 6554 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6555 6556 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6557 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6558 6559 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6560 6561 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6562 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6563 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6564 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6565 6566 rt2800_bbp_write(rt2x00dev, 77, 0x58); 6567 6568 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6569 6570 rt2800_bbp_write(rt2x00dev, 74, 0x0b); 6571 rt2800_bbp_write(rt2x00dev, 79, 0x18); 6572 rt2800_bbp_write(rt2x00dev, 80, 0x09); 6573 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6574 6575 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6576 6577 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6578 6579 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6580 6581 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6582 6583 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6584 6585 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6586 6587 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6588 6589 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6590 6591 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 6592 6593 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6594 6595 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6596 6597 rt2800_bbp_write(rt2x00dev, 67, 0x24); 6598 rt2800_bbp_write(rt2x00dev, 143, 0x04); 6599 rt2800_bbp_write(rt2x00dev, 142, 0x99); 6600 rt2800_bbp_write(rt2x00dev, 150, 0x30); 6601 rt2800_bbp_write(rt2x00dev, 151, 0x2e); 6602 rt2800_bbp_write(rt2x00dev, 152, 0x20); 6603 rt2800_bbp_write(rt2x00dev, 153, 0x34); 6604 rt2800_bbp_write(rt2x00dev, 154, 0x40); 6605 rt2800_bbp_write(rt2x00dev, 155, 0x3b); 6606 rt2800_bbp_write(rt2x00dev, 253, 0x04); 6607 6608 value = rt2800_bbp_read(rt2x00dev, 47); 6609 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); 6610 rt2800_bbp_write(rt2x00dev, 47, value); 6611 6612 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ 6613 value = rt2800_bbp_read(rt2x00dev, 3); 6614 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); 6615 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); 6616 rt2800_bbp_write(rt2x00dev, 3, value); 6617} 6618 6619static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) 6620{ 6621 rt2800_bbp_write(rt2x00dev, 3, 0x00); 6622 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6623 6624 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6625 6626 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6627 6628 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6629 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6630 6631 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6632 6633 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6634 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6635 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6636 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6637 6638 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6639 6640 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6641 6642 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6643 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6644 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6645 6646 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6647 6648 if (rt2x00_rt(rt2x00dev, RT5350)) { 6649 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6650 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6651 } else { 6652 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6653 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6654 } 6655 6656 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6657 6658 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6659 6660 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6661 6662 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6663 6664 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6665 6666 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6667 6668 if (rt2x00_rt(rt2x00dev, RT5350)) { 6669 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6670 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6671 } else { 6672 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6673 rt2800_bbp_write(rt2x00dev, 106, 0x05); 6674 } 6675 6676 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6677 6678 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6679 6680 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 6681 /* Set ITxBF timeout to 0x9c40=1000msec */ 6682 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6683 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6684 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6685 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6686 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6687 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6688 /* Reprogram the inband interface to put right values in RXWI */ 6689 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6690 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6691 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6692 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6693 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6694 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6695 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6696 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6697 6698 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6699 6700 if (rt2x00_rt(rt2x00dev, RT5350)) { 6701 /* Antenna Software OFDM */ 6702 rt2800_bbp_write(rt2x00dev, 150, 0x40); 6703 /* Antenna Software CCK */ 6704 rt2800_bbp_write(rt2x00dev, 151, 0x30); 6705 rt2800_bbp_write(rt2x00dev, 152, 0xa3); 6706 /* Clear previously selected antenna */ 6707 rt2800_bbp_write(rt2x00dev, 154, 0); 6708 } 6709} 6710 6711static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) 6712{ 6713 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6714 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6715 6716 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6717 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6718 6719 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6720 6721 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6722 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6723 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6724 6725 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6726 6727 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6728 6729 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6730 6731 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6732 6733 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6734 6735 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6736 6737 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E)) 6738 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6739 else 6740 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6741 6742 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6743 6744 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6745 6746 rt2800_disable_unused_dac_adc(rt2x00dev); 6747} 6748 6749static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev) 6750{ 6751 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6752 6753 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6754 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6755 6756 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6757 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6758 6759 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6760 6761 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6762 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6763 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6764 6765 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6766 6767 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6768 6769 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6770 6771 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6772 6773 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6774 6775 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6776 6777 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6778 6779 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6780 6781 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6782 6783 rt2800_disable_unused_dac_adc(rt2x00dev); 6784} 6785 6786static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev) 6787{ 6788 rt2800_init_bbp_early(rt2x00dev); 6789 6790 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6791 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6792 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6793 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6794 6795 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6796 6797 /* Enable DC filter */ 6798 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E)) 6799 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6800} 6801 6802static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev) 6803{ 6804 rt2800_init_bbp_early(rt2x00dev); 6805 6806 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6807 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6808 6809 rt2800_bbp_write(rt2x00dev, 86, 0x46); 6810 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6811 6812 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6813 6814 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6815 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6816 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6817 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6818 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6819 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6820 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 6821 6822 /* Set ITxBF timeout to 0x9C40=1000msec */ 6823 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6824 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6825 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6826 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6827 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6828 6829 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6830 6831 /* Reprogram the inband interface to put right values in RXWI */ 6832 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6833 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6834 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6835 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6836 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6837 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6838 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6839 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6840 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6841} 6842 6843static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) 6844{ 6845 int ant, div_mode; 6846 u16 eeprom; 6847 u8 value; 6848 6849 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6850 6851 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6852 6853 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6854 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6855 6856 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6857 6858 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6859 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6860 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6861 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6862 6863 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6864 6865 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6866 6867 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6868 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6869 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6870 6871 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6872 6873 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6874 6875 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6876 6877 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6878 6879 if (rt2x00_rt(rt2x00dev, RT5392)) 6880 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6881 6882 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6883 6884 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6885 6886 if (rt2x00_rt(rt2x00dev, RT5392)) { 6887 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6888 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6889 } 6890 6891 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6892 6893 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6894 6895 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6896 6897 if (rt2x00_rt(rt2x00dev, RT5390)) 6898 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6899 else if (rt2x00_rt(rt2x00dev, RT5392)) 6900 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6901 else 6902 WARN_ON(1); 6903 6904 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6905 6906 if (rt2x00_rt(rt2x00dev, RT5392)) { 6907 rt2800_bbp_write(rt2x00dev, 134, 0xd0); 6908 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 6909 } 6910 6911 rt2800_disable_unused_dac_adc(rt2x00dev); 6912 6913 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6914 div_mode = rt2x00_get_field16(eeprom, 6915 EEPROM_NIC_CONF1_ANT_DIVERSITY); 6916 ant = (div_mode == 3) ? 1 : 0; 6917 6918 /* check if this is a Bluetooth combo card */ 6919 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 6920 u32 reg; 6921 6922 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 6923 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 6924 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); 6925 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); 6926 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); 6927 if (ant == 0) 6928 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); 6929 else if (ant == 1) 6930 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); 6931 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 6932 } 6933 6934 /* These chips have hardware RX antenna diversity */ 6935 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 6936 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 6937 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */ 6938 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */ 6939 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ 6940 } 6941 6942 value = rt2800_bbp_read(rt2x00dev, 152); 6943 if (ant == 0) 6944 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6945 else 6946 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6947 rt2800_bbp_write(rt2x00dev, 152, value); 6948 6949 rt2800_init_freq_calibration(rt2x00dev); 6950} 6951 6952static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) 6953{ 6954 int ant, div_mode; 6955 u16 eeprom; 6956 u8 value; 6957 6958 rt2800_init_bbp_early(rt2x00dev); 6959 6960 value = rt2800_bbp_read(rt2x00dev, 105); 6961 rt2x00_set_field8(&value, BBP105_MLD, 6962 rt2x00dev->default_ant.rx_chain_num == 2); 6963 rt2800_bbp_write(rt2x00dev, 105, value); 6964 6965 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6966 6967 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6968 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6969 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6970 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6971 rt2800_bbp_write(rt2x00dev, 69, 0x1A); 6972 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6973 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6974 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6975 rt2800_bbp_write(rt2x00dev, 75, 0x4F); 6976 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6977 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6978 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6979 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6980 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6981 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6982 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6983 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6984 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6985 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6986 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6987 /* FIXME BBP105 owerwrite */ 6988 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6989 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6990 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6991 rt2800_bbp_write(rt2x00dev, 134, 0xD0); 6992 rt2800_bbp_write(rt2x00dev, 135, 0xF6); 6993 rt2800_bbp_write(rt2x00dev, 137, 0x0F); 6994 6995 /* Initialize GLRT (Generalized Likehood Radio Test) */ 6996 rt2800_init_bbp_5592_glrt(rt2x00dev); 6997 6998 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6999 7000 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 7001 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); 7002 ant = (div_mode == 3) ? 1 : 0; 7003 value = rt2800_bbp_read(rt2x00dev, 152); 7004 if (ant == 0) { 7005 /* Main antenna */ 7006 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 7007 } else { 7008 /* Auxiliary antenna */ 7009 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 7010 } 7011 rt2800_bbp_write(rt2x00dev, 152, value); 7012 7013 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { 7014 value = rt2800_bbp_read(rt2x00dev, 254); 7015 rt2x00_set_field8(&value, BBP254_BIT7, 1); 7016 rt2800_bbp_write(rt2x00dev, 254, value); 7017 } 7018 7019 rt2800_init_freq_calibration(rt2x00dev); 7020 7021 rt2800_bbp_write(rt2x00dev, 84, 0x19); 7022 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 7023 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 7024} 7025 7026static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev) 7027{ 7028 u8 bbp; 7029 7030 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */ 7031 bbp = rt2800_bbp_read(rt2x00dev, 105); 7032 rt2x00_set_field8(&bbp, BBP105_MLD, 7033 rt2x00dev->default_ant.rx_chain_num == 2); 7034 rt2800_bbp_write(rt2x00dev, 105, bbp); 7035 7036 /* Avoid data loss and CRC errors */ 7037 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7038 7039 /* Fix I/Q swap issue */ 7040 bbp = rt2800_bbp_read(rt2x00dev, 1); 7041 bbp |= 0x04; 7042 rt2800_bbp_write(rt2x00dev, 1, bbp); 7043 7044 /* BBP for G band */ 7045 rt2800_bbp_write(rt2x00dev, 3, 0x08); 7046 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */ 7047 rt2800_bbp_write(rt2x00dev, 6, 0x08); 7048 rt2800_bbp_write(rt2x00dev, 14, 0x09); 7049 rt2800_bbp_write(rt2x00dev, 15, 0xFF); 7050 rt2800_bbp_write(rt2x00dev, 16, 0x01); 7051 rt2800_bbp_write(rt2x00dev, 20, 0x06); 7052 rt2800_bbp_write(rt2x00dev, 21, 0x00); 7053 rt2800_bbp_write(rt2x00dev, 22, 0x00); 7054 rt2800_bbp_write(rt2x00dev, 27, 0x00); 7055 rt2800_bbp_write(rt2x00dev, 28, 0x00); 7056 rt2800_bbp_write(rt2x00dev, 30, 0x00); 7057 rt2800_bbp_write(rt2x00dev, 31, 0x48); 7058 rt2800_bbp_write(rt2x00dev, 47, 0x40); 7059 rt2800_bbp_write(rt2x00dev, 62, 0x00); 7060 rt2800_bbp_write(rt2x00dev, 63, 0x00); 7061 rt2800_bbp_write(rt2x00dev, 64, 0x00); 7062 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 7063 rt2800_bbp_write(rt2x00dev, 66, 0x1C); 7064 rt2800_bbp_write(rt2x00dev, 67, 0x20); 7065 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 7066 rt2800_bbp_write(rt2x00dev, 69, 0x10); 7067 rt2800_bbp_write(rt2x00dev, 70, 0x05); 7068 rt2800_bbp_write(rt2x00dev, 73, 0x18); 7069 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 7070 rt2800_bbp_write(rt2x00dev, 75, 0x60); 7071 rt2800_bbp_write(rt2x00dev, 76, 0x44); 7072 rt2800_bbp_write(rt2x00dev, 77, 0x59); 7073 rt2800_bbp_write(rt2x00dev, 78, 0x1E); 7074 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 7075 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 7076 rt2800_bbp_write(rt2x00dev, 81, 0x3A); 7077 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 7078 rt2800_bbp_write(rt2x00dev, 83, 0x9A); 7079 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 7080 rt2800_bbp_write(rt2x00dev, 86, 0x38); 7081 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7082 rt2800_bbp_write(rt2x00dev, 91, 0x04); 7083 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7084 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 7085 rt2800_bbp_write(rt2x00dev, 96, 0x00); 7086 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 7087 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7088 /* FIXME BBP105 owerwrite */ 7089 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 7090 rt2800_bbp_write(rt2x00dev, 106, 0x12); 7091 rt2800_bbp_write(rt2x00dev, 109, 0x00); 7092 rt2800_bbp_write(rt2x00dev, 134, 0x10); 7093 rt2800_bbp_write(rt2x00dev, 135, 0xA6); 7094 rt2800_bbp_write(rt2x00dev, 137, 0x04); 7095 rt2800_bbp_write(rt2x00dev, 142, 0x30); 7096 rt2800_bbp_write(rt2x00dev, 143, 0xF7); 7097 rt2800_bbp_write(rt2x00dev, 160, 0xEC); 7098 rt2800_bbp_write(rt2x00dev, 161, 0xC4); 7099 rt2800_bbp_write(rt2x00dev, 162, 0x77); 7100 rt2800_bbp_write(rt2x00dev, 163, 0xF9); 7101 rt2800_bbp_write(rt2x00dev, 164, 0x00); 7102 rt2800_bbp_write(rt2x00dev, 165, 0x00); 7103 rt2800_bbp_write(rt2x00dev, 186, 0x00); 7104 rt2800_bbp_write(rt2x00dev, 187, 0x00); 7105 rt2800_bbp_write(rt2x00dev, 188, 0x00); 7106 rt2800_bbp_write(rt2x00dev, 186, 0x00); 7107 rt2800_bbp_write(rt2x00dev, 187, 0x01); 7108 rt2800_bbp_write(rt2x00dev, 188, 0x00); 7109 rt2800_bbp_write(rt2x00dev, 189, 0x00); 7110 7111 rt2800_bbp_write(rt2x00dev, 91, 0x06); 7112 rt2800_bbp_write(rt2x00dev, 92, 0x04); 7113 rt2800_bbp_write(rt2x00dev, 93, 0x54); 7114 rt2800_bbp_write(rt2x00dev, 99, 0x50); 7115 rt2800_bbp_write(rt2x00dev, 148, 0x84); 7116 rt2800_bbp_write(rt2x00dev, 167, 0x80); 7117 rt2800_bbp_write(rt2x00dev, 178, 0xFF); 7118 rt2800_bbp_write(rt2x00dev, 106, 0x13); 7119 7120 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */ 7121 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00); 7122 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14); 7123 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20); 7124 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A); 7125 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16); 7126 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06); 7127 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02); 7128 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07); 7129 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05); 7130 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09); 7131 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20); 7132 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08); 7133 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A); 7134 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00); 7135 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00); 7136 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0); 7137 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F); 7138 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F); 7139 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32); 7140 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08); 7141 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28); 7142 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19); 7143 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A); 7144 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16); 7145 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10); 7146 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10); 7147 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A); 7148 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36); 7149 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C); 7150 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26); 7151 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24); 7152 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42); 7153 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40); 7154 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30); 7155 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29); 7156 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C); 7157 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46); 7158 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D); 7159 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40); 7160 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E); 7161 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38); 7162 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D); 7163 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F); 7164 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C); 7165 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34); 7166 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C); 7167 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F); 7168 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C); 7169 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35); 7170 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E); 7171 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F); 7172 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49); 7173 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41); 7174 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36); 7175 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39); 7176 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30); 7177 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30); 7178 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E); 7179 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D); 7180 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28); 7181 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21); 7182 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C); 7183 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16); 7184 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50); 7185 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A); 7186 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43); 7187 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50); 7188 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10); 7189 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10); 7190 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10); 7191 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10); 7192 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D); 7193 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14); 7194 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32); 7195 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C); 7196 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36); 7197 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C); 7198 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43); 7199 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C); 7200 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E); 7201 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36); 7202 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30); 7203 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E); 7204 7205 /* BBP for G band DCOC function */ 7206 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C); 7207 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00); 7208 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10); 7209 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10); 7210 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10); 7211 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10); 7212 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08); 7213 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40); 7214 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04); 7215 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04); 7216 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08); 7217 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08); 7218 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03); 7219 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03); 7220 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03); 7221 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02); 7222 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40); 7223 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40); 7224 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64); 7225 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64); 7226 7227 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7228} 7229 7230static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 7231{ 7232 unsigned int i; 7233 u16 eeprom; 7234 u8 reg_id; 7235 u8 value; 7236 7237 if (rt2800_is_305x_soc(rt2x00dev)) 7238 rt2800_init_bbp_305x_soc(rt2x00dev); 7239 7240 switch (rt2x00dev->chip.rt) { 7241 case RT2860: 7242 case RT2872: 7243 case RT2883: 7244 rt2800_init_bbp_28xx(rt2x00dev); 7245 break; 7246 case RT3070: 7247 case RT3071: 7248 case RT3090: 7249 rt2800_init_bbp_30xx(rt2x00dev); 7250 break; 7251 case RT3290: 7252 rt2800_init_bbp_3290(rt2x00dev); 7253 break; 7254 case RT3352: 7255 case RT5350: 7256 rt2800_init_bbp_3352(rt2x00dev); 7257 break; 7258 case RT3390: 7259 rt2800_init_bbp_3390(rt2x00dev); 7260 break; 7261 case RT3572: 7262 rt2800_init_bbp_3572(rt2x00dev); 7263 break; 7264 case RT3593: 7265 rt2800_init_bbp_3593(rt2x00dev); 7266 return; 7267 case RT3883: 7268 rt2800_init_bbp_3883(rt2x00dev); 7269 return; 7270 case RT5390: 7271 case RT5392: 7272 rt2800_init_bbp_53xx(rt2x00dev); 7273 break; 7274 case RT5592: 7275 rt2800_init_bbp_5592(rt2x00dev); 7276 return; 7277 case RT6352: 7278 rt2800_init_bbp_6352(rt2x00dev); 7279 break; 7280 } 7281 7282 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 7283 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 7284 EEPROM_BBP_START, i); 7285 7286 if (eeprom != 0xffff && eeprom != 0x0000) { 7287 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 7288 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 7289 rt2800_bbp_write(rt2x00dev, reg_id, value); 7290 } 7291 } 7292} 7293 7294static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) 7295{ 7296 u32 reg; 7297 7298 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR); 7299 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); 7300 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 7301} 7302 7303static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, 7304 u8 filter_target) 7305{ 7306 unsigned int i; 7307 u8 bbp; 7308 u8 rfcsr; 7309 u8 passband; 7310 u8 stopband; 7311 u8 overtuned = 0; 7312 u8 rfcsr24 = (bw40) ? 0x27 : 0x07; 7313 7314 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7315 7316 bbp = rt2800_bbp_read(rt2x00dev, 4); 7317 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 7318 rt2800_bbp_write(rt2x00dev, 4, bbp); 7319 7320 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 7321 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); 7322 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 7323 7324 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 7325 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 7326 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 7327 7328 /* 7329 * Set power & frequency of passband test tone 7330 */ 7331 rt2800_bbp_write(rt2x00dev, 24, 0); 7332 7333 for (i = 0; i < 100; i++) { 7334 rt2800_bbp_write(rt2x00dev, 25, 0x90); 7335 msleep(1); 7336 7337 passband = rt2800_bbp_read(rt2x00dev, 55); 7338 if (passband) 7339 break; 7340 } 7341 7342 /* 7343 * Set power & frequency of stopband test tone 7344 */ 7345 rt2800_bbp_write(rt2x00dev, 24, 0x06); 7346 7347 for (i = 0; i < 100; i++) { 7348 rt2800_bbp_write(rt2x00dev, 25, 0x90); 7349 msleep(1); 7350 7351 stopband = rt2800_bbp_read(rt2x00dev, 55); 7352 7353 if ((passband - stopband) <= filter_target) { 7354 rfcsr24++; 7355 overtuned += ((passband - stopband) == filter_target); 7356 } else 7357 break; 7358 7359 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7360 } 7361 7362 rfcsr24 -= !!overtuned; 7363 7364 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7365 return rfcsr24; 7366} 7367 7368static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, 7369 const unsigned int rf_reg) 7370{ 7371 u8 rfcsr; 7372 7373 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg); 7374 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); 7375 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 7376 msleep(1); 7377 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0); 7378 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 7379} 7380 7381static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) 7382{ 7383 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7384 u8 filter_tgt_bw20; 7385 u8 filter_tgt_bw40; 7386 u8 rfcsr, bbp; 7387 7388 /* 7389 * TODO: sync filter_tgt values with vendor driver 7390 */ 7391 if (rt2x00_rt(rt2x00dev, RT3070)) { 7392 filter_tgt_bw20 = 0x16; 7393 filter_tgt_bw40 = 0x19; 7394 } else { 7395 filter_tgt_bw20 = 0x13; 7396 filter_tgt_bw40 = 0x15; 7397 } 7398 7399 drv_data->calibration_bw20 = 7400 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20); 7401 drv_data->calibration_bw40 = 7402 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40); 7403 7404 /* 7405 * Save BBP 25 & 26 values for later use in channel switching (for 3052) 7406 */ 7407 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 7408 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 7409 7410 /* 7411 * Set back to initial state 7412 */ 7413 rt2800_bbp_write(rt2x00dev, 24, 0); 7414 7415 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 7416 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 7417 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 7418 7419 /* 7420 * Set BBP back to BW20 7421 */ 7422 bbp = rt2800_bbp_read(rt2x00dev, 4); 7423 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 7424 rt2800_bbp_write(rt2x00dev, 4, bbp); 7425} 7426 7427static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) 7428{ 7429 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7430 u8 min_gain, rfcsr, bbp; 7431 u16 eeprom; 7432 7433 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 7434 7435 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 7436 if (rt2x00_rt(rt2x00dev, RT3070) || 7437 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7438 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 7439 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 7440 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev)) 7441 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 7442 } 7443 7444 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2; 7445 if (drv_data->txmixer_gain_24g >= min_gain) { 7446 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 7447 drv_data->txmixer_gain_24g); 7448 } 7449 7450 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 7451 7452 if (rt2x00_rt(rt2x00dev, RT3090)) { 7453 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7454 bbp = rt2800_bbp_read(rt2x00dev, 138); 7455 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7456 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7457 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 7458 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7459 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 7460 rt2800_bbp_write(rt2x00dev, 138, bbp); 7461 } 7462 7463 if (rt2x00_rt(rt2x00dev, RT3070)) { 7464 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27); 7465 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) 7466 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 7467 else 7468 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 7469 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); 7470 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); 7471 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); 7472 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 7473 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7474 rt2x00_rt(rt2x00dev, RT3090) || 7475 rt2x00_rt(rt2x00dev, RT3390)) { 7476 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 7477 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 7478 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 7479 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 7480 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 7481 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 7482 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 7483 7484 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15); 7485 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); 7486 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); 7487 7488 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 7489 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); 7490 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 7491 7492 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 7493 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); 7494 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 7495 } 7496} 7497 7498static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) 7499{ 7500 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7501 u8 rfcsr; 7502 u8 tx_gain; 7503 7504 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 7505 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); 7506 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7507 7508 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 7509 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, 7510 RFCSR17_TXMIXER_GAIN); 7511 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); 7512 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 7513 7514 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38); 7515 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); 7516 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); 7517 7518 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39); 7519 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); 7520 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 7521 7522 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 7523 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 7524 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 7525 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 7526 7527 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 7528 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 7529 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 7530 7531 /* TODO: enable stream mode */ 7532} 7533 7534static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) 7535{ 7536 u8 reg; 7537 u16 eeprom; 7538 7539 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7540 reg = rt2800_bbp_read(rt2x00dev, 138); 7541 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7542 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7543 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); 7544 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7545 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); 7546 rt2800_bbp_write(rt2x00dev, 138, reg); 7547 7548 reg = rt2800_rfcsr_read(rt2x00dev, 38); 7549 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); 7550 rt2800_rfcsr_write(rt2x00dev, 38, reg); 7551 7552 reg = rt2800_rfcsr_read(rt2x00dev, 39); 7553 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); 7554 rt2800_rfcsr_write(rt2x00dev, 39, reg); 7555 7556 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7557 7558 reg = rt2800_rfcsr_read(rt2x00dev, 30); 7559 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); 7560 rt2800_rfcsr_write(rt2x00dev, 30, reg); 7561} 7562 7563static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) 7564{ 7565 rt2800_rf_init_calibration(rt2x00dev, 30); 7566 7567 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 7568 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 7569 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 7570 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 7571 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7572 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7573 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7574 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 7575 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 7576 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7577 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 7578 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7579 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 7580 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 7581 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7582 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7583 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7584 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7585 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7586 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7587 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7588 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7589 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7590 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 7591 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7592 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 7593 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 7594 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 7595 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 7596 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 7597 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 7598 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 7599} 7600 7601static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) 7602{ 7603 u8 rfcsr; 7604 u16 eeprom; 7605 u32 reg; 7606 7607 /* XXX vendor driver do this only for 3070 */ 7608 rt2800_rf_init_calibration(rt2x00dev, 30); 7609 7610 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7611 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7612 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7613 rt2800_rfcsr_write(rt2x00dev, 7, 0x60); 7614 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7615 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 7616 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7617 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 7618 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7619 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7620 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7621 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7622 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7623 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7624 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7625 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7626 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7627 rt2800_rfcsr_write(rt2x00dev, 25, 0x03); 7628 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 7629 7630 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 7631 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7632 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7633 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7634 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7635 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7636 rt2x00_rt(rt2x00dev, RT3090)) { 7637 rt2800_rfcsr_write(rt2x00dev, 31, 0x14); 7638 7639 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7640 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7641 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7642 7643 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7644 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7645 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7646 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 7647 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 7648 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 7649 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7650 else 7651 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7652 } 7653 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7654 7655 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7656 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7657 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7658 } 7659 7660 rt2800_rx_filter_calibration(rt2x00dev); 7661 7662 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 7663 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7664 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) 7665 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7666 7667 rt2800_led_open_drain_enable(rt2x00dev); 7668 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7669} 7670 7671static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) 7672{ 7673 u8 rfcsr; 7674 7675 rt2800_rf_init_calibration(rt2x00dev, 2); 7676 7677 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 7678 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7679 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7680 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7681 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 7682 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); 7683 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7684 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7685 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7686 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7687 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7688 rt2800_rfcsr_write(rt2x00dev, 18, 0x02); 7689 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7690 rt2800_rfcsr_write(rt2x00dev, 25, 0x83); 7691 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7692 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7693 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7694 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7695 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7696 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7697 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7698 rt2800_rfcsr_write(rt2x00dev, 34, 0x05); 7699 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7700 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7701 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7702 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7703 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7704 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7705 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7706 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); 7707 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7708 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7709 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7710 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7711 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7712 rt2800_rfcsr_write(rt2x00dev, 49, 0x98); 7713 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7714 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7715 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 7716 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7717 rt2800_rfcsr_write(rt2x00dev, 56, 0x02); 7718 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 7719 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 7720 rt2800_rfcsr_write(rt2x00dev, 59, 0x09); 7721 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7722 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); 7723 7724 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29); 7725 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); 7726 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); 7727 7728 rt2800_led_open_drain_enable(rt2x00dev); 7729 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7730} 7731 7732static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) 7733{ 7734 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0, 7735 &rt2x00dev->cap_flags); 7736 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1, 7737 &rt2x00dev->cap_flags); 7738 u8 rfcsr; 7739 7740 rt2800_rf_init_calibration(rt2x00dev, 30); 7741 7742 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7743 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7744 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7745 rt2800_rfcsr_write(rt2x00dev, 3, 0x18); 7746 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7747 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7748 rt2800_rfcsr_write(rt2x00dev, 6, 0x33); 7749 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7750 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7751 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7752 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); 7753 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 7754 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 7755 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 7756 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); 7757 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7758 rt2800_rfcsr_write(rt2x00dev, 16, 0x01); 7759 rt2800_rfcsr_write(rt2x00dev, 18, 0x45); 7760 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7761 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7762 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7763 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7764 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7765 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7766 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7767 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7768 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7769 rt2800_rfcsr_write(rt2x00dev, 28, 0x03); 7770 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 7771 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7772 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7773 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7774 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7775 rfcsr = 0x01; 7776 if (tx0_ext_pa) 7777 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1); 7778 if (tx1_ext_pa) 7779 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1); 7780 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 7781 rt2800_rfcsr_write(rt2x00dev, 35, 0x03); 7782 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); 7783 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); 7784 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); 7785 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); 7786 rt2800_rfcsr_write(rt2x00dev, 40, 0x33); 7787 rfcsr = 0x52; 7788 if (!tx0_ext_pa) { 7789 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1); 7790 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1); 7791 } 7792 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr); 7793 rfcsr = 0x52; 7794 if (!tx1_ext_pa) { 7795 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1); 7796 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1); 7797 } 7798 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 7799 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); 7800 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); 7801 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); 7802 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); 7803 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); 7804 rt2800_rfcsr_write(rt2x00dev, 48, 0x14); 7805 rt2800_rfcsr_write(rt2x00dev, 49, 0x00); 7806 rfcsr = 0x2d; 7807 if (tx0_ext_pa) 7808 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1); 7809 if (tx1_ext_pa) 7810 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1); 7811 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7812 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f)); 7813 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00)); 7814 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52)); 7815 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b)); 7816 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f)); 7817 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00)); 7818 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52)); 7819 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b)); 7820 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 7821 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 7822 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 7823 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7824 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7825 7826 rt2800_rx_filter_calibration(rt2x00dev); 7827 rt2800_led_open_drain_enable(rt2x00dev); 7828 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7829} 7830 7831static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) 7832{ 7833 u32 reg; 7834 7835 rt2800_rf_init_calibration(rt2x00dev, 30); 7836 7837 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 7838 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 7839 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7840 rt2800_rfcsr_write(rt2x00dev, 3, 0x62); 7841 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7842 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); 7843 rt2800_rfcsr_write(rt2x00dev, 6, 0x42); 7844 rt2800_rfcsr_write(rt2x00dev, 7, 0x34); 7845 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 7846 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 7847 rt2800_rfcsr_write(rt2x00dev, 10, 0x61); 7848 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7849 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); 7850 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); 7851 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7852 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7853 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); 7854 rt2800_rfcsr_write(rt2x00dev, 17, 0x94); 7855 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); 7856 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); 7857 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); 7858 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); 7859 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7860 rt2800_rfcsr_write(rt2x00dev, 23, 0x14); 7861 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7862 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 7863 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7864 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7865 rt2800_rfcsr_write(rt2x00dev, 28, 0x41); 7866 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 7867 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 7868 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 7869 7870 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7871 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7872 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7873 7874 rt2800_rx_filter_calibration(rt2x00dev); 7875 7876 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) 7877 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7878 7879 rt2800_led_open_drain_enable(rt2x00dev); 7880 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7881} 7882 7883static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) 7884{ 7885 u8 rfcsr; 7886 u32 reg; 7887 7888 rt2800_rf_init_calibration(rt2x00dev, 30); 7889 7890 rt2800_rfcsr_write(rt2x00dev, 0, 0x70); 7891 rt2800_rfcsr_write(rt2x00dev, 1, 0x81); 7892 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7893 rt2800_rfcsr_write(rt2x00dev, 3, 0x02); 7894 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); 7895 rt2800_rfcsr_write(rt2x00dev, 5, 0x05); 7896 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); 7897 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 7898 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 7899 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 7900 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 7901 rt2800_rfcsr_write(rt2x00dev, 12, 0x70); 7902 rt2800_rfcsr_write(rt2x00dev, 13, 0x65); 7903 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); 7904 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7905 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); 7906 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 7907 rt2800_rfcsr_write(rt2x00dev, 18, 0xac); 7908 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 7909 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 7910 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); 7911 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7912 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); 7913 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7914 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 7915 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7916 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7917 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7918 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 7919 rt2800_rfcsr_write(rt2x00dev, 30, 0x09); 7920 rt2800_rfcsr_write(rt2x00dev, 31, 0x10); 7921 7922 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7923 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7924 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7925 7926 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7927 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7928 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7929 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7930 msleep(1); 7931 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7932 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7933 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7934 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7935 7936 rt2800_rx_filter_calibration(rt2x00dev); 7937 rt2800_led_open_drain_enable(rt2x00dev); 7938 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7939} 7940 7941static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) 7942{ 7943 u8 bbp; 7944 bool txbf_enabled = false; /* FIXME */ 7945 7946 bbp = rt2800_bbp_read(rt2x00dev, 105); 7947 if (rt2x00dev->default_ant.rx_chain_num == 1) 7948 rt2x00_set_field8(&bbp, BBP105_MLD, 0); 7949 else 7950 rt2x00_set_field8(&bbp, BBP105_MLD, 1); 7951 rt2800_bbp_write(rt2x00dev, 105, bbp); 7952 7953 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7954 7955 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7956 rt2800_bbp_write(rt2x00dev, 82, 0x82); 7957 rt2800_bbp_write(rt2x00dev, 106, 0x05); 7958 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7959 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7960 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 7961 rt2800_bbp_write(rt2x00dev, 47, 0x48); 7962 rt2800_bbp_write(rt2x00dev, 120, 0x50); 7963 7964 if (txbf_enabled) 7965 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 7966 else 7967 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 7968 7969 /* SNR mapping */ 7970 rt2800_bbp_write(rt2x00dev, 142, 6); 7971 rt2800_bbp_write(rt2x00dev, 143, 160); 7972 rt2800_bbp_write(rt2x00dev, 142, 7); 7973 rt2800_bbp_write(rt2x00dev, 143, 161); 7974 rt2800_bbp_write(rt2x00dev, 142, 8); 7975 rt2800_bbp_write(rt2x00dev, 143, 162); 7976 7977 /* ADC/DAC control */ 7978 rt2800_bbp_write(rt2x00dev, 31, 0x08); 7979 7980 /* RX AGC energy lower bound in log2 */ 7981 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 7982 7983 /* FIXME: BBP 105 owerwrite? */ 7984 rt2800_bbp_write(rt2x00dev, 105, 0x04); 7985 7986} 7987 7988static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) 7989{ 7990 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7991 u32 reg; 7992 u8 rfcsr; 7993 7994 /* Disable GPIO #4 and #7 function for LAN PE control */ 7995 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7996 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); 7997 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); 7998 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7999 8000 /* Initialize default register values */ 8001 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 8002 rt2800_rfcsr_write(rt2x00dev, 3, 0x80); 8003 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 8004 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 8005 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 8006 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 8007 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 8008 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 8009 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e); 8010 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 8011 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 8012 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8013 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8014 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8015 rt2800_rfcsr_write(rt2x00dev, 32, 0x78); 8016 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b); 8017 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 8018 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0); 8019 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 8020 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 8021 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3); 8022 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 8023 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 8024 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 8025 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 8026 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 8027 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 8028 rt2800_rfcsr_write(rt2x00dev, 53, 0x18); 8029 rt2800_rfcsr_write(rt2x00dev, 54, 0x18); 8030 rt2800_rfcsr_write(rt2x00dev, 55, 0x18); 8031 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 8032 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 8033 8034 /* Initiate calibration */ 8035 /* TODO: use rt2800_rf_init_calibration ? */ 8036 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 8037 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 8038 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8039 8040 rt2800_freq_cal_mode1(rt2x00dev); 8041 8042 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 8043 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); 8044 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 8045 8046 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 8047 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 8048 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 8049 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 8050 usleep_range(1000, 1500); 8051 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 8052 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 8053 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 8054 8055 /* Set initial values for RX filter calibration */ 8056 drv_data->calibration_bw20 = 0x1f; 8057 drv_data->calibration_bw40 = 0x2f; 8058 8059 /* Save BBP 25 & 26 values for later use in channel switching */ 8060 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 8061 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 8062 8063 rt2800_led_open_drain_enable(rt2x00dev); 8064 rt2800_normal_mode_setup_3593(rt2x00dev); 8065 8066 rt3593_post_bbp_init(rt2x00dev); 8067 8068 /* TODO: enable stream mode support */ 8069} 8070 8071static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev) 8072{ 8073 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 8074 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 8075 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 8076 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 8077 rt2800_rfcsr_write(rt2x00dev, 4, 0x49); 8078 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8079 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8080 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8081 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 8082 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 8083 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8084 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8085 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8086 if (rt2800_clk_is_20mhz(rt2x00dev)) 8087 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f); 8088 else 8089 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8090 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8091 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8092 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0); 8093 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8094 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8095 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8096 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8097 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8098 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 8099 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8100 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8101 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8102 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 8103 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8104 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0); 8105 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8106 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8107 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8108 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8109 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8110 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8111 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8112 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8113 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 8114 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8115 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 8116 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8117 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 8118 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 8119 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c); 8120 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6); 8121 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8122 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8123 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8124 rt2800_rfcsr_write(rt2x00dev, 49, 0x80); 8125 rt2800_rfcsr_write(rt2x00dev, 50, 0x00); 8126 rt2800_rfcsr_write(rt2x00dev, 51, 0x00); 8127 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 8128 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 8129 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 8130 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 8131 rt2800_rfcsr_write(rt2x00dev, 56, 0x82); 8132 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 8133 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 8134 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b); 8135 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8136 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 8137 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8138 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8139} 8140 8141static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev) 8142{ 8143 u8 rfcsr; 8144 8145 /* TODO: get the actual ECO value from the SoC */ 8146 const unsigned int eco = 5; 8147 8148 rt2800_rf_init_calibration(rt2x00dev, 2); 8149 8150 rt2800_rfcsr_write(rt2x00dev, 0, 0xe0); 8151 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 8152 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 8153 rt2800_rfcsr_write(rt2x00dev, 3, 0x20); 8154 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 8155 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 8156 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 8157 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8158 rt2800_rfcsr_write(rt2x00dev, 8, 0x5b); 8159 rt2800_rfcsr_write(rt2x00dev, 9, 0x08); 8160 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 8161 rt2800_rfcsr_write(rt2x00dev, 11, 0x48); 8162 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a); 8163 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 8164 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8165 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8166 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8167 8168 /* RFCSR 17 will be initialized later based on the 8169 * frequency offset stored in the EEPROM 8170 */ 8171 8172 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 8173 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8174 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8175 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8176 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8177 rt2800_rfcsr_write(rt2x00dev, 23, 0xc0); 8178 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8179 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 8180 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8181 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8182 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8183 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 8184 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8185 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8186 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8187 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8188 rt2800_rfcsr_write(rt2x00dev, 34, 0x20); 8189 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 8190 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8191 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 8192 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 8193 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 8194 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 8195 rt2800_rfcsr_write(rt2x00dev, 41, 0x00); 8196 rt2800_rfcsr_write(rt2x00dev, 42, 0x00); 8197 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 8198 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 8199 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 8200 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 8201 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8202 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 8203 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 8204 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 8205 rt2800_rfcsr_write(rt2x00dev, 51, 0x51); 8206 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 8207 rt2800_rfcsr_write(rt2x00dev, 53, 0x76); 8208 rt2800_rfcsr_write(rt2x00dev, 54, 0x76); 8209 rt2800_rfcsr_write(rt2x00dev, 55, 0x76); 8210 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 8211 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e); 8212 rt2800_rfcsr_write(rt2x00dev, 58, 0x00); 8213 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 8214 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 8215 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 8216 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8217 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8218 8219 /* TODO: rx filter calibration? */ 8220 8221 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 8222 8223 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 8224 8225 rt2800_bbp_write(rt2x00dev, 105, 0x05); 8226 8227 rt2800_bbp_write(rt2x00dev, 179, 0x02); 8228 rt2800_bbp_write(rt2x00dev, 180, 0x00); 8229 rt2800_bbp_write(rt2x00dev, 182, 0x40); 8230 rt2800_bbp_write(rt2x00dev, 180, 0x01); 8231 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 8232 8233 rt2800_bbp_write(rt2x00dev, 179, 0x00); 8234 8235 rt2800_bbp_write(rt2x00dev, 142, 0x04); 8236 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 8237 rt2800_bbp_write(rt2x00dev, 142, 0x06); 8238 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 8239 rt2800_bbp_write(rt2x00dev, 142, 0x07); 8240 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 8241 rt2800_bbp_write(rt2x00dev, 142, 0x08); 8242 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 8243 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 8244 8245 if (eco == 5) { 8246 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8); 8247 rt2800_rfcsr_write(rt2x00dev, 33, 0x32); 8248 } 8249 8250 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 8251 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0); 8252 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 8253 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8254 msleep(1); 8255 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0); 8256 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8257 8258 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 8259 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 8260 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 8261 8262 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 8263 rfcsr |= 0xc0; 8264 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 8265 8266 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 8267 rfcsr |= 0x20; 8268 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 8269 8270 rfcsr = rt2800_rfcsr_read(rt2x00dev, 46); 8271 rfcsr |= 0x20; 8272 rt2800_rfcsr_write(rt2x00dev, 46, rfcsr); 8273 8274 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 8275 rfcsr &= ~0xee; 8276 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 8277} 8278 8279static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) 8280{ 8281 rt2800_rf_init_calibration(rt2x00dev, 2); 8282 8283 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 8284 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 8285 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 8286 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8287 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8288 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8289 else 8290 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 8291 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8292 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8293 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8294 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8295 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8296 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8297 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8298 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8299 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8300 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8301 8302 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8303 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8304 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8305 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 8306 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8307 if (rt2x00_is_usb(rt2x00dev) && 8308 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8309 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8310 else 8311 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); 8312 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8313 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 8314 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8315 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8316 8317 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8318 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8319 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8320 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8321 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8322 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8323 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8324 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8325 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 8326 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8327 8328 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 8329 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8330 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); 8331 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); 8332 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 8333 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 8334 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8335 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8336 else 8337 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); 8338 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8339 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8340 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 8341 8342 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 8343 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8344 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 8345 else 8346 rt2800_rfcsr_write(rt2x00dev, 53, 0x84); 8347 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 8348 rt2800_rfcsr_write(rt2x00dev, 55, 0x44); 8349 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8350 rt2800_rfcsr_write(rt2x00dev, 56, 0x42); 8351 else 8352 rt2800_rfcsr_write(rt2x00dev, 56, 0x22); 8353 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 8354 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 8355 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f); 8356 8357 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8358 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 8359 if (rt2x00_is_usb(rt2x00dev)) 8360 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 8361 else 8362 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5); 8363 } else { 8364 if (rt2x00_is_usb(rt2x00dev)) 8365 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 8366 else 8367 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5); 8368 } 8369 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8370 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8371 8372 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8373 8374 rt2800_led_open_drain_enable(rt2x00dev); 8375} 8376 8377static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) 8378{ 8379 rt2800_rf_init_calibration(rt2x00dev, 2); 8380 8381 rt2800_rfcsr_write(rt2x00dev, 1, 0x17); 8382 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 8383 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8384 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8385 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8386 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8387 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8388 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8389 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8390 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8391 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8392 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8393 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8394 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); 8395 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8396 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); 8397 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8398 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); 8399 rt2800_rfcsr_write(rt2x00dev, 24, 0x44); 8400 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8401 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 8402 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 8403 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8404 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8405 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8406 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8407 rt2800_rfcsr_write(rt2x00dev, 32, 0x20); 8408 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 8409 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8410 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8411 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8412 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8413 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 8414 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8415 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); 8416 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8417 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 8418 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 8419 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 8420 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 8421 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8422 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); 8423 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8424 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 8425 rt2800_rfcsr_write(rt2x00dev, 50, 0x94); 8426 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); 8427 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 8428 rt2800_rfcsr_write(rt2x00dev, 53, 0x44); 8429 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 8430 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 8431 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); 8432 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 8433 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 8434 rt2800_rfcsr_write(rt2x00dev, 59, 0x07); 8435 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8436 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 8437 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 8438 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 8439 8440 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8441 8442 rt2800_led_open_drain_enable(rt2x00dev); 8443} 8444 8445static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) 8446{ 8447 rt2800_rf_init_calibration(rt2x00dev, 30); 8448 8449 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F); 8450 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 8451 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8452 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4); 8453 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8454 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8455 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8456 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8457 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8458 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D); 8459 rt2800_rfcsr_write(rt2x00dev, 20, 0x10); 8460 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D); 8461 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 8462 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8463 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8464 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 8465 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8466 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8467 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C); 8468 rt2800_rfcsr_write(rt2x00dev, 53, 0x22); 8469 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 8470 8471 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 8472 msleep(1); 8473 8474 rt2800_freq_cal_mode1(rt2x00dev); 8475 8476 /* Enable DC filter */ 8477 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 8478 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 8479 8480 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8481 8482 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C)) 8483 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 8484 8485 rt2800_led_open_drain_enable(rt2x00dev); 8486} 8487 8488static void rt2800_rf_self_txdc_cal(struct rt2x00_dev *rt2x00dev) 8489{ 8490 u8 rfb5r1_org, rfb7r1_org, rfvalue; 8491 u32 mac0518, mac051c, mac0528, mac052c; 8492 u8 i; 8493 8494 mac0518 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 8495 mac051c = rt2800_register_read(rt2x00dev, RF_BYPASS0); 8496 mac0528 = rt2800_register_read(rt2x00dev, RF_CONTROL2); 8497 mac052c = rt2800_register_read(rt2x00dev, RF_BYPASS2); 8498 8499 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0); 8500 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0); 8501 8502 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0xC); 8503 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x3306); 8504 rt2800_register_write(rt2x00dev, RF_CONTROL2, 0x3330); 8505 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0xfffff); 8506 rfb5r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8507 rfb7r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1); 8508 8509 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, 0x4); 8510 for (i = 0; i < 100; ++i) { 8511 usleep_range(50, 100); 8512 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8513 if ((rfvalue & 0x04) != 0x4) 8514 break; 8515 } 8516 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rfb5r1_org); 8517 8518 rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, 0x4); 8519 for (i = 0; i < 100; ++i) { 8520 usleep_range(50, 100); 8521 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1); 8522 if ((rfvalue & 0x04) != 0x4) 8523 break; 8524 } 8525 rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, rfb7r1_org); 8526 8527 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0); 8528 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0); 8529 rt2800_register_write(rt2x00dev, RF_CONTROL0, mac0518); 8530 rt2800_register_write(rt2x00dev, RF_BYPASS0, mac051c); 8531 rt2800_register_write(rt2x00dev, RF_CONTROL2, mac0528); 8532 rt2800_register_write(rt2x00dev, RF_BYPASS2, mac052c); 8533} 8534 8535static int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2) 8536{ 8537 int calcode = ((d2 - d1) * 1000) / 43; 8538 8539 if ((calcode % 10) >= 5) 8540 calcode += 10; 8541 calcode = (calcode / 10); 8542 8543 return calcode; 8544} 8545 8546static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev) 8547{ 8548 u32 savemacsysctrl; 8549 u8 saverfb0r1, saverfb0r34, saverfb0r35; 8550 u8 saverfb5r4, saverfb5r17, saverfb5r18; 8551 u8 saverfb5r19, saverfb5r20; 8552 u8 savebbpr22, savebbpr47, savebbpr49; 8553 u8 bytevalue = 0; 8554 int rcalcode; 8555 u8 r_cal_code = 0; 8556 s8 d1 = 0, d2 = 0; 8557 u8 rfvalue; 8558 u32 MAC_RF_BYPASS0, MAC_RF_CONTROL0, MAC_PWR_PIN_CFG; 8559 u32 maccfg; 8560 8561 saverfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 8562 saverfb0r34 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 34); 8563 saverfb0r35 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35); 8564 saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8565 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 8566 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 8567 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 8568 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 8569 8570 savebbpr22 = rt2800_bbp_read(rt2x00dev, 22); 8571 savebbpr47 = rt2800_bbp_read(rt2x00dev, 47); 8572 savebbpr49 = rt2800_bbp_read(rt2x00dev, 49); 8573 8574 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8575 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 8576 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 8577 MAC_PWR_PIN_CFG = rt2800_register_read(rt2x00dev, PWR_PIN_CFG); 8578 8579 maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8580 maccfg &= (~0x04); 8581 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg); 8582 8583 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 8584 rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n"); 8585 8586 maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8587 maccfg &= (~0x08); 8588 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg); 8589 8590 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX))) 8591 rt2x00_warn(rt2x00dev, "Wait MAC Rx Status to MAX !!!\n"); 8592 8593 rfvalue = (MAC_RF_BYPASS0 | 0x3004); 8594 rt2800_register_write(rt2x00dev, RF_BYPASS0, rfvalue); 8595 rfvalue = (MAC_RF_CONTROL0 | (~0x3002)); 8596 rt2800_register_write(rt2x00dev, RF_CONTROL0, rfvalue); 8597 8598 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x27); 8599 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80); 8600 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0x83); 8601 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x00); 8602 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20); 8603 8604 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x00); 8605 rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, 0x13); 8606 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00); 8607 8608 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x1); 8609 8610 rt2800_bbp_write(rt2x00dev, 47, 0x04); 8611 rt2800_bbp_write(rt2x00dev, 22, 0x80); 8612 usleep_range(100, 200); 8613 bytevalue = rt2800_bbp_read(rt2x00dev, 49); 8614 if (bytevalue > 128) 8615 d1 = bytevalue - 256; 8616 else 8617 d1 = (s8)bytevalue; 8618 rt2800_bbp_write(rt2x00dev, 22, 0x0); 8619 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01); 8620 8621 rt2800_bbp_write(rt2x00dev, 22, 0x80); 8622 usleep_range(100, 200); 8623 bytevalue = rt2800_bbp_read(rt2x00dev, 49); 8624 if (bytevalue > 128) 8625 d2 = bytevalue - 256; 8626 else 8627 d2 = (s8)bytevalue; 8628 rt2800_bbp_write(rt2x00dev, 22, 0x0); 8629 8630 rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2); 8631 if (rcalcode < 0) 8632 r_cal_code = 256 + rcalcode; 8633 else 8634 r_cal_code = (u8)rcalcode; 8635 8636 rt2800_rfcsr_write_bank(rt2x00dev, 0, 7, r_cal_code); 8637 8638 rt2800_bbp_write(rt2x00dev, 22, 0x0); 8639 8640 bytevalue = rt2800_bbp_read(rt2x00dev, 21); 8641 bytevalue |= 0x1; 8642 rt2800_bbp_write(rt2x00dev, 21, bytevalue); 8643 bytevalue = rt2800_bbp_read(rt2x00dev, 21); 8644 bytevalue &= (~0x1); 8645 rt2800_bbp_write(rt2x00dev, 21, bytevalue); 8646 8647 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, saverfb0r1); 8648 rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, saverfb0r34); 8649 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, saverfb0r35); 8650 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4); 8651 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); 8652 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); 8653 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); 8654 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); 8655 8656 rt2800_bbp_write(rt2x00dev, 22, savebbpr22); 8657 rt2800_bbp_write(rt2x00dev, 47, savebbpr47); 8658 rt2800_bbp_write(rt2x00dev, 49, savebbpr49); 8659 8660 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); 8661 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); 8662 8663 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 8664 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG); 8665} 8666 8667static void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev) 8668{ 8669 u8 bbpreg = 0; 8670 u32 macvalue = 0; 8671 u8 saverfb0r2, saverfb5r4, saverfb7r4, rfvalue; 8672 int i; 8673 8674 saverfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 8675 rfvalue = saverfb0r2; 8676 rfvalue |= 0x03; 8677 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfvalue); 8678 8679 rt2800_bbp_write(rt2x00dev, 158, 141); 8680 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8681 bbpreg |= 0x10; 8682 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8683 8684 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8685 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x8); 8686 8687 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 8688 rt2x00_warn(rt2x00dev, "RF TX busy in RX RXDCOC calibration\n"); 8689 8690 saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8691 saverfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4); 8692 saverfb5r4 = saverfb5r4 & (~0x40); 8693 saverfb7r4 = saverfb7r4 & (~0x40); 8694 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x64); 8695 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4); 8696 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, saverfb7r4); 8697 8698 rt2800_bbp_write(rt2x00dev, 158, 140); 8699 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8700 bbpreg = bbpreg & (~0x40); 8701 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8702 bbpreg |= 0x48; 8703 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8704 8705 for (i = 0; i < 10000; i++) { 8706 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8707 if ((bbpreg & 0x40) == 0) 8708 break; 8709 usleep_range(50, 100); 8710 } 8711 8712 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8713 bbpreg = bbpreg & (~0x40); 8714 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8715 8716 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 8717 8718 rt2800_bbp_write(rt2x00dev, 158, 141); 8719 bbpreg = rt2800_bbp_read(rt2x00dev, 159); 8720 bbpreg &= (~0x10); 8721 rt2800_bbp_write(rt2x00dev, 159, bbpreg); 8722 8723 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2); 8724} 8725 8726static u32 rt2800_do_sqrt_accumulation(u32 si) 8727{ 8728 u32 root, root_pre, bit; 8729 s8 i; 8730 8731 bit = 1 << 15; 8732 root = 0; 8733 for (i = 15; i >= 0; i = i - 1) { 8734 root_pre = root + bit; 8735 if ((root_pre * root_pre) <= si) 8736 root = root_pre; 8737 bit = bit >> 1; 8738 } 8739 8740 return root; 8741} 8742 8743static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev) 8744{ 8745 u8 rfb0r1, rfb0r2, rfb0r42; 8746 u8 rfb4r0, rfb4r19; 8747 u8 rfb5r3, rfb5r4, rfb5r17, rfb5r18, rfb5r19, rfb5r20; 8748 u8 rfb6r0, rfb6r19; 8749 u8 rfb7r3, rfb7r4, rfb7r17, rfb7r18, rfb7r19, rfb7r20; 8750 8751 u8 bbp1, bbp4; 8752 u8 bbpr241, bbpr242; 8753 u32 i; 8754 u8 ch_idx; 8755 u8 bbpval; 8756 u8 rfval, vga_idx = 0; 8757 int mi = 0, mq = 0, si = 0, sq = 0, riq = 0; 8758 int sigma_i, sigma_q, r_iq, g_rx; 8759 int g_imb; 8760 int ph_rx; 8761 u32 savemacsysctrl = 0; 8762 u32 orig_RF_CONTROL0 = 0; 8763 u32 orig_RF_BYPASS0 = 0; 8764 u32 orig_RF_CONTROL1 = 0; 8765 u32 orig_RF_BYPASS1 = 0; 8766 u32 orig_RF_CONTROL3 = 0; 8767 u32 orig_RF_BYPASS3 = 0; 8768 u32 bbpval1 = 0; 8769 static const u8 rf_vga_table[] = {0x20, 0x21, 0x22, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f}; 8770 8771 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 8772 orig_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 8773 orig_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 8774 orig_RF_CONTROL1 = rt2800_register_read(rt2x00dev, RF_CONTROL1); 8775 orig_RF_BYPASS1 = rt2800_register_read(rt2x00dev, RF_BYPASS1); 8776 orig_RF_CONTROL3 = rt2800_register_read(rt2x00dev, RF_CONTROL3); 8777 orig_RF_BYPASS3 = rt2800_register_read(rt2x00dev, RF_BYPASS3); 8778 8779 bbp1 = rt2800_bbp_read(rt2x00dev, 1); 8780 bbp4 = rt2800_bbp_read(rt2x00dev, 4); 8781 8782 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x0); 8783 8784 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY))) 8785 rt2x00_warn(rt2x00dev, "Timeout waiting for MAC status in RXIQ calibration\n"); 8786 8787 bbpval = bbp4 & (~0x18); 8788 bbpval = bbp4 | 0x00; 8789 rt2800_bbp_write(rt2x00dev, 4, bbpval); 8790 8791 bbpval = rt2800_bbp_read(rt2x00dev, 21); 8792 bbpval = bbpval | 1; 8793 rt2800_bbp_write(rt2x00dev, 21, bbpval); 8794 bbpval = bbpval & 0xfe; 8795 rt2800_bbp_write(rt2x00dev, 21, bbpval); 8796 8797 rt2800_register_write(rt2x00dev, RF_CONTROL1, 0x00000202); 8798 rt2800_register_write(rt2x00dev, RF_BYPASS1, 0x00000303); 8799 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) 8800 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0101); 8801 else 8802 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0000); 8803 8804 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0xf1f1); 8805 8806 rfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 8807 rfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 8808 rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 8809 rfb4r0 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0); 8810 rfb4r19 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 19); 8811 rfb5r3 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 8812 rfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8813 rfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 8814 rfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 8815 rfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 8816 rfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 8817 8818 rfb6r0 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0); 8819 rfb6r19 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 19); 8820 rfb7r3 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3); 8821 rfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4); 8822 rfb7r17 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17); 8823 rfb7r18 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18); 8824 rfb7r19 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19); 8825 rfb7r20 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20); 8826 8827 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x87); 8828 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0x27); 8829 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x38); 8830 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x38); 8831 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x80); 8832 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0xC1); 8833 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x60); 8834 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); 8835 8836 rt2800_bbp_write(rt2x00dev, 23, 0x0); 8837 rt2800_bbp_write(rt2x00dev, 24, 0x0); 8838 8839 rt2800_bbp_dcoc_write(rt2x00dev, 5, 0x0); 8840 8841 bbpr241 = rt2800_bbp_read(rt2x00dev, 241); 8842 bbpr242 = rt2800_bbp_read(rt2x00dev, 242); 8843 8844 rt2800_bbp_write(rt2x00dev, 241, 0x10); 8845 rt2800_bbp_write(rt2x00dev, 242, 0x84); 8846 rt2800_bbp_write(rt2x00dev, 244, 0x31); 8847 8848 bbpval = rt2800_bbp_dcoc_read(rt2x00dev, 3); 8849 bbpval = bbpval & (~0x7); 8850 rt2800_bbp_dcoc_write(rt2x00dev, 3, bbpval); 8851 8852 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 8853 udelay(1); 8854 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006); 8855 usleep_range(1, 200); 8856 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003376); 8857 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006); 8858 udelay(1); 8859 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 8860 rt2800_bbp_write(rt2x00dev, 23, 0x06); 8861 rt2800_bbp_write(rt2x00dev, 24, 0x06); 8862 } else { 8863 rt2800_bbp_write(rt2x00dev, 23, 0x02); 8864 rt2800_bbp_write(rt2x00dev, 24, 0x02); 8865 } 8866 8867 for (ch_idx = 0; ch_idx < 2; ch_idx = ch_idx + 1) { 8868 if (ch_idx == 0) { 8869 rfval = rfb0r1 & (~0x3); 8870 rfval = rfb0r1 | 0x1; 8871 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval); 8872 rfval = rfb0r2 & (~0x33); 8873 rfval = rfb0r2 | 0x11; 8874 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval); 8875 rfval = rfb0r42 & (~0x50); 8876 rfval = rfb0r42 | 0x10; 8877 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval); 8878 8879 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006); 8880 udelay(1); 8881 8882 bbpval = bbp1 & (~0x18); 8883 bbpval = bbpval | 0x00; 8884 rt2800_bbp_write(rt2x00dev, 1, bbpval); 8885 8886 rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x00); 8887 } else { 8888 rfval = rfb0r1 & (~0x3); 8889 rfval = rfb0r1 | 0x2; 8890 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval); 8891 rfval = rfb0r2 & (~0x33); 8892 rfval = rfb0r2 | 0x22; 8893 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval); 8894 rfval = rfb0r42 & (~0x50); 8895 rfval = rfb0r42 | 0x40; 8896 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval); 8897 8898 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002006); 8899 udelay(1); 8900 8901 bbpval = bbp1 & (~0x18); 8902 bbpval = bbpval | 0x08; 8903 rt2800_bbp_write(rt2x00dev, 1, bbpval); 8904 8905 rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x01); 8906 } 8907 usleep_range(500, 1500); 8908 8909 vga_idx = 0; 8910 while (vga_idx < 11) { 8911 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rf_vga_table[vga_idx]); 8912 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rf_vga_table[vga_idx]); 8913 8914 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x93); 8915 8916 for (i = 0; i < 10000; i++) { 8917 bbpval = rt2800_bbp_read(rt2x00dev, 159); 8918 if ((bbpval & 0xff) == 0x93) 8919 usleep_range(50, 100); 8920 else 8921 break; 8922 } 8923 8924 if ((bbpval & 0xff) == 0x93) { 8925 rt2x00_warn(rt2x00dev, "Fatal Error: Calibration doesn't finish"); 8926 goto restore_value; 8927 } 8928 for (i = 0; i < 5; i++) { 8929 u32 bbptemp = 0; 8930 u8 value = 0; 8931 int result = 0; 8932 8933 rt2800_bbp_write(rt2x00dev, 158, 0x1e); 8934 rt2800_bbp_write(rt2x00dev, 159, i); 8935 rt2800_bbp_write(rt2x00dev, 158, 0x22); 8936 value = rt2800_bbp_read(rt2x00dev, 159); 8937 bbptemp = bbptemp + (value << 24); 8938 rt2800_bbp_write(rt2x00dev, 158, 0x21); 8939 value = rt2800_bbp_read(rt2x00dev, 159); 8940 bbptemp = bbptemp + (value << 16); 8941 rt2800_bbp_write(rt2x00dev, 158, 0x20); 8942 value = rt2800_bbp_read(rt2x00dev, 159); 8943 bbptemp = bbptemp + (value << 8); 8944 rt2800_bbp_write(rt2x00dev, 158, 0x1f); 8945 value = rt2800_bbp_read(rt2x00dev, 159); 8946 bbptemp = bbptemp + value; 8947 8948 if (i < 2 && (bbptemp & 0x800000)) 8949 result = (bbptemp & 0xffffff) - 0x1000000; 8950 else 8951 result = bbptemp; 8952 8953 if (i == 0) 8954 mi = result / 4096; 8955 else if (i == 1) 8956 mq = result / 4096; 8957 else if (i == 2) 8958 si = bbptemp / 4096; 8959 else if (i == 3) 8960 sq = bbptemp / 4096; 8961 else 8962 riq = result / 4096; 8963 } 8964 8965 bbpval1 = si - mi * mi; 8966 rt2x00_dbg(rt2x00dev, 8967 "RXIQ si=%d, sq=%d, riq=%d, bbpval %d, vga_idx %d", 8968 si, sq, riq, bbpval1, vga_idx); 8969 8970 if (bbpval1 >= (100 * 100)) 8971 break; 8972 8973 if (bbpval1 <= 100) 8974 vga_idx = vga_idx + 9; 8975 else if (bbpval1 <= 158) 8976 vga_idx = vga_idx + 8; 8977 else if (bbpval1 <= 251) 8978 vga_idx = vga_idx + 7; 8979 else if (bbpval1 <= 398) 8980 vga_idx = vga_idx + 6; 8981 else if (bbpval1 <= 630) 8982 vga_idx = vga_idx + 5; 8983 else if (bbpval1 <= 1000) 8984 vga_idx = vga_idx + 4; 8985 else if (bbpval1 <= 1584) 8986 vga_idx = vga_idx + 3; 8987 else if (bbpval1 <= 2511) 8988 vga_idx = vga_idx + 2; 8989 else 8990 vga_idx = vga_idx + 1; 8991 } 8992 8993 sigma_i = rt2800_do_sqrt_accumulation(100 * (si - mi * mi)); 8994 sigma_q = rt2800_do_sqrt_accumulation(100 * (sq - mq * mq)); 8995 r_iq = 10 * (riq - (mi * mq)); 8996 8997 rt2x00_dbg(rt2x00dev, "Sigma_i=%d, Sigma_q=%d, R_iq=%d", sigma_i, sigma_q, r_iq); 8998 8999 if (sigma_i <= 1400 && sigma_i >= 1000 && 9000 (sigma_i - sigma_q) <= 112 && 9001 (sigma_i - sigma_q) >= -112 && 9002 mi <= 32 && mi >= -32 && 9003 mq <= 32 && mq >= -32) { 9004 r_iq = 10 * (riq - (mi * mq)); 9005 rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n", 9006 sigma_i, sigma_q, r_iq); 9007 9008 g_rx = (1000 * sigma_q) / sigma_i; 9009 g_imb = ((-2) * 128 * (1000 - g_rx)) / (1000 + g_rx); 9010 ph_rx = (r_iq * 2292) / (sigma_i * sigma_q); 9011 9012 if (ph_rx > 20 || ph_rx < -20) { 9013 ph_rx = 0; 9014 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL"); 9015 } 9016 9017 if (g_imb > 12 || g_imb < -12) { 9018 g_imb = 0; 9019 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL"); 9020 } 9021 } else { 9022 g_imb = 0; 9023 ph_rx = 0; 9024 rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n", 9025 sigma_i, sigma_q, r_iq); 9026 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL"); 9027 } 9028 9029 if (ch_idx == 0) { 9030 rt2800_bbp_write(rt2x00dev, 158, 0x37); 9031 rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f); 9032 rt2800_bbp_write(rt2x00dev, 158, 0x35); 9033 rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f); 9034 } else { 9035 rt2800_bbp_write(rt2x00dev, 158, 0x55); 9036 rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f); 9037 rt2800_bbp_write(rt2x00dev, 158, 0x53); 9038 rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f); 9039 } 9040 } 9041 9042restore_value: 9043 rt2800_bbp_write(rt2x00dev, 158, 0x3); 9044 bbpval = rt2800_bbp_read(rt2x00dev, 159); 9045 rt2800_bbp_write(rt2x00dev, 159, (bbpval | 0x07)); 9046 9047 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9048 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9049 rt2800_bbp_write(rt2x00dev, 1, bbp1); 9050 rt2800_bbp_write(rt2x00dev, 4, bbp4); 9051 rt2800_bbp_write(rt2x00dev, 241, bbpr241); 9052 rt2800_bbp_write(rt2x00dev, 242, bbpr242); 9053 9054 rt2800_bbp_write(rt2x00dev, 244, 0x00); 9055 bbpval = rt2800_bbp_read(rt2x00dev, 21); 9056 bbpval |= 0x1; 9057 rt2800_bbp_write(rt2x00dev, 21, bbpval); 9058 usleep_range(10, 200); 9059 bbpval &= 0xfe; 9060 rt2800_bbp_write(rt2x00dev, 21, bbpval); 9061 9062 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfb0r1); 9063 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfb0r2); 9064 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42); 9065 9066 rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, rfb4r0); 9067 rt2800_rfcsr_write_bank(rt2x00dev, 4, 19, rfb4r19); 9068 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rfb5r3); 9069 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rfb5r4); 9070 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rfb5r17); 9071 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, rfb5r18); 9072 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, rfb5r19); 9073 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, rfb5r20); 9074 9075 rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, rfb6r0); 9076 rt2800_rfcsr_write_bank(rt2x00dev, 6, 19, rfb6r19); 9077 rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, rfb7r3); 9078 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, rfb7r4); 9079 rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, rfb7r17); 9080 rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, rfb7r18); 9081 rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, rfb7r19); 9082 rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, rfb7r20); 9083 9084 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006); 9085 udelay(1); 9086 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 9087 udelay(1); 9088 rt2800_register_write(rt2x00dev, RF_CONTROL0, orig_RF_CONTROL0); 9089 udelay(1); 9090 rt2800_register_write(rt2x00dev, RF_BYPASS0, orig_RF_BYPASS0); 9091 rt2800_register_write(rt2x00dev, RF_CONTROL1, orig_RF_CONTROL1); 9092 rt2800_register_write(rt2x00dev, RF_BYPASS1, orig_RF_BYPASS1); 9093 rt2800_register_write(rt2x00dev, RF_CONTROL3, orig_RF_CONTROL3); 9094 rt2800_register_write(rt2x00dev, RF_BYPASS3, orig_RF_BYPASS3); 9095 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 9096} 9097 9098static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev, 9099 struct rf_reg_pair rf_reg_record[][13], u8 chain) 9100{ 9101 u8 rfvalue = 0; 9102 9103 if (chain == CHAIN_0) { 9104 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 9105 rf_reg_record[CHAIN_0][0].bank = 0; 9106 rf_reg_record[CHAIN_0][0].reg = 1; 9107 rf_reg_record[CHAIN_0][0].value = rfvalue; 9108 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 9109 rf_reg_record[CHAIN_0][1].bank = 0; 9110 rf_reg_record[CHAIN_0][1].reg = 2; 9111 rf_reg_record[CHAIN_0][1].value = rfvalue; 9112 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35); 9113 rf_reg_record[CHAIN_0][2].bank = 0; 9114 rf_reg_record[CHAIN_0][2].reg = 35; 9115 rf_reg_record[CHAIN_0][2].value = rfvalue; 9116 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 9117 rf_reg_record[CHAIN_0][3].bank = 0; 9118 rf_reg_record[CHAIN_0][3].reg = 42; 9119 rf_reg_record[CHAIN_0][3].value = rfvalue; 9120 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0); 9121 rf_reg_record[CHAIN_0][4].bank = 4; 9122 rf_reg_record[CHAIN_0][4].reg = 0; 9123 rf_reg_record[CHAIN_0][4].value = rfvalue; 9124 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2); 9125 rf_reg_record[CHAIN_0][5].bank = 4; 9126 rf_reg_record[CHAIN_0][5].reg = 2; 9127 rf_reg_record[CHAIN_0][5].value = rfvalue; 9128 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34); 9129 rf_reg_record[CHAIN_0][6].bank = 4; 9130 rf_reg_record[CHAIN_0][6].reg = 34; 9131 rf_reg_record[CHAIN_0][6].value = rfvalue; 9132 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 9133 rf_reg_record[CHAIN_0][7].bank = 5; 9134 rf_reg_record[CHAIN_0][7].reg = 3; 9135 rf_reg_record[CHAIN_0][7].value = rfvalue; 9136 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 9137 rf_reg_record[CHAIN_0][8].bank = 5; 9138 rf_reg_record[CHAIN_0][8].reg = 4; 9139 rf_reg_record[CHAIN_0][8].value = rfvalue; 9140 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 9141 rf_reg_record[CHAIN_0][9].bank = 5; 9142 rf_reg_record[CHAIN_0][9].reg = 17; 9143 rf_reg_record[CHAIN_0][9].value = rfvalue; 9144 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 9145 rf_reg_record[CHAIN_0][10].bank = 5; 9146 rf_reg_record[CHAIN_0][10].reg = 18; 9147 rf_reg_record[CHAIN_0][10].value = rfvalue; 9148 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 9149 rf_reg_record[CHAIN_0][11].bank = 5; 9150 rf_reg_record[CHAIN_0][11].reg = 19; 9151 rf_reg_record[CHAIN_0][11].value = rfvalue; 9152 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 9153 rf_reg_record[CHAIN_0][12].bank = 5; 9154 rf_reg_record[CHAIN_0][12].reg = 20; 9155 rf_reg_record[CHAIN_0][12].value = rfvalue; 9156 } else if (chain == CHAIN_1) { 9157 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1); 9158 rf_reg_record[CHAIN_1][0].bank = 0; 9159 rf_reg_record[CHAIN_1][0].reg = 1; 9160 rf_reg_record[CHAIN_1][0].value = rfvalue; 9161 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2); 9162 rf_reg_record[CHAIN_1][1].bank = 0; 9163 rf_reg_record[CHAIN_1][1].reg = 2; 9164 rf_reg_record[CHAIN_1][1].value = rfvalue; 9165 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35); 9166 rf_reg_record[CHAIN_1][2].bank = 0; 9167 rf_reg_record[CHAIN_1][2].reg = 35; 9168 rf_reg_record[CHAIN_1][2].value = rfvalue; 9169 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 9170 rf_reg_record[CHAIN_1][3].bank = 0; 9171 rf_reg_record[CHAIN_1][3].reg = 42; 9172 rf_reg_record[CHAIN_1][3].value = rfvalue; 9173 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0); 9174 rf_reg_record[CHAIN_1][4].bank = 6; 9175 rf_reg_record[CHAIN_1][4].reg = 0; 9176 rf_reg_record[CHAIN_1][4].value = rfvalue; 9177 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2); 9178 rf_reg_record[CHAIN_1][5].bank = 6; 9179 rf_reg_record[CHAIN_1][5].reg = 2; 9180 rf_reg_record[CHAIN_1][5].value = rfvalue; 9181 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34); 9182 rf_reg_record[CHAIN_1][6].bank = 6; 9183 rf_reg_record[CHAIN_1][6].reg = 34; 9184 rf_reg_record[CHAIN_1][6].value = rfvalue; 9185 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3); 9186 rf_reg_record[CHAIN_1][7].bank = 7; 9187 rf_reg_record[CHAIN_1][7].reg = 3; 9188 rf_reg_record[CHAIN_1][7].value = rfvalue; 9189 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4); 9190 rf_reg_record[CHAIN_1][8].bank = 7; 9191 rf_reg_record[CHAIN_1][8].reg = 4; 9192 rf_reg_record[CHAIN_1][8].value = rfvalue; 9193 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17); 9194 rf_reg_record[CHAIN_1][9].bank = 7; 9195 rf_reg_record[CHAIN_1][9].reg = 17; 9196 rf_reg_record[CHAIN_1][9].value = rfvalue; 9197 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18); 9198 rf_reg_record[CHAIN_1][10].bank = 7; 9199 rf_reg_record[CHAIN_1][10].reg = 18; 9200 rf_reg_record[CHAIN_1][10].value = rfvalue; 9201 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19); 9202 rf_reg_record[CHAIN_1][11].bank = 7; 9203 rf_reg_record[CHAIN_1][11].reg = 19; 9204 rf_reg_record[CHAIN_1][11].value = rfvalue; 9205 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20); 9206 rf_reg_record[CHAIN_1][12].bank = 7; 9207 rf_reg_record[CHAIN_1][12].reg = 20; 9208 rf_reg_record[CHAIN_1][12].value = rfvalue; 9209 } else { 9210 rt2x00_warn(rt2x00dev, "Unknown chain = %u\n", chain); 9211 } 9212} 9213 9214static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev, 9215 struct rf_reg_pair rf_record[][13]) 9216{ 9217 u8 chain_index = 0, record_index = 0; 9218 u8 bank = 0, rf_register = 0, value = 0; 9219 9220 for (chain_index = 0; chain_index < 2; chain_index++) { 9221 for (record_index = 0; record_index < 13; record_index++) { 9222 bank = rf_record[chain_index][record_index].bank; 9223 rf_register = rf_record[chain_index][record_index].reg; 9224 value = rf_record[chain_index][record_index].value; 9225 rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value); 9226 rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n", 9227 bank, rf_register, value); 9228 } 9229 } 9230} 9231 9232static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev) 9233{ 9234 rt2800_bbp_write(rt2x00dev, 158, 0xAA); 9235 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9236 9237 rt2800_bbp_write(rt2x00dev, 158, 0xAB); 9238 rt2800_bbp_write(rt2x00dev, 159, 0x0A); 9239 9240 rt2800_bbp_write(rt2x00dev, 158, 0xAC); 9241 rt2800_bbp_write(rt2x00dev, 159, 0x3F); 9242 9243 rt2800_bbp_write(rt2x00dev, 158, 0xAD); 9244 rt2800_bbp_write(rt2x00dev, 159, 0x3F); 9245 9246 rt2800_bbp_write(rt2x00dev, 244, 0x40); 9247} 9248 9249static u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg) 9250{ 9251 u32 macvalue = 0; 9252 int fftout_i = 0, fftout_q = 0; 9253 u32 ptmp = 0, pint = 0; 9254 u8 bbp = 0; 9255 u8 tidxi; 9256 9257 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9258 rt2800_bbp_write(rt2x00dev, 159, 0x9b); 9259 9260 bbp = 0x9b; 9261 9262 while (bbp == 0x9b) { 9263 usleep_range(10, 50); 9264 bbp = rt2800_bbp_read(rt2x00dev, 159); 9265 bbp = bbp & 0xff; 9266 } 9267 9268 rt2800_bbp_write(rt2x00dev, 158, 0xba); 9269 rt2800_bbp_write(rt2x00dev, 159, tidx); 9270 rt2800_bbp_write(rt2x00dev, 159, tidx); 9271 rt2800_bbp_write(rt2x00dev, 159, tidx); 9272 9273 macvalue = rt2800_register_read(rt2x00dev, 0x057C); 9274 9275 fftout_i = (macvalue >> 16); 9276 fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i; 9277 fftout_q = (macvalue & 0xffff); 9278 fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q; 9279 ptmp = (fftout_i * fftout_i); 9280 ptmp = ptmp + (fftout_q * fftout_q); 9281 pint = ptmp; 9282 rt2x00_dbg(rt2x00dev, "I = %d, Q = %d, power = %x\n", fftout_i, fftout_q, pint); 9283 if (read_neg) { 9284 pint = pint >> 1; 9285 tidxi = 0x40 - tidx; 9286 tidxi = tidxi & 0x3f; 9287 9288 rt2800_bbp_write(rt2x00dev, 158, 0xba); 9289 rt2800_bbp_write(rt2x00dev, 159, tidxi); 9290 rt2800_bbp_write(rt2x00dev, 159, tidxi); 9291 rt2800_bbp_write(rt2x00dev, 159, tidxi); 9292 9293 macvalue = rt2800_register_read(rt2x00dev, 0x057C); 9294 9295 fftout_i = (macvalue >> 16); 9296 fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i; 9297 fftout_q = (macvalue & 0xffff); 9298 fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q; 9299 ptmp = (fftout_i * fftout_i); 9300 ptmp = ptmp + (fftout_q * fftout_q); 9301 ptmp = ptmp >> 1; 9302 pint = pint + ptmp; 9303 } 9304 9305 return pint; 9306} 9307 9308static u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx) 9309{ 9310 u32 macvalue = 0; 9311 int fftout_i = 0, fftout_q = 0; 9312 u32 ptmp = 0, pint = 0; 9313 9314 rt2800_bbp_write(rt2x00dev, 158, 0xBA); 9315 rt2800_bbp_write(rt2x00dev, 159, tidx); 9316 rt2800_bbp_write(rt2x00dev, 159, tidx); 9317 rt2800_bbp_write(rt2x00dev, 159, tidx); 9318 9319 macvalue = rt2800_register_read(rt2x00dev, 0x057C); 9320 9321 fftout_i = (macvalue >> 16); 9322 fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i; 9323 fftout_q = (macvalue & 0xffff); 9324 fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q; 9325 ptmp = (fftout_i * fftout_i); 9326 ptmp = ptmp + (fftout_q * fftout_q); 9327 pint = ptmp; 9328 9329 return pint; 9330} 9331 9332static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc) 9333{ 9334 u8 bbp = 0; 9335 9336 rt2800_bbp_write(rt2x00dev, 158, 0xb0); 9337 bbp = alc | 0x80; 9338 rt2800_bbp_write(rt2x00dev, 159, bbp); 9339 9340 if (ch_idx == 0) 9341 bbp = (iorq == 0) ? 0xb1 : 0xb2; 9342 else 9343 bbp = (iorq == 0) ? 0xb8 : 0xb9; 9344 9345 rt2800_bbp_write(rt2x00dev, 158, bbp); 9346 bbp = dc; 9347 rt2800_bbp_write(rt2x00dev, 159, bbp); 9348} 9349 9350static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, 9351 u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2]) 9352{ 9353 u32 p0 = 0, p1 = 0, pf = 0; 9354 s8 idx0 = 0, idx1 = 0; 9355 u8 idxf[] = {0x00, 0x00}; 9356 u8 ibit = 0x20; 9357 u8 iorq; 9358 s8 bidx; 9359 9360 rt2800_bbp_write(rt2x00dev, 158, 0xb0); 9361 rt2800_bbp_write(rt2x00dev, 159, 0x80); 9362 9363 for (bidx = 5; bidx >= 0; bidx--) { 9364 for (iorq = 0; iorq <= 1; iorq++) { 9365 if (idxf[iorq] == 0x20) { 9366 idx0 = 0x20; 9367 p0 = pf; 9368 } else { 9369 idx0 = idxf[iorq] - ibit; 9370 idx0 = idx0 & 0x3F; 9371 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0); 9372 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9373 } 9374 9375 idx1 = idxf[iorq] + (bidx == 5 ? 0 : ibit); 9376 idx1 = idx1 & 0x3F; 9377 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1); 9378 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9379 9380 rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n", 9381 alc_idx, iorq, idxf[iorq]); 9382 rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x\n", 9383 p0, p1, pf, idx0, idx1, ibit); 9384 9385 if (bidx != 5 && pf <= p0 && pf < p1) { 9386 idxf[iorq] = idxf[iorq]; 9387 } else if (p0 < p1) { 9388 pf = p0; 9389 idxf[iorq] = idx0 & 0x3F; 9390 } else { 9391 pf = p1; 9392 idxf[iorq] = idx1 & 0x3F; 9393 } 9394 rt2x00_dbg(rt2x00dev, "IorQ=%u, idx_final[%u]:%x, pf:%8x\n", 9395 iorq, iorq, idxf[iorq], pf); 9396 9397 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]); 9398 } 9399 ibit = ibit >> 1; 9400 } 9401 dc_result[ch_idx][alc_idx][0] = idxf[0]; 9402 dc_result[ch_idx][alc_idx][1] = idxf[1]; 9403} 9404 9405static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes) 9406{ 9407 u32 p0 = 0, p1 = 0, pf = 0; 9408 s8 perr = 0, gerr = 0, iq_err = 0; 9409 s8 pef = 0, gef = 0; 9410 s8 psta, pend; 9411 s8 gsta, gend; 9412 9413 u8 ibit = 0x20; 9414 u8 first_search = 0x00, touch_neg_max = 0x00; 9415 s8 idx0 = 0, idx1 = 0; 9416 u8 gop; 9417 u8 bbp = 0; 9418 s8 bidx; 9419 9420 for (bidx = 5; bidx >= 1; bidx--) { 9421 for (gop = 0; gop < 2; gop++) { 9422 if (gop == 1 || bidx < 4) { 9423 if (gop == 0) 9424 iq_err = gerr; 9425 else 9426 iq_err = perr; 9427 9428 first_search = (gop == 0) ? (bidx == 3) : (bidx == 5); 9429 touch_neg_max = (gop) ? ((iq_err & 0x0F) == 0x08) : 9430 ((iq_err & 0x3F) == 0x20); 9431 9432 if (touch_neg_max) { 9433 p0 = pf; 9434 idx0 = iq_err; 9435 } else { 9436 idx0 = iq_err - ibit; 9437 bbp = (ch_idx == 0) ? ((gop == 0) ? 0x28 : 0x29) : 9438 ((gop == 0) ? 0x46 : 0x47); 9439 9440 rt2800_bbp_write(rt2x00dev, 158, bbp); 9441 rt2800_bbp_write(rt2x00dev, 159, idx0); 9442 9443 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1); 9444 } 9445 9446 idx1 = iq_err + (first_search ? 0 : ibit); 9447 idx1 = (gop == 0) ? (idx1 & 0x0F) : (idx1 & 0x3F); 9448 9449 bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : 9450 (gop == 0) ? 0x46 : 0x47; 9451 9452 rt2800_bbp_write(rt2x00dev, 158, bbp); 9453 rt2800_bbp_write(rt2x00dev, 159, idx1); 9454 9455 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1); 9456 9457 rt2x00_dbg(rt2x00dev, 9458 "p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x\n", 9459 p0, p1, pf, idx0, idx1, iq_err, gop, ibit); 9460 9461 if (!(!first_search && pf <= p0 && pf < p1)) { 9462 if (p0 < p1) { 9463 pf = p0; 9464 iq_err = idx0; 9465 } else { 9466 pf = p1; 9467 iq_err = idx1; 9468 } 9469 } 9470 9471 bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : 9472 (gop == 0) ? 0x46 : 0x47; 9473 9474 rt2800_bbp_write(rt2x00dev, 158, bbp); 9475 rt2800_bbp_write(rt2x00dev, 159, iq_err); 9476 9477 if (gop == 0) 9478 gerr = iq_err; 9479 else 9480 perr = iq_err; 9481 9482 rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n", 9483 pf, gerr & 0x0F, perr & 0x3F); 9484 } 9485 } 9486 9487 if (bidx > 0) 9488 ibit = (ibit >> 1); 9489 } 9490 gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F); 9491 perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F); 9492 9493 gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr; 9494 gsta = gerr - 1; 9495 gend = gerr + 2; 9496 9497 perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr; 9498 psta = perr - 1; 9499 pend = perr + 2; 9500 9501 for (gef = gsta; gef <= gend; gef = gef + 1) 9502 for (pef = psta; pef <= pend; pef = pef + 1) { 9503 bbp = (ch_idx == 0) ? 0x28 : 0x46; 9504 rt2800_bbp_write(rt2x00dev, 158, bbp); 9505 rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F); 9506 9507 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9508 rt2800_bbp_write(rt2x00dev, 158, bbp); 9509 rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F); 9510 9511 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1); 9512 if (gef == gsta && pef == psta) { 9513 pf = p1; 9514 gerr = gef; 9515 perr = pef; 9516 } else if (pf > p1) { 9517 pf = p1; 9518 gerr = gef; 9519 perr = pef; 9520 } 9521 rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n", 9522 p1, pf, gef & 0x0F, pef & 0x3F); 9523 } 9524 9525 ges[ch_idx] = gerr & 0x0F; 9526 pes[ch_idx] = perr & 0x3F; 9527} 9528 9529static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev) 9530{ 9531 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21); 9532 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10); 9533 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00); 9534 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b); 9535 rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81); 9536 rt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81); 9537 rt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee); 9538 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d); 9539 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d); 9540 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80); 9541 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7); 9542 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2); 9543 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20); 9544} 9545 9546static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev) 9547{ 9548 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22); 9549 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20); 9550 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00); 9551 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b); 9552 rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81); 9553 rt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81); 9554 rt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee); 9555 rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d); 9556 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d); 9557 rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80); 9558 rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7); 9559 rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2); 9560 rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20); 9561} 9562 9563static void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev) 9564{ 9565 struct rf_reg_pair rf_store[CHAIN_NUM][13]; 9566 u32 macorg1 = 0; 9567 u32 macorg2 = 0; 9568 u32 macorg3 = 0; 9569 u32 macorg4 = 0; 9570 u32 macorg5 = 0; 9571 u32 orig528 = 0; 9572 u32 orig52c = 0; 9573 9574 u32 savemacsysctrl = 0; 9575 u32 macvalue = 0; 9576 u32 mac13b8 = 0; 9577 u32 p0 = 0, p1 = 0; 9578 u32 p0_idx10 = 0, p1_idx10 = 0; 9579 9580 u8 rfvalue; 9581 u8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2]; 9582 u8 ger[CHAIN_NUM], per[CHAIN_NUM]; 9583 9584 u8 vga_gain[] = {14, 14}; 9585 u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0; 9586 u8 bbpr30, rfb0r39, rfb0r42; 9587 u8 bbpr1; 9588 u8 bbpr4; 9589 u8 bbpr241, bbpr242; 9590 u8 count_step; 9591 9592 static const u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c}; 9593 static const u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 9594 0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F}; 9595 static const u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08}; 9596 9597 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9598 macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 9599 macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 9600 macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 9601 macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3); 9602 macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3); 9603 mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8); 9604 orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2); 9605 orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2); 9606 9607 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9608 macvalue &= (~0x04); 9609 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9610 9611 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 9612 rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n"); 9613 9614 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9615 macvalue &= (~0x08); 9616 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9617 9618 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX))) 9619 rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n"); 9620 9621 for (ch_idx = 0; ch_idx < 2; ch_idx++) 9622 rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx); 9623 9624 bbpr30 = rt2800_bbp_read(rt2x00dev, 30); 9625 rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39); 9626 rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42); 9627 9628 rt2800_bbp_write(rt2x00dev, 30, 0x1F); 9629 rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80); 9630 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B); 9631 9632 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9633 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9634 9635 rt2800_setbbptonegenerator(rt2x00dev); 9636 9637 for (ch_idx = 0; ch_idx < 2; ch_idx++) { 9638 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9639 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9640 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00); 9641 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F); 9642 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 9643 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306); 9644 rt2800_register_write(rt2x00dev, 0x13b8, 0x10); 9645 udelay(1); 9646 9647 if (ch_idx == 0) 9648 rt2800_rf_aux_tx0_loopback(rt2x00dev); 9649 else 9650 rt2800_rf_aux_tx1_loopback(rt2x00dev); 9651 9652 udelay(1); 9653 9654 if (ch_idx == 0) 9655 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004); 9656 else 9657 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004); 9658 9659 rt2800_bbp_write(rt2x00dev, 158, 0x05); 9660 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9661 9662 rt2800_bbp_write(rt2x00dev, 158, 0x01); 9663 if (ch_idx == 0) 9664 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9665 else 9666 rt2800_bbp_write(rt2x00dev, 159, 0x01); 9667 9668 vga_gain[ch_idx] = 18; 9669 for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) { 9670 rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]); 9671 rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]); 9672 9673 macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3); 9674 macvalue &= (~0x0000F1F1); 9675 macvalue |= (rf_gain[rf_alc_idx] << 4); 9676 macvalue |= (rf_gain[rf_alc_idx] << 12); 9677 rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue); 9678 macvalue = (0x0000F1F1); 9679 rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue); 9680 9681 if (rf_alc_idx == 0) { 9682 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21); 9683 for (; vga_gain[ch_idx] > 0; 9684 vga_gain[ch_idx] = vga_gain[ch_idx] - 2) { 9685 rfvalue = rfvga_gain_table[vga_gain[ch_idx]]; 9686 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue); 9687 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue); 9688 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00); 9689 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00); 9690 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9691 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21); 9692 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0); 9693 rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1); 9694 if ((p0 < 7000 * 7000) && (p1 < (7000 * 7000))) 9695 break; 9696 } 9697 9698 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00); 9699 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00); 9700 9701 rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx], 9702 rfvga_gain_table[vga_gain[ch_idx]]); 9703 9704 if (vga_gain[ch_idx] < 0) 9705 vga_gain[ch_idx] = 0; 9706 } 9707 9708 rfvalue = rfvga_gain_table[vga_gain[ch_idx]]; 9709 9710 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue); 9711 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue); 9712 9713 rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result); 9714 } 9715 } 9716 9717 for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) { 9718 for (idx = 0; idx < 4; idx++) { 9719 rt2800_bbp_write(rt2x00dev, 158, 0xB0); 9720 bbp = (idx << 2) + rf_alc_idx; 9721 rt2800_bbp_write(rt2x00dev, 159, bbp); 9722 rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp); 9723 9724 rt2800_bbp_write(rt2x00dev, 158, 0xb1); 9725 bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00]; 9726 bbp = bbp & 0x3F; 9727 rt2800_bbp_write(rt2x00dev, 159, bbp); 9728 rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp); 9729 9730 rt2800_bbp_write(rt2x00dev, 158, 0xb2); 9731 bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01]; 9732 bbp = bbp & 0x3F; 9733 rt2800_bbp_write(rt2x00dev, 159, bbp); 9734 rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp); 9735 9736 rt2800_bbp_write(rt2x00dev, 158, 0xb8); 9737 bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00]; 9738 bbp = bbp & 0x3F; 9739 rt2800_bbp_write(rt2x00dev, 159, bbp); 9740 rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp); 9741 9742 rt2800_bbp_write(rt2x00dev, 158, 0xb9); 9743 bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01]; 9744 bbp = bbp & 0x3F; 9745 rt2800_bbp_write(rt2x00dev, 159, bbp); 9746 rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp); 9747 } 9748 } 9749 9750 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9751 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9752 9753 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 9754 9755 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9756 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9757 9758 bbp = 0x00; 9759 rt2800_bbp_write(rt2x00dev, 244, 0x00); 9760 9761 rt2800_bbp_write(rt2x00dev, 21, 0x01); 9762 udelay(1); 9763 rt2800_bbp_write(rt2x00dev, 21, 0x00); 9764 9765 rt2800_rf_configrecover(rt2x00dev, rf_store); 9766 9767 rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1); 9768 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 9769 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00); 9770 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00); 9771 rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2); 9772 udelay(1); 9773 rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3); 9774 rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4); 9775 rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5); 9776 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 9777 rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528); 9778 rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c); 9779 rt2800_register_write(rt2x00dev, 0x13b8, mac13b8); 9780 9781 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9782 macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 9783 macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 9784 macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 9785 macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3); 9786 macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3); 9787 9788 bbpr1 = rt2800_bbp_read(rt2x00dev, 1); 9789 bbpr4 = rt2800_bbp_read(rt2x00dev, 4); 9790 bbpr241 = rt2800_bbp_read(rt2x00dev, 241); 9791 bbpr242 = rt2800_bbp_read(rt2x00dev, 242); 9792 mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8); 9793 9794 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9795 macvalue &= (~0x04); 9796 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9797 9798 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX))) 9799 rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n"); 9800 9801 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9802 macvalue &= (~0x08); 9803 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue); 9804 9805 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX))) 9806 rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n"); 9807 9808 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9809 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101); 9810 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1); 9811 } 9812 9813 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9814 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9815 9816 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9817 rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18)); 9818 rt2800_bbp_write(rt2x00dev, 21, 0x01); 9819 udelay(1); 9820 rt2800_bbp_write(rt2x00dev, 21, 0x00); 9821 9822 rt2800_bbp_write(rt2x00dev, 241, 0x14); 9823 rt2800_bbp_write(rt2x00dev, 242, 0x80); 9824 rt2800_bbp_write(rt2x00dev, 244, 0x31); 9825 } else { 9826 rt2800_setbbptonegenerator(rt2x00dev); 9827 } 9828 9829 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004); 9830 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306); 9831 udelay(1); 9832 9833 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F); 9834 9835 if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9836 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000); 9837 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1); 9838 } 9839 9840 rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010); 9841 9842 for (ch_idx = 0; ch_idx < 2; ch_idx++) 9843 rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx); 9844 9845 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B); 9846 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B); 9847 9848 rt2800_bbp_write(rt2x00dev, 158, 0x03); 9849 rt2800_bbp_write(rt2x00dev, 159, 0x60); 9850 rt2800_bbp_write(rt2x00dev, 158, 0xB0); 9851 rt2800_bbp_write(rt2x00dev, 159, 0x80); 9852 9853 for (ch_idx = 0; ch_idx < 2; ch_idx++) { 9854 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9855 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9856 9857 if (ch_idx == 0) { 9858 rt2800_bbp_write(rt2x00dev, 158, 0x01); 9859 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9860 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9861 bbp = bbpr1 & (~0x18); 9862 bbp = bbp | 0x00; 9863 rt2800_bbp_write(rt2x00dev, 1, bbp); 9864 } 9865 rt2800_rf_aux_tx0_loopback(rt2x00dev); 9866 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004); 9867 } else { 9868 rt2800_bbp_write(rt2x00dev, 158, 0x01); 9869 rt2800_bbp_write(rt2x00dev, 159, 0x01); 9870 if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) { 9871 bbp = bbpr1 & (~0x18); 9872 bbp = bbp | 0x08; 9873 rt2800_bbp_write(rt2x00dev, 1, bbp); 9874 } 9875 rt2800_rf_aux_tx1_loopback(rt2x00dev); 9876 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004); 9877 } 9878 9879 rt2800_bbp_write(rt2x00dev, 158, 0x05); 9880 rt2800_bbp_write(rt2x00dev, 159, 0x04); 9881 9882 bbp = (ch_idx == 0) ? 0x28 : 0x46; 9883 rt2800_bbp_write(rt2x00dev, 158, bbp); 9884 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9885 9886 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9887 rt2800_bbp_write(rt2x00dev, 23, 0x06); 9888 rt2800_bbp_write(rt2x00dev, 24, 0x06); 9889 count_step = 1; 9890 } else { 9891 rt2800_bbp_write(rt2x00dev, 23, 0x1F); 9892 rt2800_bbp_write(rt2x00dev, 24, 0x1F); 9893 count_step = 2; 9894 } 9895 9896 for (; vga_gain[ch_idx] < 19; vga_gain[ch_idx] = (vga_gain[ch_idx] + count_step)) { 9897 rfvalue = rfvga_gain_table[vga_gain[ch_idx]]; 9898 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue); 9899 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue); 9900 9901 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9902 rt2800_bbp_write(rt2x00dev, 158, bbp); 9903 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9904 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0); 9905 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) 9906 p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A); 9907 9908 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9909 rt2800_bbp_write(rt2x00dev, 158, bbp); 9910 rt2800_bbp_write(rt2x00dev, 159, 0x21); 9911 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0); 9912 if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) 9913 p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A); 9914 9915 rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1); 9916 9917 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9918 rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10); 9919 if ((p0_idx10 > 7000 * 7000) || (p1_idx10 > 7000 * 7000)) { 9920 if (vga_gain[ch_idx] != 0) 9921 vga_gain[ch_idx] = vga_gain[ch_idx] - 1; 9922 break; 9923 } 9924 } 9925 9926 if ((p0 > 2500 * 2500) || (p1 > 2500 * 2500)) 9927 break; 9928 } 9929 9930 if (vga_gain[ch_idx] > 18) 9931 vga_gain[ch_idx] = 18; 9932 rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx], 9933 rfvga_gain_table[vga_gain[ch_idx]]); 9934 9935 bbp = (ch_idx == 0) ? 0x29 : 0x47; 9936 rt2800_bbp_write(rt2x00dev, 158, bbp); 9937 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9938 9939 rt2800_iq_search(rt2x00dev, ch_idx, ger, per); 9940 } 9941 9942 rt2800_bbp_write(rt2x00dev, 23, 0x00); 9943 rt2800_bbp_write(rt2x00dev, 24, 0x00); 9944 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 9945 9946 rt2800_bbp_write(rt2x00dev, 158, 0x28); 9947 bbp = ger[CHAIN_0] & 0x0F; 9948 rt2800_bbp_write(rt2x00dev, 159, bbp); 9949 9950 rt2800_bbp_write(rt2x00dev, 158, 0x29); 9951 bbp = per[CHAIN_0] & 0x3F; 9952 rt2800_bbp_write(rt2x00dev, 159, bbp); 9953 9954 rt2800_bbp_write(rt2x00dev, 158, 0x46); 9955 bbp = ger[CHAIN_1] & 0x0F; 9956 rt2800_bbp_write(rt2x00dev, 159, bbp); 9957 9958 rt2800_bbp_write(rt2x00dev, 158, 0x47); 9959 bbp = per[CHAIN_1] & 0x3F; 9960 rt2800_bbp_write(rt2x00dev, 159, bbp); 9961 9962 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) { 9963 rt2800_bbp_write(rt2x00dev, 1, bbpr1); 9964 rt2800_bbp_write(rt2x00dev, 241, bbpr241); 9965 rt2800_bbp_write(rt2x00dev, 242, bbpr242); 9966 } 9967 rt2800_bbp_write(rt2x00dev, 244, 0x00); 9968 9969 rt2800_bbp_write(rt2x00dev, 158, 0x00); 9970 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9971 rt2800_bbp_write(rt2x00dev, 158, 0xB0); 9972 rt2800_bbp_write(rt2x00dev, 159, 0x00); 9973 9974 rt2800_bbp_write(rt2x00dev, 30, bbpr30); 9975 rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39); 9976 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42); 9977 9978 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) 9979 rt2800_bbp_write(rt2x00dev, 4, bbpr4); 9980 9981 rt2800_bbp_write(rt2x00dev, 21, 0x01); 9982 udelay(1); 9983 rt2800_bbp_write(rt2x00dev, 21, 0x00); 9984 9985 rt2800_rf_configrecover(rt2x00dev, rf_store); 9986 9987 rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1); 9988 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00); 9989 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00); 9990 rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2); 9991 udelay(1); 9992 rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3); 9993 rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4); 9994 rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5); 9995 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl); 9996 rt2800_register_write(rt2x00dev, 0x13b8, mac13b8); 9997} 9998 9999static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev, 10000 bool set_bw, bool is_ht40) 10001{ 10002 u8 bbp_val; 10003 10004 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 10005 bbp_val |= 0x1; 10006 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 10007 usleep_range(100, 200); 10008 10009 if (set_bw) { 10010 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 10011 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40); 10012 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 10013 usleep_range(100, 200); 10014 } 10015 10016 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 10017 bbp_val &= (~0x1); 10018 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 10019 usleep_range(100, 200); 10020} 10021 10022static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal) 10023{ 10024 u8 rf_val; 10025 10026 if (btxcal) 10027 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 10028 else 10029 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02); 10030 10031 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06); 10032 10033 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 10034 rf_val |= 0x80; 10035 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val); 10036 10037 if (btxcal) { 10038 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1); 10039 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20); 10040 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 10041 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 10042 rf_val &= (~0x3F); 10043 rf_val |= 0x3F; 10044 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 10045 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 10046 rf_val &= (~0x3F); 10047 rf_val |= 0x3F; 10048 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 10049 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31); 10050 } else { 10051 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1); 10052 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18); 10053 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 10054 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 10055 rf_val &= (~0x3F); 10056 rf_val |= 0x34; 10057 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 10058 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 10059 rf_val &= (~0x3F); 10060 rf_val |= 0x34; 10061 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 10062 } 10063 10064 return 0; 10065} 10066 10067static s8 rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev) 10068{ 10069 unsigned int cnt; 10070 u8 bbp_val; 10071 s8 cal_val; 10072 10073 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82); 10074 10075 cnt = 0; 10076 do { 10077 usleep_range(500, 2000); 10078 bbp_val = rt2800_bbp_read(rt2x00dev, 159); 10079 if (bbp_val == 0x02 || cnt == 20) 10080 break; 10081 10082 cnt++; 10083 } while (cnt < 20); 10084 10085 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39); 10086 cal_val = bbp_val & 0x7F; 10087 if (cal_val >= 0x40) 10088 cal_val -= 128; 10089 10090 return cal_val; 10091} 10092 10093static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, 10094 bool btxcal) 10095{ 10096 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 10097 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc; 10098 u8 filter_target; 10099 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02; 10100 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31; 10101 int loop = 0, is_ht40, cnt; 10102 u8 bbp_val, rf_val; 10103 s8 cal_r32_init, cal_r32_val, cal_diff; 10104 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05; 10105 u8 saverfb5r06, saverfb5r07; 10106 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20; 10107 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41; 10108 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46; 10109 u8 saverfb5r58, saverfb5r59; 10110 u8 savebbp159r0, savebbp159r2, savebbpr23; 10111 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0; 10112 10113 /* Save MAC registers */ 10114 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 10115 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 10116 10117 /* save BBP registers */ 10118 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23); 10119 10120 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0); 10121 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2); 10122 10123 /* Save RF registers */ 10124 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 10125 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 10126 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 10127 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 10128 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5); 10129 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 10130 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 10131 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 10132 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 10133 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 10134 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 10135 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 10136 10137 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37); 10138 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38); 10139 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39); 10140 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40); 10141 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41); 10142 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42); 10143 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43); 10144 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44); 10145 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45); 10146 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46); 10147 10148 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 10149 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 10150 10151 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 10152 rf_val |= 0x3; 10153 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 10154 10155 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 10156 rf_val |= 0x1; 10157 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val); 10158 10159 cnt = 0; 10160 do { 10161 usleep_range(500, 2000); 10162 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 10163 if (((rf_val & 0x1) == 0x00) || (cnt == 40)) 10164 break; 10165 cnt++; 10166 } while (cnt < 40); 10167 10168 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 10169 rf_val &= (~0x3); 10170 rf_val |= 0x1; 10171 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 10172 10173 /* I-3 */ 10174 bbp_val = rt2800_bbp_read(rt2x00dev, 23); 10175 bbp_val &= (~0x1F); 10176 bbp_val |= 0x10; 10177 rt2800_bbp_write(rt2x00dev, 23, bbp_val); 10178 10179 do { 10180 /* I-4,5,6,7,8,9 */ 10181 if (loop == 0) { 10182 is_ht40 = false; 10183 10184 if (btxcal) 10185 filter_target = tx_filter_target_20m; 10186 else 10187 filter_target = rx_filter_target_20m; 10188 } else { 10189 is_ht40 = true; 10190 10191 if (btxcal) 10192 filter_target = tx_filter_target_40m; 10193 else 10194 filter_target = rx_filter_target_40m; 10195 } 10196 10197 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 10198 rf_val &= (~0x04); 10199 if (loop == 1) 10200 rf_val |= 0x4; 10201 10202 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val); 10203 10204 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40); 10205 10206 rt2800_rf_lp_config(rt2x00dev, btxcal); 10207 if (btxcal) { 10208 tx_agc_fc = 0; 10209 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 10210 rf_val &= (~0x7F); 10211 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 10212 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 10213 rf_val &= (~0x7F); 10214 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 10215 } else { 10216 rx_agc_fc = 0; 10217 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 10218 rf_val &= (~0x7F); 10219 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 10220 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 10221 rf_val &= (~0x7F); 10222 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 10223 } 10224 10225 usleep_range(1000, 2000); 10226 10227 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 10228 bbp_val &= (~0x6); 10229 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 10230 10231 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 10232 10233 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 10234 10235 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 10236 bbp_val |= 0x6; 10237 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 10238do_cal: 10239 if (btxcal) { 10240 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 10241 rf_val &= (~0x7F); 10242 rf_val |= tx_agc_fc; 10243 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 10244 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 10245 rf_val &= (~0x7F); 10246 rf_val |= tx_agc_fc; 10247 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 10248 } else { 10249 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 10250 rf_val &= (~0x7F); 10251 rf_val |= rx_agc_fc; 10252 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 10253 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 10254 rf_val &= (~0x7F); 10255 rf_val |= rx_agc_fc; 10256 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 10257 } 10258 10259 usleep_range(500, 1000); 10260 10261 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 10262 10263 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 10264 10265 cal_diff = cal_r32_init - cal_r32_val; 10266 10267 if (btxcal) 10268 cmm_agc_fc = tx_agc_fc; 10269 else 10270 cmm_agc_fc = rx_agc_fc; 10271 10272 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) || 10273 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) { 10274 if (btxcal) 10275 tx_agc_fc = 0; 10276 else 10277 rx_agc_fc = 0; 10278 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) { 10279 if (btxcal) 10280 tx_agc_fc++; 10281 else 10282 rx_agc_fc++; 10283 goto do_cal; 10284 } 10285 10286 if (btxcal) { 10287 if (loop == 0) 10288 drv_data->tx_calibration_bw20 = tx_agc_fc; 10289 else 10290 drv_data->tx_calibration_bw40 = tx_agc_fc; 10291 } else { 10292 if (loop == 0) 10293 drv_data->rx_calibration_bw20 = rx_agc_fc; 10294 else 10295 drv_data->rx_calibration_bw40 = rx_agc_fc; 10296 } 10297 10298 loop++; 10299 } while (loop <= 1); 10300 10301 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00); 10302 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01); 10303 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03); 10304 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04); 10305 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05); 10306 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06); 10307 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07); 10308 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08); 10309 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); 10310 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); 10311 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); 10312 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); 10313 10314 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37); 10315 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38); 10316 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39); 10317 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40); 10318 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41); 10319 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42); 10320 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43); 10321 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44); 10322 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45); 10323 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46); 10324 10325 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58); 10326 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59); 10327 10328 rt2800_bbp_write(rt2x00dev, 23, savebbpr23); 10329 10330 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0); 10331 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2); 10332 10333 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 10334 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 10335 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)); 10336 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 10337 10338 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); 10339 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); 10340} 10341 10342static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev) 10343{ 10344 /* Initialize RF central register to default value */ 10345 rt2800_rfcsr_write(rt2x00dev, 0, 0x02); 10346 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 10347 rt2800_rfcsr_write(rt2x00dev, 2, 0x33); 10348 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF); 10349 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 10350 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 10351 rt2800_rfcsr_write(rt2x00dev, 6, 0x00); 10352 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 10353 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 10354 rt2800_rfcsr_write(rt2x00dev, 9, 0x00); 10355 rt2800_rfcsr_write(rt2x00dev, 10, 0x00); 10356 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 10357 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset); 10358 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 10359 rt2800_rfcsr_write(rt2x00dev, 14, 0x40); 10360 rt2800_rfcsr_write(rt2x00dev, 15, 0x22); 10361 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C); 10362 rt2800_rfcsr_write(rt2x00dev, 17, 0x00); 10363 rt2800_rfcsr_write(rt2x00dev, 18, 0x00); 10364 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 10365 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0); 10366 rt2800_rfcsr_write(rt2x00dev, 21, 0x12); 10367 rt2800_rfcsr_write(rt2x00dev, 22, 0x07); 10368 rt2800_rfcsr_write(rt2x00dev, 23, 0x13); 10369 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE); 10370 rt2800_rfcsr_write(rt2x00dev, 25, 0x24); 10371 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A); 10372 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 10373 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 10374 rt2800_rfcsr_write(rt2x00dev, 29, 0x05); 10375 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 10376 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 10377 rt2800_rfcsr_write(rt2x00dev, 32, 0x00); 10378 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 10379 rt2800_rfcsr_write(rt2x00dev, 34, 0x00); 10380 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 10381 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 10382 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 10383 rt2800_rfcsr_write(rt2x00dev, 38, 0x00); 10384 rt2800_rfcsr_write(rt2x00dev, 39, 0x00); 10385 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 10386 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0); 10387 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B); 10388 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 10389 10390 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 10391 if (rt2800_clk_is_20mhz(rt2x00dev)) 10392 rt2800_rfcsr_write(rt2x00dev, 13, 0x03); 10393 else 10394 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 10395 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C); 10396 rt2800_rfcsr_write(rt2x00dev, 16, 0x80); 10397 rt2800_rfcsr_write(rt2x00dev, 17, 0x99); 10398 rt2800_rfcsr_write(rt2x00dev, 18, 0x99); 10399 rt2800_rfcsr_write(rt2x00dev, 19, 0x09); 10400 rt2800_rfcsr_write(rt2x00dev, 20, 0x50); 10401 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0); 10402 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 10403 rt2800_rfcsr_write(rt2x00dev, 23, 0x06); 10404 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 10405 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 10406 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D); 10407 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 10408 rt2800_rfcsr_write(rt2x00dev, 28, 0x61); 10409 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5); 10410 rt2800_rfcsr_write(rt2x00dev, 43, 0x02); 10411 10412 rt2800_rfcsr_write(rt2x00dev, 28, 0x62); 10413 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD); 10414 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 10415 10416 /* Initialize RF channel register to default value */ 10417 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03); 10418 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00); 10419 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00); 10420 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00); 10421 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00); 10422 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08); 10423 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00); 10424 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51); 10425 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53); 10426 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16); 10427 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61); 10428 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 10429 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22); 10430 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D); 10431 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 10432 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13); 10433 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22); 10434 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27); 10435 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02); 10436 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 10437 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01); 10438 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52); 10439 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80); 10440 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3); 10441 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00); 10442 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00); 10443 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00); 10444 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00); 10445 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C); 10446 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B); 10447 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B); 10448 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31); 10449 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D); 10450 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00); 10451 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6); 10452 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55); 10453 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00); 10454 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB); 10455 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3); 10456 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3); 10457 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03); 10458 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00); 10459 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00); 10460 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3); 10461 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3); 10462 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 10463 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07); 10464 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68); 10465 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF); 10466 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C); 10467 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07); 10468 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8); 10469 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85); 10470 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10); 10471 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07); 10472 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A); 10473 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85); 10474 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10); 10475 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C); 10476 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00); 10477 10478 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5); 10479 10480 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47); 10481 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71); 10482 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33); 10483 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E); 10484 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23); 10485 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4); 10486 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02); 10487 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12); 10488 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C); 10489 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB); 10490 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D); 10491 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6); 10492 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08); 10493 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4); 10494 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 10495 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3); 10496 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 10497 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 10498 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67); 10499 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69); 10500 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF); 10501 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27); 10502 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20); 10503 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 10504 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF); 10505 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C); 10506 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20); 10507 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 10508 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7); 10509 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); 10510 10511 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51); 10512 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 10513 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 10514 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C); 10515 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64); 10516 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51); 10517 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36); 10518 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 10519 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); 10520 10521 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C); 10522 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC); 10523 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F); 10524 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 10525 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 10526 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 10527 10528 /* Initialize RF channel register for DRQFN */ 10529 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 10530 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3); 10531 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5); 10532 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28); 10533 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68); 10534 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7); 10535 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02); 10536 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7); 10537 10538 /* Initialize RF DC calibration register to default value */ 10539 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47); 10540 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00); 10541 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00); 10542 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00); 10543 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00); 10544 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 10545 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 10546 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 10547 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 10548 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00); 10549 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07); 10550 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01); 10551 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07); 10552 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07); 10553 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07); 10554 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20); 10555 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22); 10556 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00); 10557 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00); 10558 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00); 10559 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); 10560 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1); 10561 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11); 10562 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02); 10563 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41); 10564 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20); 10565 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00); 10566 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7); 10567 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2); 10568 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20); 10569 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49); 10570 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20); 10571 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04); 10572 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1); 10573 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1); 10574 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01); 10575 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00); 10576 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00); 10577 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00); 10578 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00); 10579 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00); 10580 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00); 10581 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E); 10582 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D); 10583 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E); 10584 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D); 10585 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E); 10586 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D); 10587 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00); 10588 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00); 10589 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00); 10590 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00); 10591 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00); 10592 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 10593 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 10594 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A); 10595 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00); 10596 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00); 10597 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00); 10598 10599 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08); 10600 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04); 10601 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20); 10602 10603 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 10604 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); 10605 10606 rt2800_r_calibration(rt2x00dev); 10607 rt2800_rf_self_txdc_cal(rt2x00dev); 10608 rt2800_rxdcoc_calibration(rt2x00dev); 10609 rt2800_bw_filter_calibration(rt2x00dev, true); 10610 rt2800_bw_filter_calibration(rt2x00dev, false); 10611 rt2800_loft_iq_calibration(rt2x00dev); 10612 rt2800_rxiq_calibration(rt2x00dev); 10613} 10614 10615static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 10616{ 10617 if (rt2800_is_305x_soc(rt2x00dev)) { 10618 rt2800_init_rfcsr_305x_soc(rt2x00dev); 10619 return; 10620 } 10621 10622 switch (rt2x00dev->chip.rt) { 10623 case RT3070: 10624 case RT3071: 10625 case RT3090: 10626 rt2800_init_rfcsr_30xx(rt2x00dev); 10627 break; 10628 case RT3290: 10629 rt2800_init_rfcsr_3290(rt2x00dev); 10630 break; 10631 case RT3352: 10632 rt2800_init_rfcsr_3352(rt2x00dev); 10633 break; 10634 case RT3390: 10635 rt2800_init_rfcsr_3390(rt2x00dev); 10636 break; 10637 case RT3883: 10638 rt2800_init_rfcsr_3883(rt2x00dev); 10639 break; 10640 case RT3572: 10641 rt2800_init_rfcsr_3572(rt2x00dev); 10642 break; 10643 case RT3593: 10644 rt2800_init_rfcsr_3593(rt2x00dev); 10645 break; 10646 case RT5350: 10647 rt2800_init_rfcsr_5350(rt2x00dev); 10648 break; 10649 case RT5390: 10650 rt2800_init_rfcsr_5390(rt2x00dev); 10651 break; 10652 case RT5392: 10653 rt2800_init_rfcsr_5392(rt2x00dev); 10654 break; 10655 case RT5592: 10656 rt2800_init_rfcsr_5592(rt2x00dev); 10657 break; 10658 case RT6352: 10659 rt2800_init_rfcsr_6352(rt2x00dev); 10660 break; 10661 } 10662} 10663 10664int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) 10665{ 10666 u32 reg; 10667 u16 word; 10668 10669 /* 10670 * Initialize MAC registers. 10671 */ 10672 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 10673 rt2800_init_registers(rt2x00dev))) 10674 return -EIO; 10675 10676 /* 10677 * Wait BBP/RF to wake up. 10678 */ 10679 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY))) 10680 return -EIO; 10681 10682 /* 10683 * Send signal during boot time to initialize firmware. 10684 */ 10685 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 10686 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 10687 if (rt2x00_is_usb(rt2x00dev)) 10688 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 10689 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 10690 msleep(1); 10691 10692 /* 10693 * Make sure BBP is up and running. 10694 */ 10695 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) 10696 return -EIO; 10697 10698 /* 10699 * Initialize BBP/RF registers. 10700 */ 10701 rt2800_init_bbp(rt2x00dev); 10702 rt2800_init_rfcsr(rt2x00dev); 10703 10704 if (rt2x00_is_usb(rt2x00dev) && 10705 (rt2x00_rt(rt2x00dev, RT3070) || 10706 rt2x00_rt(rt2x00dev, RT3071) || 10707 rt2x00_rt(rt2x00dev, RT3572))) { 10708 udelay(200); 10709 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 10710 udelay(10); 10711 } 10712 10713 /* 10714 * Enable RX. 10715 */ 10716 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 10717 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 10718 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 10719 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 10720 10721 udelay(50); 10722 10723 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 10724 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 10725 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 10726 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 10727 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 10728 10729 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 10730 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 10731 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); 10732 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 10733 10734 /* 10735 * Initialize LED control 10736 */ 10737 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF); 10738 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, 10739 word & 0xff, (word >> 8) & 0xff); 10740 10741 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF); 10742 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, 10743 word & 0xff, (word >> 8) & 0xff); 10744 10745 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY); 10746 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, 10747 word & 0xff, (word >> 8) & 0xff); 10748 10749 return 0; 10750} 10751EXPORT_SYMBOL_GPL(rt2800_enable_radio); 10752 10753void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) 10754{ 10755 u32 reg; 10756 10757 rt2800_disable_wpdma(rt2x00dev); 10758 10759 /* Wait for DMA, ignore error */ 10760 rt2800_wait_wpdma_ready(rt2x00dev); 10761 10762 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 10763 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); 10764 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 10765 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 10766} 10767EXPORT_SYMBOL_GPL(rt2800_disable_radio); 10768 10769int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 10770{ 10771 u32 reg; 10772 u16 efuse_ctrl_reg; 10773 10774 if (rt2x00_rt(rt2x00dev, RT3290)) 10775 efuse_ctrl_reg = EFUSE_CTRL_3290; 10776 else 10777 efuse_ctrl_reg = EFUSE_CTRL; 10778 10779 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg); 10780 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 10781} 10782EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 10783 10784static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 10785{ 10786 u32 reg; 10787 u16 efuse_ctrl_reg; 10788 u16 efuse_data0_reg; 10789 u16 efuse_data1_reg; 10790 u16 efuse_data2_reg; 10791 u16 efuse_data3_reg; 10792 10793 if (rt2x00_rt(rt2x00dev, RT3290)) { 10794 efuse_ctrl_reg = EFUSE_CTRL_3290; 10795 efuse_data0_reg = EFUSE_DATA0_3290; 10796 efuse_data1_reg = EFUSE_DATA1_3290; 10797 efuse_data2_reg = EFUSE_DATA2_3290; 10798 efuse_data3_reg = EFUSE_DATA3_3290; 10799 } else { 10800 efuse_ctrl_reg = EFUSE_CTRL; 10801 efuse_data0_reg = EFUSE_DATA0; 10802 efuse_data1_reg = EFUSE_DATA1; 10803 efuse_data2_reg = EFUSE_DATA2; 10804 efuse_data3_reg = EFUSE_DATA3; 10805 } 10806 mutex_lock(&rt2x00dev->csr_mutex); 10807 10808 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg); 10809 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); 10810 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); 10811 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); 10812 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); 10813 10814 /* Wait until the EEPROM has been loaded */ 10815 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); 10816 /* Apparently the data is read from end to start */ 10817 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg); 10818 /* The returned value is in CPU order, but eeprom is le */ 10819 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 10820 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg); 10821 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 10822 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg); 10823 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 10824 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg); 10825 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 10826 10827 mutex_unlock(&rt2x00dev->csr_mutex); 10828} 10829 10830int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 10831{ 10832 unsigned int i; 10833 10834 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) 10835 rt2800_efuse_read(rt2x00dev, i); 10836 10837 return 0; 10838} 10839EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 10840 10841static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) 10842{ 10843 u16 word; 10844 10845 if (rt2x00_rt(rt2x00dev, RT3593) || 10846 rt2x00_rt(rt2x00dev, RT3883)) 10847 return 0; 10848 10849 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG); 10850 if ((word & 0x00ff) != 0x00ff) 10851 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); 10852 10853 return 0; 10854} 10855 10856static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) 10857{ 10858 u16 word; 10859 10860 if (rt2x00_rt(rt2x00dev, RT3593) || 10861 rt2x00_rt(rt2x00dev, RT3883)) 10862 return 0; 10863 10864 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A); 10865 if ((word & 0x00ff) != 0x00ff) 10866 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); 10867 10868 return 0; 10869} 10870 10871static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 10872{ 10873 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 10874 u16 word; 10875 u8 *mac; 10876 u8 default_lna_gain; 10877 int retval; 10878 10879 /* 10880 * Read the EEPROM. 10881 */ 10882 retval = rt2800_read_eeprom(rt2x00dev); 10883 if (retval) 10884 return retval; 10885 10886 /* 10887 * Start validation of the data that has been read. 10888 */ 10889 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 10890 rt2x00lib_set_mac_address(rt2x00dev, mac); 10891 10892 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 10893 if (word == 0xffff) { 10894 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 10895 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); 10896 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); 10897 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 10898 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 10899 } else if (rt2x00_rt(rt2x00dev, RT2860) || 10900 rt2x00_rt(rt2x00dev, RT2872)) { 10901 /* 10902 * There is a max of 2 RX streams for RT28x0 series 10903 */ 10904 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) 10905 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 10906 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 10907 } 10908 10909 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 10910 if (word == 0xffff) { 10911 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); 10912 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); 10913 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); 10914 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); 10915 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); 10916 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); 10917 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); 10918 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); 10919 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); 10920 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); 10921 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); 10922 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); 10923 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); 10924 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); 10925 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); 10926 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); 10927 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 10928 } 10929 10930 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 10931 if ((word & 0x00ff) == 0x00ff) { 10932 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 10933 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 10934 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 10935 } 10936 if ((word & 0xff00) == 0xff00) { 10937 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 10938 LED_MODE_TXRX_ACTIVITY); 10939 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 10940 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 10941 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); 10942 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); 10943 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); 10944 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word); 10945 } 10946 10947 /* 10948 * During the LNA validation we are going to use 10949 * lna0 as correct value. Note that EEPROM_LNA 10950 * is never validated. 10951 */ 10952 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 10953 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); 10954 10955 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 10956 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) 10957 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); 10958 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) 10959 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); 10960 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); 10961 10962 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); 10963 10964 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 10965 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) 10966 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); 10967 if (!rt2x00_rt(rt2x00dev, RT3593) && 10968 !rt2x00_rt(rt2x00dev, RT3883)) { 10969 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || 10970 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) 10971 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, 10972 default_lna_gain); 10973 } 10974 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); 10975 10976 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); 10977 10978 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 10979 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) 10980 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); 10981 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) 10982 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); 10983 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); 10984 10985 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 10986 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) 10987 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); 10988 if (!rt2x00_rt(rt2x00dev, RT3593) && 10989 !rt2x00_rt(rt2x00dev, RT3883)) { 10990 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || 10991 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) 10992 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, 10993 default_lna_gain); 10994 } 10995 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 10996 10997 if (rt2x00_rt(rt2x00dev, RT3593) || 10998 rt2x00_rt(rt2x00dev, RT3883)) { 10999 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 11000 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || 11001 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) 11002 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 11003 default_lna_gain); 11004 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 || 11005 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff) 11006 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 11007 default_lna_gain); 11008 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word); 11009 } 11010 11011 return 0; 11012} 11013 11014static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 11015{ 11016 u16 value; 11017 u16 eeprom; 11018 u16 rf; 11019 11020 /* 11021 * Read EEPROM word for configuration. 11022 */ 11023 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 11024 11025 /* 11026 * Identify RF chipset by EEPROM value 11027 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 11028 * RT53xx: defined in "EEPROM_CHIP_ID" field 11029 */ 11030 if (rt2x00_rt(rt2x00dev, RT3290) || 11031 rt2x00_rt(rt2x00dev, RT5390) || 11032 rt2x00_rt(rt2x00dev, RT5392) || 11033 rt2x00_rt(rt2x00dev, RT6352)) 11034 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID); 11035 else if (rt2x00_rt(rt2x00dev, RT3352)) 11036 rf = RF3322; 11037 else if (rt2x00_rt(rt2x00dev, RT3883)) 11038 rf = RF3853; 11039 else if (rt2x00_rt(rt2x00dev, RT5350)) 11040 rf = RF5350; 11041 else if (rt2x00_rt(rt2x00dev, RT5592)) 11042 rf = RF5592; 11043 else 11044 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 11045 11046 switch (rf) { 11047 case RF2820: 11048 case RF2850: 11049 case RF2720: 11050 case RF2750: 11051 case RF3020: 11052 case RF2020: 11053 case RF3021: 11054 case RF3022: 11055 case RF3052: 11056 case RF3053: 11057 case RF3070: 11058 case RF3290: 11059 case RF3320: 11060 case RF3322: 11061 case RF3853: 11062 case RF5350: 11063 case RF5360: 11064 case RF5362: 11065 case RF5370: 11066 case RF5372: 11067 case RF5390: 11068 case RF5392: 11069 case RF5592: 11070 case RF7620: 11071 break; 11072 default: 11073 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", 11074 rf); 11075 return -ENODEV; 11076 } 11077 11078 rt2x00_set_rf(rt2x00dev, rf); 11079 11080 /* 11081 * Identify default antenna configuration. 11082 */ 11083 rt2x00dev->default_ant.tx_chain_num = 11084 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); 11085 rt2x00dev->default_ant.rx_chain_num = 11086 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); 11087 11088 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 11089 11090 if (rt2x00_rt(rt2x00dev, RT3070) || 11091 rt2x00_rt(rt2x00dev, RT3090) || 11092 rt2x00_rt(rt2x00dev, RT3352) || 11093 rt2x00_rt(rt2x00dev, RT3390)) { 11094 value = rt2x00_get_field16(eeprom, 11095 EEPROM_NIC_CONF1_ANT_DIVERSITY); 11096 switch (value) { 11097 case 0: 11098 case 1: 11099 case 2: 11100 rt2x00dev->default_ant.tx = ANTENNA_A; 11101 rt2x00dev->default_ant.rx = ANTENNA_A; 11102 break; 11103 case 3: 11104 rt2x00dev->default_ant.tx = ANTENNA_A; 11105 rt2x00dev->default_ant.rx = ANTENNA_B; 11106 break; 11107 } 11108 } else { 11109 rt2x00dev->default_ant.tx = ANTENNA_A; 11110 rt2x00dev->default_ant.rx = ANTENNA_A; 11111 } 11112 11113 /* These chips have hardware RX antenna diversity */ 11114 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 11115 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 11116 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */ 11117 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */ 11118 } 11119 11120 /* 11121 * Determine external LNA informations. 11122 */ 11123 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) 11124 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 11125 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) 11126 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 11127 11128 /* 11129 * Detect if this device has an hardware controlled radio. 11130 */ 11131 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) 11132 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 11133 11134 /* 11135 * Detect if this device has Bluetooth co-existence. 11136 */ 11137 if (!rt2x00_rt(rt2x00dev, RT3352) && 11138 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) 11139 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); 11140 11141 /* 11142 * Read frequency offset and RF programming sequence. 11143 */ 11144 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 11145 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 11146 11147 /* 11148 * Store led settings, for correct led behaviour. 11149 */ 11150#ifdef CONFIG_RT2X00_LIB_LEDS 11151 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 11152 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 11153 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 11154 11155 rt2x00dev->led_mcu_reg = eeprom; 11156#endif /* CONFIG_RT2X00_LIB_LEDS */ 11157 11158 /* 11159 * Check if support EIRP tx power limit feature. 11160 */ 11161 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 11162 11163 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < 11164 EIRP_MAX_TX_POWER_LIMIT) 11165 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); 11166 11167 /* 11168 * Detect if device uses internal or external PA 11169 */ 11170 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 11171 11172 if (rt2x00_rt(rt2x00dev, RT3352) || 11173 rt2x00_rt(rt2x00dev, RT6352)) { 11174 if (rt2x00_get_field16(eeprom, 11175 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352)) 11176 __set_bit(CAPABILITY_EXTERNAL_PA_TX0, 11177 &rt2x00dev->cap_flags); 11178 if (rt2x00_get_field16(eeprom, 11179 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352)) 11180 __set_bit(CAPABILITY_EXTERNAL_PA_TX1, 11181 &rt2x00dev->cap_flags); 11182 } 11183 11184 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF2); 11185 11186 if (rt2x00_rt(rt2x00dev, RT6352) && eeprom != 0 && eeprom != 0xffff) { 11187 if (!rt2x00_get_field16(eeprom, 11188 EEPROM_NIC_CONF2_EXTERNAL_PA)) { 11189 __clear_bit(CAPABILITY_EXTERNAL_PA_TX0, 11190 &rt2x00dev->cap_flags); 11191 __clear_bit(CAPABILITY_EXTERNAL_PA_TX1, 11192 &rt2x00dev->cap_flags); 11193 } 11194 } 11195 11196 return 0; 11197} 11198 11199/* 11200 * RF value list for rt28xx 11201 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 11202 */ 11203static const struct rf_channel rf_vals[] = { 11204 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, 11205 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, 11206 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, 11207 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, 11208 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, 11209 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, 11210 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, 11211 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, 11212 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, 11213 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, 11214 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, 11215 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, 11216 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, 11217 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, 11218 11219 /* 802.11 UNI / HyperLan 2 */ 11220 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, 11221 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, 11222 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, 11223 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, 11224 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, 11225 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, 11226 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, 11227 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, 11228 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, 11229 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, 11230 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, 11231 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, 11232 11233 /* 802.11 HyperLan 2 */ 11234 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, 11235 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, 11236 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, 11237 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, 11238 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, 11239 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, 11240 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, 11241 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, 11242 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, 11243 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, 11244 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, 11245 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, 11246 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, 11247 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, 11248 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, 11249 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, 11250 11251 /* 802.11 UNII */ 11252 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, 11253 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, 11254 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, 11255 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, 11256 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, 11257 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, 11258 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, 11259 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, 11260 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, 11261 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, 11262 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, 11263 11264 /* 802.11 Japan */ 11265 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, 11266 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, 11267 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, 11268 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, 11269 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, 11270 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, 11271 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, 11272}; 11273 11274/* 11275 * RF value list for rt3xxx 11276 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053) 11277 */ 11278static const struct rf_channel rf_vals_3x[] = { 11279 {1, 241, 2, 2 }, 11280 {2, 241, 2, 7 }, 11281 {3, 242, 2, 2 }, 11282 {4, 242, 2, 7 }, 11283 {5, 243, 2, 2 }, 11284 {6, 243, 2, 7 }, 11285 {7, 244, 2, 2 }, 11286 {8, 244, 2, 7 }, 11287 {9, 245, 2, 2 }, 11288 {10, 245, 2, 7 }, 11289 {11, 246, 2, 2 }, 11290 {12, 246, 2, 7 }, 11291 {13, 247, 2, 2 }, 11292 {14, 248, 2, 4 }, 11293 11294 /* 802.11 UNI / HyperLan 2 */ 11295 {36, 0x56, 0, 4}, 11296 {38, 0x56, 0, 6}, 11297 {40, 0x56, 0, 8}, 11298 {44, 0x57, 0, 0}, 11299 {46, 0x57, 0, 2}, 11300 {48, 0x57, 0, 4}, 11301 {52, 0x57, 0, 8}, 11302 {54, 0x57, 0, 10}, 11303 {56, 0x58, 0, 0}, 11304 {60, 0x58, 0, 4}, 11305 {62, 0x58, 0, 6}, 11306 {64, 0x58, 0, 8}, 11307 11308 /* 802.11 HyperLan 2 */ 11309 {100, 0x5b, 0, 8}, 11310 {102, 0x5b, 0, 10}, 11311 {104, 0x5c, 0, 0}, 11312 {108, 0x5c, 0, 4}, 11313 {110, 0x5c, 0, 6}, 11314 {112, 0x5c, 0, 8}, 11315 {116, 0x5d, 0, 0}, 11316 {118, 0x5d, 0, 2}, 11317 {120, 0x5d, 0, 4}, 11318 {124, 0x5d, 0, 8}, 11319 {126, 0x5d, 0, 10}, 11320 {128, 0x5e, 0, 0}, 11321 {132, 0x5e, 0, 4}, 11322 {134, 0x5e, 0, 6}, 11323 {136, 0x5e, 0, 8}, 11324 {140, 0x5f, 0, 0}, 11325 11326 /* 802.11 UNII */ 11327 {149, 0x5f, 0, 9}, 11328 {151, 0x5f, 0, 11}, 11329 {153, 0x60, 0, 1}, 11330 {157, 0x60, 0, 5}, 11331 {159, 0x60, 0, 7}, 11332 {161, 0x60, 0, 9}, 11333 {165, 0x61, 0, 1}, 11334 {167, 0x61, 0, 3}, 11335 {169, 0x61, 0, 5}, 11336 {171, 0x61, 0, 7}, 11337 {173, 0x61, 0, 9}, 11338}; 11339 11340/* 11341 * RF value list for rt3xxx with Xtal20MHz 11342 * Supports: 2.4 GHz (all) (RF3322) 11343 */ 11344static const struct rf_channel rf_vals_3x_xtal20[] = { 11345 {1, 0xE2, 2, 0x14}, 11346 {2, 0xE3, 2, 0x14}, 11347 {3, 0xE4, 2, 0x14}, 11348 {4, 0xE5, 2, 0x14}, 11349 {5, 0xE6, 2, 0x14}, 11350 {6, 0xE7, 2, 0x14}, 11351 {7, 0xE8, 2, 0x14}, 11352 {8, 0xE9, 2, 0x14}, 11353 {9, 0xEA, 2, 0x14}, 11354 {10, 0xEB, 2, 0x14}, 11355 {11, 0xEC, 2, 0x14}, 11356 {12, 0xED, 2, 0x14}, 11357 {13, 0xEE, 2, 0x14}, 11358 {14, 0xF0, 2, 0x18}, 11359}; 11360 11361static const struct rf_channel rf_vals_3853[] = { 11362 {1, 241, 6, 2}, 11363 {2, 241, 6, 7}, 11364 {3, 242, 6, 2}, 11365 {4, 242, 6, 7}, 11366 {5, 243, 6, 2}, 11367 {6, 243, 6, 7}, 11368 {7, 244, 6, 2}, 11369 {8, 244, 6, 7}, 11370 {9, 245, 6, 2}, 11371 {10, 245, 6, 7}, 11372 {11, 246, 6, 2}, 11373 {12, 246, 6, 7}, 11374 {13, 247, 6, 2}, 11375 {14, 248, 6, 4}, 11376 11377 {36, 0x56, 8, 4}, 11378 {38, 0x56, 8, 6}, 11379 {40, 0x56, 8, 8}, 11380 {44, 0x57, 8, 0}, 11381 {46, 0x57, 8, 2}, 11382 {48, 0x57, 8, 4}, 11383 {52, 0x57, 8, 8}, 11384 {54, 0x57, 8, 10}, 11385 {56, 0x58, 8, 0}, 11386 {60, 0x58, 8, 4}, 11387 {62, 0x58, 8, 6}, 11388 {64, 0x58, 8, 8}, 11389 11390 {100, 0x5b, 8, 8}, 11391 {102, 0x5b, 8, 10}, 11392 {104, 0x5c, 8, 0}, 11393 {108, 0x5c, 8, 4}, 11394 {110, 0x5c, 8, 6}, 11395 {112, 0x5c, 8, 8}, 11396 {114, 0x5c, 8, 10}, 11397 {116, 0x5d, 8, 0}, 11398 {118, 0x5d, 8, 2}, 11399 {120, 0x5d, 8, 4}, 11400 {124, 0x5d, 8, 8}, 11401 {126, 0x5d, 8, 10}, 11402 {128, 0x5e, 8, 0}, 11403 {132, 0x5e, 8, 4}, 11404 {134, 0x5e, 8, 6}, 11405 {136, 0x5e, 8, 8}, 11406 {140, 0x5f, 8, 0}, 11407 11408 {149, 0x5f, 8, 9}, 11409 {151, 0x5f, 8, 11}, 11410 {153, 0x60, 8, 1}, 11411 {157, 0x60, 8, 5}, 11412 {159, 0x60, 8, 7}, 11413 {161, 0x60, 8, 9}, 11414 {165, 0x61, 8, 1}, 11415 {167, 0x61, 8, 3}, 11416 {169, 0x61, 8, 5}, 11417 {171, 0x61, 8, 7}, 11418 {173, 0x61, 8, 9}, 11419}; 11420 11421static const struct rf_channel rf_vals_5592_xtal20[] = { 11422 /* Channel, N, K, mod, R */ 11423 {1, 482, 4, 10, 3}, 11424 {2, 483, 4, 10, 3}, 11425 {3, 484, 4, 10, 3}, 11426 {4, 485, 4, 10, 3}, 11427 {5, 486, 4, 10, 3}, 11428 {6, 487, 4, 10, 3}, 11429 {7, 488, 4, 10, 3}, 11430 {8, 489, 4, 10, 3}, 11431 {9, 490, 4, 10, 3}, 11432 {10, 491, 4, 10, 3}, 11433 {11, 492, 4, 10, 3}, 11434 {12, 493, 4, 10, 3}, 11435 {13, 494, 4, 10, 3}, 11436 {14, 496, 8, 10, 3}, 11437 {36, 172, 8, 12, 1}, 11438 {38, 173, 0, 12, 1}, 11439 {40, 173, 4, 12, 1}, 11440 {42, 173, 8, 12, 1}, 11441 {44, 174, 0, 12, 1}, 11442 {46, 174, 4, 12, 1}, 11443 {48, 174, 8, 12, 1}, 11444 {50, 175, 0, 12, 1}, 11445 {52, 175, 4, 12, 1}, 11446 {54, 175, 8, 12, 1}, 11447 {56, 176, 0, 12, 1}, 11448 {58, 176, 4, 12, 1}, 11449 {60, 176, 8, 12, 1}, 11450 {62, 177, 0, 12, 1}, 11451 {64, 177, 4, 12, 1}, 11452 {100, 183, 4, 12, 1}, 11453 {102, 183, 8, 12, 1}, 11454 {104, 184, 0, 12, 1}, 11455 {106, 184, 4, 12, 1}, 11456 {108, 184, 8, 12, 1}, 11457 {110, 185, 0, 12, 1}, 11458 {112, 185, 4, 12, 1}, 11459 {114, 185, 8, 12, 1}, 11460 {116, 186, 0, 12, 1}, 11461 {118, 186, 4, 12, 1}, 11462 {120, 186, 8, 12, 1}, 11463 {122, 187, 0, 12, 1}, 11464 {124, 187, 4, 12, 1}, 11465 {126, 187, 8, 12, 1}, 11466 {128, 188, 0, 12, 1}, 11467 {130, 188, 4, 12, 1}, 11468 {132, 188, 8, 12, 1}, 11469 {134, 189, 0, 12, 1}, 11470 {136, 189, 4, 12, 1}, 11471 {138, 189, 8, 12, 1}, 11472 {140, 190, 0, 12, 1}, 11473 {149, 191, 6, 12, 1}, 11474 {151, 191, 10, 12, 1}, 11475 {153, 192, 2, 12, 1}, 11476 {155, 192, 6, 12, 1}, 11477 {157, 192, 10, 12, 1}, 11478 {159, 193, 2, 12, 1}, 11479 {161, 193, 6, 12, 1}, 11480 {165, 194, 2, 12, 1}, 11481 {184, 164, 0, 12, 1}, 11482 {188, 164, 4, 12, 1}, 11483 {192, 165, 8, 12, 1}, 11484 {196, 166, 0, 12, 1}, 11485}; 11486 11487static const struct rf_channel rf_vals_5592_xtal40[] = { 11488 /* Channel, N, K, mod, R */ 11489 {1, 241, 2, 10, 3}, 11490 {2, 241, 7, 10, 3}, 11491 {3, 242, 2, 10, 3}, 11492 {4, 242, 7, 10, 3}, 11493 {5, 243, 2, 10, 3}, 11494 {6, 243, 7, 10, 3}, 11495 {7, 244, 2, 10, 3}, 11496 {8, 244, 7, 10, 3}, 11497 {9, 245, 2, 10, 3}, 11498 {10, 245, 7, 10, 3}, 11499 {11, 246, 2, 10, 3}, 11500 {12, 246, 7, 10, 3}, 11501 {13, 247, 2, 10, 3}, 11502 {14, 248, 4, 10, 3}, 11503 {36, 86, 4, 12, 1}, 11504 {38, 86, 6, 12, 1}, 11505 {40, 86, 8, 12, 1}, 11506 {42, 86, 10, 12, 1}, 11507 {44, 87, 0, 12, 1}, 11508 {46, 87, 2, 12, 1}, 11509 {48, 87, 4, 12, 1}, 11510 {50, 87, 6, 12, 1}, 11511 {52, 87, 8, 12, 1}, 11512 {54, 87, 10, 12, 1}, 11513 {56, 88, 0, 12, 1}, 11514 {58, 88, 2, 12, 1}, 11515 {60, 88, 4, 12, 1}, 11516 {62, 88, 6, 12, 1}, 11517 {64, 88, 8, 12, 1}, 11518 {100, 91, 8, 12, 1}, 11519 {102, 91, 10, 12, 1}, 11520 {104, 92, 0, 12, 1}, 11521 {106, 92, 2, 12, 1}, 11522 {108, 92, 4, 12, 1}, 11523 {110, 92, 6, 12, 1}, 11524 {112, 92, 8, 12, 1}, 11525 {114, 92, 10, 12, 1}, 11526 {116, 93, 0, 12, 1}, 11527 {118, 93, 2, 12, 1}, 11528 {120, 93, 4, 12, 1}, 11529 {122, 93, 6, 12, 1}, 11530 {124, 93, 8, 12, 1}, 11531 {126, 93, 10, 12, 1}, 11532 {128, 94, 0, 12, 1}, 11533 {130, 94, 2, 12, 1}, 11534 {132, 94, 4, 12, 1}, 11535 {134, 94, 6, 12, 1}, 11536 {136, 94, 8, 12, 1}, 11537 {138, 94, 10, 12, 1}, 11538 {140, 95, 0, 12, 1}, 11539 {149, 95, 9, 12, 1}, 11540 {151, 95, 11, 12, 1}, 11541 {153, 96, 1, 12, 1}, 11542 {155, 96, 3, 12, 1}, 11543 {157, 96, 5, 12, 1}, 11544 {159, 96, 7, 12, 1}, 11545 {161, 96, 9, 12, 1}, 11546 {165, 97, 1, 12, 1}, 11547 {184, 82, 0, 12, 1}, 11548 {188, 82, 4, 12, 1}, 11549 {192, 82, 8, 12, 1}, 11550 {196, 83, 0, 12, 1}, 11551}; 11552 11553static const struct rf_channel rf_vals_7620[] = { 11554 {1, 0x50, 0x99, 0x99, 1}, 11555 {2, 0x50, 0x44, 0x44, 2}, 11556 {3, 0x50, 0xEE, 0xEE, 2}, 11557 {4, 0x50, 0x99, 0x99, 3}, 11558 {5, 0x51, 0x44, 0x44, 0}, 11559 {6, 0x51, 0xEE, 0xEE, 0}, 11560 {7, 0x51, 0x99, 0x99, 1}, 11561 {8, 0x51, 0x44, 0x44, 2}, 11562 {9, 0x51, 0xEE, 0xEE, 2}, 11563 {10, 0x51, 0x99, 0x99, 3}, 11564 {11, 0x52, 0x44, 0x44, 0}, 11565 {12, 0x52, 0xEE, 0xEE, 0}, 11566 {13, 0x52, 0x99, 0x99, 1}, 11567 {14, 0x52, 0x33, 0x33, 3}, 11568}; 11569 11570static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 11571{ 11572 struct hw_mode_spec *spec = &rt2x00dev->spec; 11573 struct channel_info *info; 11574 s8 *default_power1; 11575 s8 *default_power2; 11576 s8 *default_power3; 11577 unsigned int i, tx_chains, rx_chains; 11578 u32 reg; 11579 11580 /* 11581 * Disable powersaving as default. 11582 */ 11583 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 11584 11585 /* 11586 * Change default retry settings to values corresponding more closely 11587 * to rate[0].count setting of minstrel rate control algorithm. 11588 */ 11589 rt2x00dev->hw->wiphy->retry_short = 2; 11590 rt2x00dev->hw->wiphy->retry_long = 2; 11591 11592 /* 11593 * Initialize all hw fields. 11594 */ 11595 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS); 11596 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION); 11597 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 11598 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 11599 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 11600 11601 /* 11602 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices 11603 * unless we are capable of sending the buffered frames out after the 11604 * DTIM transmission using rt2x00lib_beacondone. This will send out 11605 * multicast and broadcast traffic immediately instead of buffering it 11606 * infinitly and thus dropping it after some time. 11607 */ 11608 if (!rt2x00_is_usb(rt2x00dev)) 11609 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 11610 11611 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE); 11612 11613 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 11614 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 11615 rt2800_eeprom_addr(rt2x00dev, 11616 EEPROM_MAC_ADDR_0)); 11617 11618 /* 11619 * As rt2800 has a global fallback table we cannot specify 11620 * more then one tx rate per frame but since the hw will 11621 * try several rates (based on the fallback table) we should 11622 * initialize max_report_rates to the maximum number of rates 11623 * we are going to try. Otherwise mac80211 will truncate our 11624 * reported tx rates and the rc algortihm will end up with 11625 * incorrect data. 11626 */ 11627 rt2x00dev->hw->max_rates = 1; 11628 rt2x00dev->hw->max_report_rates = 7; 11629 rt2x00dev->hw->max_rate_tries = 1; 11630 11631 /* 11632 * Initialize hw_mode information. 11633 */ 11634 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 11635 11636 switch (rt2x00dev->chip.rf) { 11637 case RF2720: 11638 case RF2820: 11639 spec->num_channels = 14; 11640 spec->channels = rf_vals; 11641 break; 11642 11643 case RF2750: 11644 case RF2850: 11645 spec->num_channels = ARRAY_SIZE(rf_vals); 11646 spec->channels = rf_vals; 11647 break; 11648 11649 case RF2020: 11650 case RF3020: 11651 case RF3021: 11652 case RF3022: 11653 case RF3070: 11654 case RF3290: 11655 case RF3320: 11656 case RF3322: 11657 case RF5350: 11658 case RF5360: 11659 case RF5362: 11660 case RF5370: 11661 case RF5372: 11662 case RF5390: 11663 case RF5392: 11664 spec->num_channels = 14; 11665 if (rt2800_clk_is_20mhz(rt2x00dev)) 11666 spec->channels = rf_vals_3x_xtal20; 11667 else 11668 spec->channels = rf_vals_3x; 11669 break; 11670 11671 case RF7620: 11672 spec->num_channels = ARRAY_SIZE(rf_vals_7620); 11673 spec->channels = rf_vals_7620; 11674 break; 11675 11676 case RF3052: 11677 case RF3053: 11678 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 11679 spec->channels = rf_vals_3x; 11680 break; 11681 11682 case RF3853: 11683 spec->num_channels = ARRAY_SIZE(rf_vals_3853); 11684 spec->channels = rf_vals_3853; 11685 break; 11686 11687 case RF5592: 11688 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX); 11689 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { 11690 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); 11691 spec->channels = rf_vals_5592_xtal40; 11692 } else { 11693 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); 11694 spec->channels = rf_vals_5592_xtal20; 11695 } 11696 break; 11697 } 11698 11699 if (WARN_ON_ONCE(!spec->channels)) 11700 return -ENODEV; 11701 11702 spec->supported_bands = SUPPORT_BAND_2GHZ; 11703 if (spec->num_channels > 14) 11704 spec->supported_bands |= SUPPORT_BAND_5GHZ; 11705 11706 /* 11707 * Initialize HT information. 11708 */ 11709 if (!rt2x00_rf(rt2x00dev, RF2020)) 11710 spec->ht.ht_supported = true; 11711 else 11712 spec->ht.ht_supported = false; 11713 11714 spec->ht.cap = 11715 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 11716 IEEE80211_HT_CAP_GRN_FLD | 11717 IEEE80211_HT_CAP_SGI_20 | 11718 IEEE80211_HT_CAP_SGI_40; 11719 11720 tx_chains = rt2x00dev->default_ant.tx_chain_num; 11721 rx_chains = rt2x00dev->default_ant.rx_chain_num; 11722 11723 if (tx_chains >= 2) 11724 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; 11725 11726 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT; 11727 11728 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2; 11729 spec->ht.ampdu_density = 4; 11730 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 11731 if (tx_chains != rx_chains) { 11732 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 11733 spec->ht.mcs.tx_params |= 11734 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; 11735 } 11736 11737 switch (rx_chains) { 11738 case 3: 11739 spec->ht.mcs.rx_mask[2] = 0xff; 11740 fallthrough; 11741 case 2: 11742 spec->ht.mcs.rx_mask[1] = 0xff; 11743 fallthrough; 11744 case 1: 11745 spec->ht.mcs.rx_mask[0] = 0xff; 11746 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ 11747 break; 11748 } 11749 11750 /* 11751 * Create channel information and survey arrays 11752 */ 11753 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 11754 if (!info) 11755 return -ENOMEM; 11756 11757 rt2x00dev->chan_survey = 11758 kcalloc(spec->num_channels, sizeof(struct rt2x00_chan_survey), 11759 GFP_KERNEL); 11760 if (!rt2x00dev->chan_survey) { 11761 kfree(info); 11762 return -ENOMEM; 11763 } 11764 11765 spec->channels_info = info; 11766 11767 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 11768 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 11769 11770 if (rt2x00dev->default_ant.tx_chain_num > 2) 11771 default_power3 = rt2800_eeprom_addr(rt2x00dev, 11772 EEPROM_EXT_TXPOWER_BG3); 11773 else 11774 default_power3 = NULL; 11775 11776 for (i = 0; i < 14; i++) { 11777 info[i].default_power1 = default_power1[i]; 11778 info[i].default_power2 = default_power2[i]; 11779 if (default_power3) 11780 info[i].default_power3 = default_power3[i]; 11781 } 11782 11783 if (spec->num_channels > 14) { 11784 default_power1 = rt2800_eeprom_addr(rt2x00dev, 11785 EEPROM_TXPOWER_A1); 11786 default_power2 = rt2800_eeprom_addr(rt2x00dev, 11787 EEPROM_TXPOWER_A2); 11788 11789 if (rt2x00dev->default_ant.tx_chain_num > 2) 11790 default_power3 = 11791 rt2800_eeprom_addr(rt2x00dev, 11792 EEPROM_EXT_TXPOWER_A3); 11793 else 11794 default_power3 = NULL; 11795 11796 for (i = 14; i < spec->num_channels; i++) { 11797 info[i].default_power1 = default_power1[i - 14]; 11798 info[i].default_power2 = default_power2[i - 14]; 11799 if (default_power3) 11800 info[i].default_power3 = default_power3[i - 14]; 11801 } 11802 } 11803 11804 switch (rt2x00dev->chip.rf) { 11805 case RF2020: 11806 case RF3020: 11807 case RF3021: 11808 case RF3022: 11809 case RF3320: 11810 case RF3052: 11811 case RF3053: 11812 case RF3070: 11813 case RF3290: 11814 case RF3853: 11815 case RF5350: 11816 case RF5360: 11817 case RF5362: 11818 case RF5370: 11819 case RF5372: 11820 case RF5390: 11821 case RF5392: 11822 case RF5592: 11823 case RF7620: 11824 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); 11825 break; 11826 } 11827 11828 return 0; 11829} 11830 11831static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) 11832{ 11833 u32 reg; 11834 u32 rt; 11835 u32 rev; 11836 11837 if (rt2x00_rt(rt2x00dev, RT3290)) 11838 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290); 11839 else 11840 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 11841 11842 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); 11843 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); 11844 11845 switch (rt) { 11846 case RT2860: 11847 case RT2872: 11848 case RT2883: 11849 case RT3070: 11850 case RT3071: 11851 case RT3090: 11852 case RT3290: 11853 case RT3352: 11854 case RT3390: 11855 case RT3572: 11856 case RT3593: 11857 case RT3883: 11858 case RT5350: 11859 case RT5390: 11860 case RT5392: 11861 case RT5592: 11862 break; 11863 default: 11864 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", 11865 rt, rev); 11866 return -ENODEV; 11867 } 11868 11869 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev)) 11870 rt = RT6352; 11871 11872 rt2x00_set_rt(rt2x00dev, rt, rev); 11873 11874 return 0; 11875} 11876 11877int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) 11878{ 11879 int retval; 11880 u32 reg; 11881 11882 retval = rt2800_probe_rt(rt2x00dev); 11883 if (retval) 11884 return retval; 11885 11886 /* 11887 * Allocate eeprom data. 11888 */ 11889 retval = rt2800_validate_eeprom(rt2x00dev); 11890 if (retval) 11891 return retval; 11892 11893 retval = rt2800_init_eeprom(rt2x00dev); 11894 if (retval) 11895 return retval; 11896 11897 /* 11898 * Enable rfkill polling by setting GPIO direction of the 11899 * rfkill switch GPIO pin correctly. 11900 */ 11901 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 11902 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); 11903 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 11904 11905 /* 11906 * Initialize hw specifications. 11907 */ 11908 retval = rt2800_probe_hw_mode(rt2x00dev); 11909 if (retval) 11910 return retval; 11911 11912 /* 11913 * Set device capabilities. 11914 */ 11915 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 11916 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags); 11917 if (!rt2x00_is_usb(rt2x00dev)) 11918 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags); 11919 11920 /* 11921 * Set device requirements. 11922 */ 11923 if (!rt2x00_is_soc(rt2x00dev)) 11924 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 11925 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags); 11926 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags); 11927 if (!rt2800_hwcrypt_disabled(rt2x00dev)) 11928 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 11929 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 11930 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags); 11931 if (rt2x00_is_usb(rt2x00dev)) 11932 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); 11933 else { 11934 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 11935 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags); 11936 } 11937 11938 if (modparam_watchdog) { 11939 __set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags); 11940 rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100); 11941 } else { 11942 rt2x00dev->link.watchdog_disabled = true; 11943 } 11944 11945 /* 11946 * Set the rssi offset. 11947 */ 11948 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 11949 11950 return 0; 11951} 11952EXPORT_SYMBOL_GPL(rt2800_probe_hw); 11953 11954/* 11955 * IEEE80211 stack callback functions. 11956 */ 11957void rt2800_get_key_seq(struct ieee80211_hw *hw, 11958 struct ieee80211_key_conf *key, 11959 struct ieee80211_key_seq *seq) 11960{ 11961 struct rt2x00_dev *rt2x00dev = hw->priv; 11962 struct mac_iveiv_entry iveiv_entry; 11963 u32 offset; 11964 11965 if (key->cipher != WLAN_CIPHER_SUITE_TKIP) 11966 return; 11967 11968 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 11969 rt2800_register_multiread(rt2x00dev, offset, 11970 &iveiv_entry, sizeof(iveiv_entry)); 11971 11972 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2); 11973 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4); 11974} 11975EXPORT_SYMBOL_GPL(rt2800_get_key_seq); 11976 11977int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 11978{ 11979 struct rt2x00_dev *rt2x00dev = hw->priv; 11980 u32 reg; 11981 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 11982 11983 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 11984 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); 11985 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 11986 11987 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 11988 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); 11989 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 11990 11991 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 11992 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); 11993 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 11994 11995 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 11996 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); 11997 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 11998 11999 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 12000 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); 12001 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 12002 12003 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 12004 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); 12005 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 12006 12007 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 12008 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); 12009 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 12010 12011 return 0; 12012} 12013EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); 12014 12015int rt2800_conf_tx(struct ieee80211_hw *hw, 12016 struct ieee80211_vif *vif, 12017 unsigned int link_id, u16 queue_idx, 12018 const struct ieee80211_tx_queue_params *params) 12019{ 12020 struct rt2x00_dev *rt2x00dev = hw->priv; 12021 struct data_queue *queue; 12022 struct rt2x00_field32 field; 12023 int retval; 12024 u32 reg; 12025 u32 offset; 12026 12027 /* 12028 * First pass the configuration through rt2x00lib, that will 12029 * update the queue settings and validate the input. After that 12030 * we are free to update the registers based on the value 12031 * in the queue parameter. 12032 */ 12033 retval = rt2x00mac_conf_tx(hw, vif, link_id, queue_idx, params); 12034 if (retval) 12035 return retval; 12036 12037 /* 12038 * We only need to perform additional register initialization 12039 * for WMM queues/ 12040 */ 12041 if (queue_idx >= 4) 12042 return 0; 12043 12044 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 12045 12046 /* Update WMM TXOP register */ 12047 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 12048 field.bit_offset = (queue_idx & 1) * 16; 12049 field.bit_mask = 0xffff << field.bit_offset; 12050 12051 reg = rt2800_register_read(rt2x00dev, offset); 12052 rt2x00_set_field32(®, field, queue->txop); 12053 rt2800_register_write(rt2x00dev, offset, reg); 12054 12055 /* Update WMM registers */ 12056 field.bit_offset = queue_idx * 4; 12057 field.bit_mask = 0xf << field.bit_offset; 12058 12059 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG); 12060 rt2x00_set_field32(®, field, queue->aifs); 12061 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 12062 12063 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG); 12064 rt2x00_set_field32(®, field, queue->cw_min); 12065 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 12066 12067 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG); 12068 rt2x00_set_field32(®, field, queue->cw_max); 12069 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 12070 12071 /* Update EDCA registers */ 12072 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 12073 12074 reg = rt2800_register_read(rt2x00dev, offset); 12075 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); 12076 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); 12077 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); 12078 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); 12079 rt2800_register_write(rt2x00dev, offset, reg); 12080 12081 return 0; 12082} 12083EXPORT_SYMBOL_GPL(rt2800_conf_tx); 12084 12085u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 12086{ 12087 struct rt2x00_dev *rt2x00dev = hw->priv; 12088 u64 tsf; 12089 u32 reg; 12090 12091 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1); 12092 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 12093 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0); 12094 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 12095 12096 return tsf; 12097} 12098EXPORT_SYMBOL_GPL(rt2800_get_tsf); 12099 12100int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 12101 struct ieee80211_ampdu_params *params) 12102{ 12103 struct ieee80211_sta *sta = params->sta; 12104 enum ieee80211_ampdu_mlme_action action = params->action; 12105 u16 tid = params->tid; 12106 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; 12107 int ret = 0; 12108 12109 /* 12110 * Don't allow aggregation for stations the hardware isn't aware 12111 * of because tx status reports for frames to an unknown station 12112 * always contain wcid=WCID_END+1 and thus we can't distinguish 12113 * between multiple stations which leads to unwanted situations 12114 * when the hw reorders frames due to aggregation. 12115 */ 12116 if (sta_priv->wcid > WCID_END) 12117 return -ENOSPC; 12118 12119 switch (action) { 12120 case IEEE80211_AMPDU_RX_START: 12121 case IEEE80211_AMPDU_RX_STOP: 12122 /* 12123 * The hw itself takes care of setting up BlockAck mechanisms. 12124 * So, we only have to allow mac80211 to nagotiate a BlockAck 12125 * agreement. Once that is done, the hw will BlockAck incoming 12126 * AMPDUs without further setup. 12127 */ 12128 break; 12129 case IEEE80211_AMPDU_TX_START: 12130 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 12131 break; 12132 case IEEE80211_AMPDU_TX_STOP_CONT: 12133 case IEEE80211_AMPDU_TX_STOP_FLUSH: 12134 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 12135 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 12136 break; 12137 case IEEE80211_AMPDU_TX_OPERATIONAL: 12138 break; 12139 default: 12140 rt2x00_warn((struct rt2x00_dev *)hw->priv, 12141 "Unknown AMPDU action\n"); 12142 } 12143 12144 return ret; 12145} 12146EXPORT_SYMBOL_GPL(rt2800_ampdu_action); 12147 12148int rt2800_get_survey(struct ieee80211_hw *hw, int idx, 12149 struct survey_info *survey) 12150{ 12151 struct rt2x00_dev *rt2x00dev = hw->priv; 12152 struct rt2x00_chan_survey *chan_survey = 12153 &rt2x00dev->chan_survey[idx]; 12154 enum nl80211_band band = NL80211_BAND_2GHZ; 12155 12156 if (idx >= rt2x00dev->bands[band].n_channels) { 12157 idx -= rt2x00dev->bands[band].n_channels; 12158 band = NL80211_BAND_5GHZ; 12159 } 12160 12161 if (idx >= rt2x00dev->bands[band].n_channels) 12162 return -ENOENT; 12163 12164 if (idx == 0) 12165 rt2800_update_survey(rt2x00dev); 12166 12167 survey->channel = &rt2x00dev->bands[band].channels[idx]; 12168 12169 survey->filled = SURVEY_INFO_TIME | 12170 SURVEY_INFO_TIME_BUSY | 12171 SURVEY_INFO_TIME_EXT_BUSY; 12172 12173 survey->time = div_u64(chan_survey->time_idle + chan_survey->time_busy, 1000); 12174 survey->time_busy = div_u64(chan_survey->time_busy, 1000); 12175 survey->time_ext_busy = div_u64(chan_survey->time_ext_busy, 1000); 12176 12177 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 12178 survey->filled |= SURVEY_INFO_IN_USE; 12179 12180 return 0; 12181 12182} 12183EXPORT_SYMBOL_GPL(rt2800_get_survey); 12184 12185MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); 12186MODULE_VERSION(DRV_VERSION); 12187MODULE_DESCRIPTION("Ralink RT2800 library"); 12188MODULE_LICENSE("GPL"); 12189