1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#ifndef __MT7921_REGS_H
5#define __MT7921_REGS_H
6
7#include "../mt792x_regs.h"
8
9#define MT_MDP_BASE			0x820cd000
10#define MT_MDP(ofs)			(MT_MDP_BASE + (ofs))
11
12#define MT_MDP_DCR0			MT_MDP(0x000)
13#define MT_MDP_DCR0_DAMSDU_EN		BIT(15)
14#define MT_MDP_DCR0_RX_HDR_TRANS_EN	BIT(19)
15
16#define MT_MDP_DCR1			MT_MDP(0x004)
17#define MT_MDP_DCR1_MAX_RX_LEN		GENMASK(15, 3)
18
19#define MT_MDP_BNRCFR0(_band)		MT_MDP(0x070 + ((_band) << 8))
20#define MT_MDP_RCFR0_MCU_RX_MGMT	GENMASK(5, 4)
21#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR	GENMASK(7, 6)
22#define MT_MDP_RCFR0_MCU_RX_CTL_BAR	GENMASK(9, 8)
23
24#define MT_MDP_BNRCFR1(_band)		MT_MDP(0x074 + ((_band) << 8))
25#define MT_MDP_RCFR1_MCU_RX_BYPASS	GENMASK(23, 22)
26#define MT_MDP_RCFR1_RX_DROPPED_UCAST	GENMASK(28, 27)
27#define MT_MDP_RCFR1_RX_DROPPED_MCAST	GENMASK(30, 29)
28#define MT_MDP_TO_HIF			0
29#define MT_MDP_TO_WM			1
30
31#define MT_WFDMA0_HOST_INT_ENA		MT_WFDMA0(0x204)
32#define HOST_TX_DONE_INT_ENA8		BIT(12)
33#define HOST_TX_DONE_INT_ENA9		BIT(13)
34#define HOST_TX_DONE_INT_ENA10		BIT(14)
35#define HOST_TX_DONE_INT_ENA11		BIT(15)
36#define HOST_TX_DONE_INT_ENA12		BIT(16)
37#define HOST_TX_DONE_INT_ENA13		BIT(17)
38#define HOST_TX_DONE_INT_ENA14		BIT(18)
39#define HOST_RX_DONE_INT_ENA4		BIT(22)
40#define HOST_RX_DONE_INT_ENA5		BIT(23)
41#define HOST_TX_DONE_INT_ENA16		BIT(26)
42#define HOST_TX_DONE_INT_ENA17		BIT(27)
43
44/* WFDMA interrupt */
45#define MT_INT_RX_DONE_DATA		HOST_RX_DONE_INT_ENA2
46#define MT_INT_RX_DONE_WM		HOST_RX_DONE_INT_ENA0
47#define MT_INT_RX_DONE_WM2		HOST_RX_DONE_INT_ENA4
48#define MT_INT_RX_DONE_ALL		(MT_INT_RX_DONE_DATA | \
49					 MT_INT_RX_DONE_WM | \
50					 MT_INT_RX_DONE_WM2)
51#define MT_INT_TX_DONE_MCU_WM		HOST_TX_DONE_INT_ENA17
52#define MT_INT_TX_DONE_FWDL		HOST_TX_DONE_INT_ENA16
53#define MT_INT_TX_DONE_BAND0		HOST_TX_DONE_INT_ENA0
54
55#define MT_INT_TX_DONE_MCU		(MT_INT_TX_DONE_MCU_WM |	\
56					 MT_INT_TX_DONE_FWDL)
57#define MT_INT_TX_DONE_ALL		(MT_INT_TX_DONE_MCU_WM |	\
58					 MT_INT_TX_DONE_BAND0 |	\
59					GENMASK(18, 4))
60
61#define MT_RX_DATA_RING_BASE		MT_WFDMA0(0x520)
62
63#define MT_INFRA_CFG_BASE		0xfe000
64#define MT_INFRA(ofs)			(MT_INFRA_CFG_BASE + (ofs))
65
66#define MT_HIF_REMAP_L1			MT_INFRA(0x24c)
67#define MT_HIF_REMAP_L1_MASK		GENMASK(15, 0)
68#define MT_HIF_REMAP_L1_OFFSET		GENMASK(15, 0)
69#define MT_HIF_REMAP_L1_BASE		GENMASK(31, 16)
70#define MT_HIF_REMAP_BASE_L1		0x40000
71
72#define MT_WFSYS_SW_RST_B		0x18000140
73
74#define MT_WTBLON_TOP_WDUCR		MT_WTBLON_TOP(0x200)
75#define MT_WTBLON_TOP_WDUCR_GROUP	GENMASK(2, 0)
76
77#define MT_WTBL_UPDATE			MT_WTBLON_TOP(0x230)
78#define MT_WTBL_UPDATE_WLAN_IDX		GENMASK(9, 0)
79#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR	BIT(12)
80
81#endif
82