1// SPDX-License-Identifier: ISC 2/* Copyright (C) 2020 MediaTek Inc. */ 3 4#include "mt7915.h" 5#include "mac.h" 6#include "mcu.h" 7#include "testmode.h" 8 9enum { 10 TM_CHANGED_TXPOWER, 11 TM_CHANGED_FREQ_OFFSET, 12 13 /* must be last */ 14 NUM_TM_CHANGED 15}; 16 17static const u8 tm_change_map[] = { 18 [TM_CHANGED_TXPOWER] = MT76_TM_ATTR_TX_POWER, 19 [TM_CHANGED_FREQ_OFFSET] = MT76_TM_ATTR_FREQ_OFFSET, 20}; 21 22struct reg_band { 23 u32 band[2]; 24}; 25 26#define REG_BAND(_list, _reg) \ 27 { _list.band[0] = MT_##_reg(0); \ 28 _list.band[1] = MT_##_reg(1); } 29#define REG_BAND_IDX(_list, _reg, _idx) \ 30 { _list.band[0] = MT_##_reg(0, _idx); \ 31 _list.band[1] = MT_##_reg(1, _idx); } 32 33#define TM_REG_MAX_ID 17 34static struct reg_band reg_backup_list[TM_REG_MAX_ID]; 35 36 37static int 38mt7915_tm_set_tx_power(struct mt7915_phy *phy) 39{ 40 struct mt7915_dev *dev = phy->dev; 41 struct mt76_phy *mphy = phy->mt76; 42 struct cfg80211_chan_def *chandef = &mphy->chandef; 43 int freq = chandef->center_freq1; 44 int ret; 45 struct { 46 u8 format_id; 47 u8 band_idx; 48 s8 tx_power; 49 u8 ant_idx; /* Only 0 is valid */ 50 u8 center_chan; 51 u8 rsv[3]; 52 } __packed req = { 53 .format_id = 0xf, 54 .band_idx = phy->mt76->band_idx, 55 .center_chan = ieee80211_frequency_to_channel(freq), 56 }; 57 u8 *tx_power = NULL; 58 59 if (phy->mt76->test.state != MT76_TM_STATE_OFF) 60 tx_power = phy->mt76->test.tx_power; 61 62 /* Tx power of the other antennas are the same as antenna 0 */ 63 if (tx_power && tx_power[0]) 64 req.tx_power = tx_power[0]; 65 66 ret = mt76_mcu_send_msg(&dev->mt76, 67 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), 68 &req, sizeof(req), false); 69 70 return ret; 71} 72 73static int 74mt7915_tm_set_freq_offset(struct mt7915_phy *phy, bool en, u32 val) 75{ 76 struct mt7915_dev *dev = phy->dev; 77 struct mt7915_tm_cmd req = { 78 .testmode_en = en, 79 .param_idx = MCU_ATE_SET_FREQ_OFFSET, 80 .param.freq.band = phy->mt76->band_idx, 81 .param.freq.freq_offset = cpu_to_le32(val), 82 }; 83 84 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req, 85 sizeof(req), false); 86} 87 88static int 89mt7915_tm_mode_ctrl(struct mt7915_dev *dev, bool enable) 90{ 91 struct { 92 u8 format_id; 93 bool enable; 94 u8 rsv[2]; 95 } __packed req = { 96 .format_id = 0x6, 97 .enable = enable, 98 }; 99 100 return mt76_mcu_send_msg(&dev->mt76, 101 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), 102 &req, sizeof(req), false); 103} 104 105static int 106mt7915_tm_set_trx(struct mt7915_phy *phy, int type, bool en) 107{ 108 struct mt7915_dev *dev = phy->dev; 109 struct mt7915_tm_cmd req = { 110 .testmode_en = 1, 111 .param_idx = MCU_ATE_SET_TRX, 112 .param.trx.type = type, 113 .param.trx.enable = en, 114 .param.trx.band = phy->mt76->band_idx, 115 }; 116 117 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req, 118 sizeof(req), false); 119} 120 121static int 122mt7915_tm_clean_hwq(struct mt7915_phy *phy, u8 wcid) 123{ 124 struct mt7915_dev *dev = phy->dev; 125 struct mt7915_tm_cmd req = { 126 .testmode_en = 1, 127 .param_idx = MCU_ATE_CLEAN_TXQUEUE, 128 .param.clean.wcid = wcid, 129 .param.clean.band = phy->mt76->band_idx, 130 }; 131 132 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req, 133 sizeof(req), false); 134} 135 136static int 137mt7915_tm_set_slot_time(struct mt7915_phy *phy, u8 slot_time, u8 sifs) 138{ 139 struct mt7915_dev *dev = phy->dev; 140 struct mt7915_tm_cmd req = { 141 .testmode_en = !(phy->mt76->test.state == MT76_TM_STATE_OFF), 142 .param_idx = MCU_ATE_SET_SLOT_TIME, 143 .param.slot.slot_time = slot_time, 144 .param.slot.sifs = sifs, 145 .param.slot.rifs = 2, 146 .param.slot.eifs = cpu_to_le16(60), 147 .param.slot.band = phy->mt76->band_idx, 148 }; 149 150 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req, 151 sizeof(req), false); 152} 153 154static int 155mt7915_tm_set_tam_arb(struct mt7915_phy *phy, bool enable, bool mu) 156{ 157 struct mt7915_dev *dev = phy->dev; 158 u32 op_mode; 159 160 if (!enable) 161 op_mode = TAM_ARB_OP_MODE_NORMAL; 162 else if (mu) 163 op_mode = TAM_ARB_OP_MODE_TEST; 164 else 165 op_mode = TAM_ARB_OP_MODE_FORCE_SU; 166 167 return mt7915_mcu_set_muru_ctrl(dev, MURU_SET_ARB_OP_MODE, op_mode); 168} 169 170static int 171mt7915_tm_set_wmm_qid(struct mt7915_phy *phy, u8 qid, u8 aifs, u8 cw_min, 172 u16 cw_max, u16 txop) 173{ 174 struct mt7915_vif *mvif = (struct mt7915_vif *)phy->monitor_vif->drv_priv; 175 struct mt7915_mcu_tx req = { .total = 1 }; 176 struct edca *e = &req.edca[0]; 177 178 e->queue = qid + mvif->mt76.wmm_idx * MT76_CONNAC_MAX_WMM_SETS; 179 e->set = WMM_PARAM_SET; 180 181 e->aifs = aifs; 182 e->cw_min = cw_min; 183 e->cw_max = cpu_to_le16(cw_max); 184 e->txop = cpu_to_le16(txop); 185 186 return mt7915_mcu_update_edca(phy->dev, &req); 187} 188 189static int 190mt7915_tm_set_ipg_params(struct mt7915_phy *phy, u32 ipg, u8 mode) 191{ 192#define TM_DEFAULT_SIFS 10 193#define TM_MAX_SIFS 127 194#define TM_MAX_AIFSN 0xf 195#define TM_MIN_AIFSN 0x1 196#define BBP_PROC_TIME 1500 197 struct mt7915_dev *dev = phy->dev; 198 u8 sig_ext = (mode == MT76_TM_TX_MODE_CCK) ? 0 : 6; 199 u8 slot_time = 9, sifs = TM_DEFAULT_SIFS; 200 u8 aifsn = TM_MIN_AIFSN; 201 u8 band = phy->mt76->band_idx; 202 u32 i2t_time, tr2t_time, txv_time; 203 u16 cw = 0; 204 205 if (ipg < sig_ext + slot_time + sifs) 206 ipg = 0; 207 208 if (!ipg) 209 goto done; 210 211 ipg -= sig_ext; 212 213 if (ipg <= (TM_MAX_SIFS + slot_time)) { 214 sifs = ipg - slot_time; 215 } else { 216 u32 val = (ipg + slot_time) / slot_time; 217 218 while (val >>= 1) 219 cw++; 220 221 if (cw > 16) 222 cw = 16; 223 224 ipg -= ((1 << cw) - 1) * slot_time; 225 226 aifsn = ipg / slot_time; 227 if (aifsn > TM_MAX_AIFSN) 228 aifsn = TM_MAX_AIFSN; 229 230 ipg -= aifsn * slot_time; 231 232 if (ipg > TM_DEFAULT_SIFS) 233 sifs = min_t(u32, ipg, TM_MAX_SIFS); 234 } 235done: 236 txv_time = mt76_get_field(dev, MT_TMAC_ATCR(band), 237 MT_TMAC_ATCR_TXV_TOUT); 238 txv_time *= 50; /* normal clock time */ 239 240 i2t_time = (slot_time * 1000 - txv_time - BBP_PROC_TIME) / 50; 241 tr2t_time = (sifs * 1000 - txv_time - BBP_PROC_TIME) / 50; 242 243 mt76_set(dev, MT_TMAC_TRCR0(band), 244 FIELD_PREP(MT_TMAC_TRCR0_TR2T_CHK, tr2t_time) | 245 FIELD_PREP(MT_TMAC_TRCR0_I2T_CHK, i2t_time)); 246 247 mt7915_tm_set_slot_time(phy, slot_time, sifs); 248 249 return mt7915_tm_set_wmm_qid(phy, 250 mt76_connac_lmac_mapping(IEEE80211_AC_BE), 251 aifsn, cw, cw, 0); 252} 253 254static int 255mt7915_tm_set_tx_len(struct mt7915_phy *phy, u32 tx_time) 256{ 257 struct mt76_phy *mphy = phy->mt76; 258 struct mt76_testmode_data *td = &mphy->test; 259 struct ieee80211_supported_band *sband; 260 struct rate_info rate = {}; 261 u16 flags = 0, tx_len; 262 u32 bitrate; 263 int ret; 264 265 if (!tx_time) 266 return 0; 267 268 rate.mcs = td->tx_rate_idx; 269 rate.nss = td->tx_rate_nss; 270 271 switch (td->tx_rate_mode) { 272 case MT76_TM_TX_MODE_CCK: 273 case MT76_TM_TX_MODE_OFDM: 274 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 275 sband = &mphy->sband_5g.sband; 276 else if (mphy->chandef.chan->band == NL80211_BAND_6GHZ) 277 sband = &mphy->sband_6g.sband; 278 else 279 sband = &mphy->sband_2g.sband; 280 281 rate.legacy = sband->bitrates[rate.mcs].bitrate; 282 break; 283 case MT76_TM_TX_MODE_HT: 284 rate.mcs += rate.nss * 8; 285 flags |= RATE_INFO_FLAGS_MCS; 286 287 if (td->tx_rate_sgi) 288 flags |= RATE_INFO_FLAGS_SHORT_GI; 289 break; 290 case MT76_TM_TX_MODE_VHT: 291 flags |= RATE_INFO_FLAGS_VHT_MCS; 292 293 if (td->tx_rate_sgi) 294 flags |= RATE_INFO_FLAGS_SHORT_GI; 295 break; 296 case MT76_TM_TX_MODE_HE_SU: 297 case MT76_TM_TX_MODE_HE_EXT_SU: 298 case MT76_TM_TX_MODE_HE_TB: 299 case MT76_TM_TX_MODE_HE_MU: 300 rate.he_gi = td->tx_rate_sgi; 301 flags |= RATE_INFO_FLAGS_HE_MCS; 302 break; 303 default: 304 break; 305 } 306 rate.flags = flags; 307 308 switch (mphy->chandef.width) { 309 case NL80211_CHAN_WIDTH_160: 310 case NL80211_CHAN_WIDTH_80P80: 311 rate.bw = RATE_INFO_BW_160; 312 break; 313 case NL80211_CHAN_WIDTH_80: 314 rate.bw = RATE_INFO_BW_80; 315 break; 316 case NL80211_CHAN_WIDTH_40: 317 rate.bw = RATE_INFO_BW_40; 318 break; 319 default: 320 rate.bw = RATE_INFO_BW_20; 321 break; 322 } 323 324 bitrate = cfg80211_calculate_bitrate(&rate); 325 tx_len = bitrate * tx_time / 10 / 8; 326 327 ret = mt76_testmode_alloc_skb(phy->mt76, tx_len); 328 if (ret) 329 return ret; 330 331 return 0; 332} 333 334static void 335mt7915_tm_reg_backup_restore(struct mt7915_phy *phy) 336{ 337 int n_regs = ARRAY_SIZE(reg_backup_list); 338 struct mt7915_dev *dev = phy->dev; 339 u32 *b = phy->test.reg_backup; 340 u8 band = phy->mt76->band_idx; 341 int i; 342 343 REG_BAND_IDX(reg_backup_list[0], AGG_PCR0, 0); 344 REG_BAND_IDX(reg_backup_list[1], AGG_PCR0, 1); 345 REG_BAND_IDX(reg_backup_list[2], AGG_AWSCR0, 0); 346 REG_BAND_IDX(reg_backup_list[3], AGG_AWSCR0, 1); 347 REG_BAND_IDX(reg_backup_list[4], AGG_AWSCR0, 2); 348 REG_BAND_IDX(reg_backup_list[5], AGG_AWSCR0, 3); 349 REG_BAND(reg_backup_list[6], AGG_MRCR); 350 REG_BAND(reg_backup_list[7], TMAC_TFCR0); 351 REG_BAND(reg_backup_list[8], TMAC_TCR0); 352 REG_BAND(reg_backup_list[9], AGG_ATCR1); 353 REG_BAND(reg_backup_list[10], AGG_ATCR3); 354 REG_BAND(reg_backup_list[11], TMAC_TRCR0); 355 REG_BAND(reg_backup_list[12], TMAC_ICR0); 356 REG_BAND_IDX(reg_backup_list[13], ARB_DRNGR0, 0); 357 REG_BAND_IDX(reg_backup_list[14], ARB_DRNGR0, 1); 358 REG_BAND(reg_backup_list[15], WF_RFCR); 359 REG_BAND(reg_backup_list[16], WF_RFCR1); 360 361 if (phy->mt76->test.state == MT76_TM_STATE_OFF) { 362 for (i = 0; i < n_regs; i++) 363 mt76_wr(dev, reg_backup_list[i].band[band], b[i]); 364 return; 365 } 366 367 if (!b) { 368 b = devm_kzalloc(dev->mt76.dev, 4 * n_regs, GFP_KERNEL); 369 if (!b) 370 return; 371 372 phy->test.reg_backup = b; 373 for (i = 0; i < n_regs; i++) 374 b[i] = mt76_rr(dev, reg_backup_list[i].band[band]); 375 } 376 377 mt76_clear(dev, MT_AGG_PCR0(band, 0), MT_AGG_PCR0_MM_PROT | 378 MT_AGG_PCR0_GF_PROT | MT_AGG_PCR0_ERP_PROT | 379 MT_AGG_PCR0_VHT_PROT | MT_AGG_PCR0_BW20_PROT | 380 MT_AGG_PCR0_BW40_PROT | MT_AGG_PCR0_BW80_PROT); 381 mt76_set(dev, MT_AGG_PCR0(band, 0), MT_AGG_PCR0_PTA_WIN_DIS); 382 383 mt76_wr(dev, MT_AGG_PCR0(band, 1), MT_AGG_PCR1_RTS0_NUM_THRES | 384 MT_AGG_PCR1_RTS0_LEN_THRES); 385 386 mt76_clear(dev, MT_AGG_MRCR(band), MT_AGG_MRCR_BAR_CNT_LIMIT | 387 MT_AGG_MRCR_LAST_RTS_CTS_RN | MT_AGG_MRCR_RTS_FAIL_LIMIT | 388 MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT); 389 390 mt76_rmw(dev, MT_AGG_MRCR(band), MT_AGG_MRCR_RTS_FAIL_LIMIT | 391 MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT, 392 FIELD_PREP(MT_AGG_MRCR_RTS_FAIL_LIMIT, 1) | 393 FIELD_PREP(MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT, 1)); 394 395 mt76_wr(dev, MT_TMAC_TFCR0(band), 0); 396 mt76_clear(dev, MT_TMAC_TCR0(band), MT_TMAC_TCR0_TBTT_STOP_CTRL); 397 398 /* config rx filter for testmode rx */ 399 mt76_wr(dev, MT_WF_RFCR(band), 0xcf70a); 400 mt76_wr(dev, MT_WF_RFCR1(band), 0); 401} 402 403static void 404mt7915_tm_init(struct mt7915_phy *phy, bool en) 405{ 406 struct mt7915_dev *dev = phy->dev; 407 408 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 409 return; 410 411 mt7915_mcu_set_sku_en(phy, !en); 412 413 mt7915_tm_mode_ctrl(dev, en); 414 mt7915_tm_reg_backup_restore(phy); 415 mt7915_tm_set_trx(phy, TM_MAC_TXRX, !en); 416 417 mt7915_mcu_add_bss_info(phy, phy->monitor_vif, en); 418 mt7915_mcu_add_sta(dev, phy->monitor_vif, NULL, en); 419 420 if (!en) 421 mt7915_tm_set_tam_arb(phy, en, 0); 422} 423 424static void 425mt7915_tm_update_channel(struct mt7915_phy *phy) 426{ 427 mutex_unlock(&phy->dev->mt76.mutex); 428 mt7915_set_channel(phy); 429 mutex_lock(&phy->dev->mt76.mutex); 430 431 mt7915_mcu_set_chan_info(phy, MCU_EXT_CMD(SET_RX_PATH)); 432} 433 434static void 435mt7915_tm_set_tx_frames(struct mt7915_phy *phy, bool en) 436{ 437 struct mt76_testmode_data *td = &phy->mt76->test; 438 struct mt7915_dev *dev = phy->dev; 439 struct ieee80211_tx_info *info; 440 u8 duty_cycle = td->tx_duty_cycle; 441 u32 tx_time = td->tx_time; 442 u32 ipg = td->tx_ipg; 443 444 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false); 445 mt7915_tm_clean_hwq(phy, dev->mt76.global_wcid.idx); 446 447 if (en) { 448 mt7915_tm_update_channel(phy); 449 450 if (td->tx_spe_idx) 451 phy->test.spe_idx = td->tx_spe_idx; 452 else 453 phy->test.spe_idx = mt76_connac_spe_idx(td->tx_antenna_mask); 454 } 455 456 mt7915_tm_set_tam_arb(phy, en, 457 td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU); 458 459 /* if all three params are set, duty_cycle will be ignored */ 460 if (duty_cycle && tx_time && !ipg) { 461 ipg = tx_time * 100 / duty_cycle - tx_time; 462 } else if (duty_cycle && !tx_time && ipg) { 463 if (duty_cycle < 100) 464 tx_time = duty_cycle * ipg / (100 - duty_cycle); 465 } 466 467 mt7915_tm_set_ipg_params(phy, ipg, td->tx_rate_mode); 468 mt7915_tm_set_tx_len(phy, tx_time); 469 470 if (ipg) 471 td->tx_queued_limit = MT76_TM_TIMEOUT * 1000000 / ipg / 2; 472 473 if (!en || !td->tx_skb) 474 return; 475 476 info = IEEE80211_SKB_CB(td->tx_skb); 477 info->control.vif = phy->monitor_vif; 478 479 mt7915_tm_set_trx(phy, TM_MAC_TX, en); 480} 481 482static void 483mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en) 484{ 485 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false); 486 487 if (en) { 488 struct mt7915_dev *dev = phy->dev; 489 490 mt7915_tm_update_channel(phy); 491 492 /* read-clear */ 493 mt76_rr(dev, MT_MIB_SDR3(phy->mt76->band_idx)); 494 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en); 495 } 496} 497 498static int 499mt7915_tm_rf_switch_mode(struct mt7915_dev *dev, u32 oper) 500{ 501 struct mt7915_tm_rf_test req = { 502 .op.op_mode = cpu_to_le32(oper), 503 }; 504 505 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req, 506 sizeof(req), true); 507} 508 509static int 510mt7915_tm_set_tx_cont(struct mt7915_phy *phy, bool en) 511{ 512#define TX_CONT_START 0x05 513#define TX_CONT_STOP 0x06 514 struct mt7915_dev *dev = phy->dev; 515 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 516 int freq1 = ieee80211_frequency_to_channel(chandef->center_freq1); 517 struct mt76_testmode_data *td = &phy->mt76->test; 518 u32 func_idx = en ? TX_CONT_START : TX_CONT_STOP; 519 u8 rate_idx = td->tx_rate_idx, mode; 520 u8 band = phy->mt76->band_idx; 521 u16 rateval; 522 struct mt7915_tm_rf_test req = { 523 .action = 1, 524 .icap_len = 120, 525 .op.rf.func_idx = cpu_to_le32(func_idx), 526 }; 527 struct tm_tx_cont *tx_cont = &req.op.rf.param.tx_cont; 528 529 tx_cont->control_ch = chandef->chan->hw_value; 530 tx_cont->center_ch = freq1; 531 tx_cont->tx_ant = td->tx_antenna_mask; 532 tx_cont->band = band; 533 534 switch (chandef->width) { 535 case NL80211_CHAN_WIDTH_40: 536 tx_cont->bw = CMD_CBW_40MHZ; 537 break; 538 case NL80211_CHAN_WIDTH_80: 539 tx_cont->bw = CMD_CBW_80MHZ; 540 break; 541 case NL80211_CHAN_WIDTH_80P80: 542 tx_cont->bw = CMD_CBW_8080MHZ; 543 break; 544 case NL80211_CHAN_WIDTH_160: 545 tx_cont->bw = CMD_CBW_160MHZ; 546 break; 547 case NL80211_CHAN_WIDTH_5: 548 tx_cont->bw = CMD_CBW_5MHZ; 549 break; 550 case NL80211_CHAN_WIDTH_10: 551 tx_cont->bw = CMD_CBW_10MHZ; 552 break; 553 case NL80211_CHAN_WIDTH_20: 554 tx_cont->bw = CMD_CBW_20MHZ; 555 break; 556 case NL80211_CHAN_WIDTH_20_NOHT: 557 tx_cont->bw = CMD_CBW_20MHZ; 558 break; 559 default: 560 return -EINVAL; 561 } 562 563 if (!en) { 564 req.op.rf.param.func_data = cpu_to_le32(band); 565 goto out; 566 } 567 568 if (td->tx_rate_mode <= MT76_TM_TX_MODE_OFDM) { 569 struct ieee80211_supported_band *sband; 570 u8 idx = rate_idx; 571 572 if (chandef->chan->band == NL80211_BAND_5GHZ) 573 sband = &phy->mt76->sband_5g.sband; 574 else if (chandef->chan->band == NL80211_BAND_6GHZ) 575 sband = &phy->mt76->sband_6g.sband; 576 else 577 sband = &phy->mt76->sband_2g.sband; 578 579 if (td->tx_rate_mode == MT76_TM_TX_MODE_OFDM) 580 idx += 4; 581 rate_idx = sband->bitrates[idx].hw_value & 0xff; 582 } 583 584 switch (td->tx_rate_mode) { 585 case MT76_TM_TX_MODE_CCK: 586 mode = MT_PHY_TYPE_CCK; 587 break; 588 case MT76_TM_TX_MODE_OFDM: 589 mode = MT_PHY_TYPE_OFDM; 590 break; 591 case MT76_TM_TX_MODE_HT: 592 mode = MT_PHY_TYPE_HT; 593 break; 594 case MT76_TM_TX_MODE_VHT: 595 mode = MT_PHY_TYPE_VHT; 596 break; 597 case MT76_TM_TX_MODE_HE_SU: 598 mode = MT_PHY_TYPE_HE_SU; 599 break; 600 case MT76_TM_TX_MODE_HE_EXT_SU: 601 mode = MT_PHY_TYPE_HE_EXT_SU; 602 break; 603 case MT76_TM_TX_MODE_HE_TB: 604 mode = MT_PHY_TYPE_HE_TB; 605 break; 606 case MT76_TM_TX_MODE_HE_MU: 607 mode = MT_PHY_TYPE_HE_MU; 608 break; 609 default: 610 return -EINVAL; 611 } 612 613 rateval = mode << 6 | rate_idx; 614 tx_cont->rateval = cpu_to_le16(rateval); 615 616out: 617 if (!en) { 618 int ret; 619 620 ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req, 621 sizeof(req), true); 622 if (ret) 623 return ret; 624 625 return mt7915_tm_rf_switch_mode(dev, RF_OPER_NORMAL); 626 } 627 628 mt7915_tm_rf_switch_mode(dev, RF_OPER_RF_TEST); 629 mt7915_tm_update_channel(phy); 630 631 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req, 632 sizeof(req), true); 633} 634 635static void 636mt7915_tm_update_params(struct mt7915_phy *phy, u32 changed) 637{ 638 struct mt76_testmode_data *td = &phy->mt76->test; 639 bool en = phy->mt76->test.state != MT76_TM_STATE_OFF; 640 641 if (changed & BIT(TM_CHANGED_FREQ_OFFSET)) 642 mt7915_tm_set_freq_offset(phy, en, en ? td->freq_offset : 0); 643 if (changed & BIT(TM_CHANGED_TXPOWER)) 644 mt7915_tm_set_tx_power(phy); 645} 646 647static int 648mt7915_tm_set_state(struct mt76_phy *mphy, enum mt76_testmode_state state) 649{ 650 struct mt76_testmode_data *td = &mphy->test; 651 struct mt7915_phy *phy = mphy->priv; 652 enum mt76_testmode_state prev_state = td->state; 653 654 mphy->test.state = state; 655 656 if (prev_state == MT76_TM_STATE_TX_FRAMES || 657 state == MT76_TM_STATE_TX_FRAMES) 658 mt7915_tm_set_tx_frames(phy, state == MT76_TM_STATE_TX_FRAMES); 659 else if (prev_state == MT76_TM_STATE_RX_FRAMES || 660 state == MT76_TM_STATE_RX_FRAMES) 661 mt7915_tm_set_rx_frames(phy, state == MT76_TM_STATE_RX_FRAMES); 662 else if (prev_state == MT76_TM_STATE_TX_CONT || 663 state == MT76_TM_STATE_TX_CONT) 664 mt7915_tm_set_tx_cont(phy, state == MT76_TM_STATE_TX_CONT); 665 else if (prev_state == MT76_TM_STATE_OFF || 666 state == MT76_TM_STATE_OFF) 667 mt7915_tm_init(phy, !(state == MT76_TM_STATE_OFF)); 668 669 if ((state == MT76_TM_STATE_IDLE && 670 prev_state == MT76_TM_STATE_OFF) || 671 (state == MT76_TM_STATE_OFF && 672 prev_state == MT76_TM_STATE_IDLE)) { 673 u32 changed = 0; 674 int i; 675 676 for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) { 677 u16 cur = tm_change_map[i]; 678 679 if (td->param_set[cur / 32] & BIT(cur % 32)) 680 changed |= BIT(i); 681 } 682 683 mt7915_tm_update_params(phy, changed); 684 } 685 686 return 0; 687} 688 689static int 690mt7915_tm_set_params(struct mt76_phy *mphy, struct nlattr **tb, 691 enum mt76_testmode_state new_state) 692{ 693 struct mt76_testmode_data *td = &mphy->test; 694 struct mt7915_phy *phy = mphy->priv; 695 struct mt7915_dev *dev = phy->dev; 696 u32 chainmask = mphy->chainmask, changed = 0; 697 bool ext_phy = phy != &dev->phy; 698 int i; 699 700 BUILD_BUG_ON(NUM_TM_CHANGED >= 32); 701 702 if (new_state == MT76_TM_STATE_OFF || 703 td->state == MT76_TM_STATE_OFF) 704 return 0; 705 706 chainmask = ext_phy ? chainmask >> dev->chainshift : chainmask; 707 if (td->tx_antenna_mask > chainmask) 708 return -EINVAL; 709 710 for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) { 711 if (tb[tm_change_map[i]]) 712 changed |= BIT(i); 713 } 714 715 mt7915_tm_update_params(phy, changed); 716 717 return 0; 718} 719 720static int 721mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg) 722{ 723 struct mt7915_phy *phy = mphy->priv; 724 struct mt7915_dev *dev = phy->dev; 725 enum mt76_rxq_id q; 726 void *rx, *rssi; 727 u16 fcs_err; 728 int i; 729 u32 cnt; 730 731 rx = nla_nest_start(msg, MT76_TM_STATS_ATTR_LAST_RX); 732 if (!rx) 733 return -ENOMEM; 734 735 if (nla_put_s32(msg, MT76_TM_RX_ATTR_FREQ_OFFSET, phy->test.last_freq_offset)) 736 return -ENOMEM; 737 738 rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_RCPI); 739 if (!rssi) 740 return -ENOMEM; 741 742 for (i = 0; i < ARRAY_SIZE(phy->test.last_rcpi); i++) 743 if (nla_put_u8(msg, i, phy->test.last_rcpi[i])) 744 return -ENOMEM; 745 746 nla_nest_end(msg, rssi); 747 748 rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_IB_RSSI); 749 if (!rssi) 750 return -ENOMEM; 751 752 for (i = 0; i < ARRAY_SIZE(phy->test.last_ib_rssi); i++) 753 if (nla_put_s8(msg, i, phy->test.last_ib_rssi[i])) 754 return -ENOMEM; 755 756 nla_nest_end(msg, rssi); 757 758 rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_WB_RSSI); 759 if (!rssi) 760 return -ENOMEM; 761 762 for (i = 0; i < ARRAY_SIZE(phy->test.last_wb_rssi); i++) 763 if (nla_put_s8(msg, i, phy->test.last_wb_rssi[i])) 764 return -ENOMEM; 765 766 nla_nest_end(msg, rssi); 767 768 if (nla_put_u8(msg, MT76_TM_RX_ATTR_SNR, phy->test.last_snr)) 769 return -ENOMEM; 770 771 nla_nest_end(msg, rx); 772 773 cnt = mt76_rr(dev, MT_MIB_SDR3(phy->mt76->band_idx)); 774 fcs_err = is_mt7915(&dev->mt76) ? FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) : 775 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt); 776 777 q = phy->mt76->band_idx ? MT_RXQ_BAND1 : MT_RXQ_MAIN; 778 mphy->test.rx_stats.packets[q] += fcs_err; 779 mphy->test.rx_stats.fcs_error[q] += fcs_err; 780 781 return 0; 782} 783 784const struct mt76_testmode_ops mt7915_testmode_ops = { 785 .set_state = mt7915_tm_set_state, 786 .set_params = mt7915_tm_set_params, 787 .dump_stats = mt7915_tm_dump_stats, 788}; 789