1/* SPDX-License-Identifier: ISC */
2
3#ifndef __MT7603_H
4#define __MT7603_H
5
6#include <linux/interrupt.h>
7#include <linux/ktime.h>
8#include "../mt76.h"
9#include "regs.h"
10
11#define MT7603_MAX_INTERFACES	4
12#define MT7603_WTBL_SIZE	128
13#define MT7603_WTBL_RESERVED	(MT7603_WTBL_SIZE - 1)
14#define MT7603_WTBL_STA		(MT7603_WTBL_RESERVED - MT7603_MAX_INTERFACES)
15
16#define MT7603_RATE_RETRY	2
17
18#define MT7603_MCU_RX_RING_SIZE	64
19#define MT7603_RX_RING_SIZE     128
20#define MT7603_TX_RING_SIZE	256
21#define MT7603_PSD_RING_SIZE	128
22
23#define MT7603_FIRMWARE_E1	"mt7603_e1.bin"
24#define MT7603_FIRMWARE_E2	"mt7603_e2.bin"
25#define MT7628_FIRMWARE_E1	"mt7628_e1.bin"
26#define MT7628_FIRMWARE_E2	"mt7628_e2.bin"
27
28#define MT7603_EEPROM_SIZE	1024
29
30#define MT_AGG_SIZE_LIMIT(_n)	(((_n) + 1) * 4)
31
32#define MT7603_PRE_TBTT_TIME	5000 /* ms */
33
34#define MT7603_WATCHDOG_TIME	100 /* ms */
35#define MT7603_WATCHDOG_TIMEOUT	10 /* number of checks */
36
37#define MT7603_EDCCA_BLOCK_TH	10
38
39#define MT7603_CFEND_RATE_DEFAULT	0x69 /* chip default (24M) */
40#define MT7603_CFEND_RATE_11B		0x03 /* 11B LP, 11M */
41
42struct mt7603_vif;
43struct mt7603_sta;
44
45enum {
46	MT7603_REV_E1 = 0x00,
47	MT7603_REV_E2 = 0x10,
48	MT7628_REV_E1 = 0x8a00,
49};
50
51enum mt7603_bw {
52	MT_BW_20,
53	MT_BW_40,
54	MT_BW_80,
55};
56
57struct mt7603_rate_set {
58	struct ieee80211_tx_rate probe_rate;
59	struct ieee80211_tx_rate rates[4];
60};
61
62struct mt7603_sta {
63	struct mt76_wcid wcid; /* must be first */
64
65	struct mt7603_vif *vif;
66
67	u32 tx_airtime_ac[4];
68
69	struct sk_buff_head psq;
70
71	struct ieee80211_tx_rate rates[4];
72
73	struct mt7603_rate_set rateset[2];
74	u32 rate_set_tsf;
75
76	u8 rate_count;
77	u8 n_rates;
78
79	u8 rate_probe;
80	u8 smps;
81
82	u8 ps;
83};
84
85struct mt7603_vif {
86	struct mt7603_sta sta; /* must be first */
87
88	u8 idx;
89};
90
91enum mt7603_reset_cause {
92	RESET_CAUSE_TX_HANG,
93	RESET_CAUSE_TX_BUSY,
94	RESET_CAUSE_RX_BUSY,
95	RESET_CAUSE_BEACON_STUCK,
96	RESET_CAUSE_RX_PSE_BUSY,
97	RESET_CAUSE_MCU_HANG,
98	RESET_CAUSE_RESET_FAILED,
99	__RESET_CAUSE_MAX
100};
101
102struct mt7603_dev {
103	union { /* must be first */
104		struct mt76_dev mt76;
105		struct mt76_phy mphy;
106	};
107
108	const struct mt76_bus_ops *bus_ops;
109
110	u32 rxfilter;
111
112	struct mt7603_sta global_sta;
113
114	u32 agc0, agc3;
115	u32 false_cca_ofdm, false_cca_cck;
116	unsigned long last_cca_adj;
117
118	u32 ampdu_ref;
119	u32 rx_ampdu_ts;
120	u8 rssi_offset[3];
121
122	u8 slottime;
123	s16 coverage_class;
124
125	s8 tx_power_limit;
126
127	ktime_t ed_time;
128
129	spinlock_t ps_lock;
130
131	u8 mcu_running;
132
133	u8 ed_monitor_enabled;
134	u8 ed_monitor;
135	s8 ed_trigger;
136	u8 ed_strict_mode;
137	u8 ed_strong_signal;
138
139	bool dynamic_sensitivity;
140	s8 sensitivity;
141	u8 sensitivity_limit;
142
143	u8 beacon_check;
144	u8 tx_hang_check;
145	u8 tx_dma_check;
146	u8 rx_dma_check;
147	u8 rx_pse_check;
148	u8 mcu_hang;
149
150	enum mt7603_reset_cause cur_reset_cause;
151
152	u16 tx_dma_idx[4];
153	u16 rx_dma_idx;
154
155	u32 reset_test;
156
157	unsigned int reset_cause[__RESET_CAUSE_MAX];
158};
159
160extern const struct mt76_driver_ops mt7603_drv_ops;
161extern const struct ieee80211_ops mt7603_ops;
162extern struct pci_driver mt7603_pci_driver;
163extern struct platform_driver mt76_wmac_driver;
164
165static inline bool is_mt7603(struct mt7603_dev *dev)
166{
167	return mt76xx_chip(dev) == 0x7603;
168}
169
170static inline bool is_mt7628(struct mt7603_dev *dev)
171{
172	return mt76xx_chip(dev) == 0x7628;
173}
174
175/* need offset to prevent conflict with ampdu_ack_len */
176#define MT_RATE_DRIVER_DATA_OFFSET	4
177
178u32 mt7603_reg_map(struct mt7603_dev *dev, u32 addr);
179
180irqreturn_t mt7603_irq_handler(int irq, void *dev_instance);
181
182int mt7603_register_device(struct mt7603_dev *dev);
183void mt7603_unregister_device(struct mt7603_dev *dev);
184int mt7603_eeprom_init(struct mt7603_dev *dev);
185int mt7603_dma_init(struct mt7603_dev *dev);
186void mt7603_dma_cleanup(struct mt7603_dev *dev);
187int mt7603_mcu_init(struct mt7603_dev *dev);
188void mt7603_init_debugfs(struct mt7603_dev *dev);
189
190static inline void mt7603_irq_enable(struct mt7603_dev *dev, u32 mask)
191{
192	mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, 0, mask);
193}
194
195static inline void mt7603_irq_disable(struct mt7603_dev *dev, u32 mask)
196{
197	mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
198}
199
200void mt7603_mac_reset_counters(struct mt7603_dev *dev);
201void mt7603_mac_dma_start(struct mt7603_dev *dev);
202void mt7603_mac_start(struct mt7603_dev *dev);
203void mt7603_mac_stop(struct mt7603_dev *dev);
204void mt7603_mac_work(struct work_struct *work);
205void mt7603_mac_set_timing(struct mt7603_dev *dev);
206void mt7603_beacon_set_timer(struct mt7603_dev *dev, int idx, int intval);
207int mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb);
208void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data);
209void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid);
210void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid,
211			    int ba_size);
212void mt7603_mac_sta_poll(struct mt7603_dev *dev);
213
214void mt7603_pse_client_reset(struct mt7603_dev *dev);
215
216int mt7603_mcu_set_channel(struct mt7603_dev *dev);
217int mt7603_mcu_set_eeprom(struct mt7603_dev *dev);
218void mt7603_mcu_exit(struct mt7603_dev *dev);
219
220void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif,
221		      const u8 *mac_addr);
222void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx);
223void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta);
224void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta,
225			   struct ieee80211_tx_rate *probe_rate,
226			   struct ieee80211_tx_rate *rates);
227int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid,
228			struct ieee80211_key_conf *key);
229void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta,
230			bool enabled);
231void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta,
232			  bool enabled);
233void mt7603_filter_tx(struct mt7603_dev *dev, int mac_idx, int idx, bool abort);
234
235int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
236			  enum mt76_txq_id qid, struct mt76_wcid *wcid,
237			  struct ieee80211_sta *sta,
238			  struct mt76_tx_info *tx_info);
239
240void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);
241
242void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
243			 struct sk_buff *skb, u32 *info);
244void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
245void mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
246int mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
247		   struct ieee80211_sta *sta);
248void mt7603_sta_assoc(struct mt76_dev *mdev, struct ieee80211_vif *vif,
249		      struct ieee80211_sta *sta);
250void mt7603_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
251		       struct ieee80211_sta *sta);
252
253void mt7603_pre_tbtt_tasklet(struct tasklet_struct *t);
254
255void mt7603_update_channel(struct mt76_phy *mphy);
256
257void mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val);
258void mt7603_cca_stats_reset(struct mt7603_dev *dev);
259
260void mt7603_init_edcca(struct mt7603_dev *dev);
261#endif
262