1// SPDX-License-Identifier: ISC 2 3#include "mt7603.h" 4 5struct beacon_bc_data { 6 struct mt7603_dev *dev; 7 struct sk_buff_head q; 8 struct sk_buff *tail[MT7603_MAX_INTERFACES]; 9 int count[MT7603_MAX_INTERFACES]; 10}; 11 12static void 13mt7603_mac_stuck_beacon_recovery(struct mt7603_dev *dev) 14{ 15 if (dev->beacon_check % 5 != 4) 16 return; 17 18 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_EN); 19 mt76_set(dev, MT_SCH_4, MT_SCH_4_RESET); 20 mt76_clear(dev, MT_SCH_4, MT_SCH_4_RESET); 21 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_EN); 22 23 mt76_set(dev, MT_WF_CFG_OFF_WOCCR, MT_WF_CFG_OFF_WOCCR_TMAC_GC_DIS); 24 mt76_set(dev, MT_ARB_SCR, MT_ARB_SCR_TX_DISABLE); 25 mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_TX_DISABLE); 26 mt76_clear(dev, MT_WF_CFG_OFF_WOCCR, MT_WF_CFG_OFF_WOCCR_TMAC_GC_DIS); 27} 28 29static void 30mt7603_update_beacon_iter(void *priv, u8 *mac, struct ieee80211_vif *vif) 31{ 32 struct mt7603_dev *dev = (struct mt7603_dev *)priv; 33 struct mt76_dev *mdev = &dev->mt76; 34 struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv; 35 struct sk_buff *skb = NULL; 36 u32 om_idx = mvif->idx; 37 u32 val; 38 39 if (!(mdev->beacon_mask & BIT(mvif->idx))) 40 return; 41 42 skb = ieee80211_beacon_get(mt76_hw(dev), vif, 0); 43 if (!skb) 44 return; 45 46 if (om_idx) 47 om_idx |= 0x10; 48 val = MT_DMA_FQCR0_BUSY | MT_DMA_FQCR0_MODE | 49 FIELD_PREP(MT_DMA_FQCR0_TARGET_BSS, om_idx) | 50 FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, 3) | 51 FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, 8); 52 53 spin_lock_bh(&dev->ps_lock); 54 55 mt76_wr(dev, MT_DMA_FQCR0, val | 56 FIELD_PREP(MT_DMA_FQCR0_TARGET_QID, MT_TX_HW_QUEUE_BCN)); 57 if (!mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 5000)) { 58 dev->beacon_check = MT7603_WATCHDOG_TIMEOUT; 59 goto out; 60 } 61 62 mt76_wr(dev, MT_DMA_FQCR0, val | 63 FIELD_PREP(MT_DMA_FQCR0_TARGET_QID, MT_TX_HW_QUEUE_BMC)); 64 if (!mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 5000)) { 65 dev->beacon_check = MT7603_WATCHDOG_TIMEOUT; 66 goto out; 67 } 68 69 mt76_tx_queue_skb(dev, dev->mphy.q_tx[MT_TXQ_BEACON], 70 MT_TXQ_BEACON, skb, &mvif->sta.wcid, NULL); 71 72out: 73 spin_unlock_bh(&dev->ps_lock); 74} 75 76static void 77mt7603_add_buffered_bc(void *priv, u8 *mac, struct ieee80211_vif *vif) 78{ 79 struct beacon_bc_data *data = priv; 80 struct mt7603_dev *dev = data->dev; 81 struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv; 82 struct ieee80211_tx_info *info; 83 struct sk_buff *skb; 84 85 if (!(dev->mt76.beacon_mask & BIT(mvif->idx))) 86 return; 87 88 skb = ieee80211_get_buffered_bc(mt76_hw(dev), vif); 89 if (!skb) 90 return; 91 92 info = IEEE80211_SKB_CB(skb); 93 info->control.vif = vif; 94 info->flags |= IEEE80211_TX_CTL_ASSIGN_SEQ; 95 mt76_skb_set_moredata(skb, true); 96 __skb_queue_tail(&data->q, skb); 97 data->tail[mvif->idx] = skb; 98 data->count[mvif->idx]++; 99} 100 101void mt7603_pre_tbtt_tasklet(struct tasklet_struct *t) 102{ 103 struct mt7603_dev *dev = from_tasklet(dev, t, mt76.pre_tbtt_tasklet); 104 struct mt76_dev *mdev = &dev->mt76; 105 struct mt76_queue *q; 106 struct beacon_bc_data data = {}; 107 struct sk_buff *skb; 108 int i, nframes; 109 110 if (mt76_hw(dev)->conf.flags & IEEE80211_CONF_OFFCHANNEL) 111 return; 112 113 data.dev = dev; 114 __skb_queue_head_init(&data.q); 115 116 /* Flush all previous CAB queue packets and beacons */ 117 mt76_wr(dev, MT_WF_ARB_CAB_FLUSH, GENMASK(30, 16) | BIT(0)); 118 119 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_CAB], false); 120 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BEACON], false); 121 122 if (dev->mphy.q_tx[MT_TXQ_BEACON]->queued > 0) 123 dev->beacon_check++; 124 else 125 dev->beacon_check = 0; 126 mt7603_mac_stuck_beacon_recovery(dev); 127 128 q = dev->mphy.q_tx[MT_TXQ_BEACON]; 129 spin_lock(&q->lock); 130 ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev), 131 IEEE80211_IFACE_ITER_RESUME_ALL, 132 mt7603_update_beacon_iter, dev); 133 mt76_queue_kick(dev, q); 134 spin_unlock(&q->lock); 135 136 mt76_csa_check(mdev); 137 if (mdev->csa_complete) 138 return; 139 140 q = dev->mphy.q_tx[MT_TXQ_CAB]; 141 do { 142 nframes = skb_queue_len(&data.q); 143 ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev), 144 IEEE80211_IFACE_ITER_RESUME_ALL, 145 mt7603_add_buffered_bc, &data); 146 } while (nframes != skb_queue_len(&data.q) && 147 skb_queue_len(&data.q) < 8); 148 149 if (skb_queue_empty(&data.q)) 150 return; 151 152 for (i = 0; i < ARRAY_SIZE(data.tail); i++) { 153 if (!data.tail[i]) 154 continue; 155 156 mt76_skb_set_moredata(data.tail[i], false); 157 } 158 159 spin_lock(&q->lock); 160 while ((skb = __skb_dequeue(&data.q)) != NULL) { 161 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 162 struct ieee80211_vif *vif = info->control.vif; 163 struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv; 164 165 mt76_tx_queue_skb(dev, q, MT_TXQ_CAB, skb, &mvif->sta.wcid, NULL); 166 } 167 mt76_queue_kick(dev, q); 168 spin_unlock(&q->lock); 169 170 for (i = 0; i < ARRAY_SIZE(data.count); i++) 171 mt76_wr(dev, MT_WF_ARB_CAB_COUNT_B0_REG(i), 172 data.count[i] << MT_WF_ARB_CAB_COUNT_B0_SHIFT(i)); 173 174 mt76_wr(dev, MT_WF_ARB_CAB_START, 175 MT_WF_ARB_CAB_START_BSSn(0) | 176 (MT_WF_ARB_CAB_START_BSS0n(1) * 177 ((1 << (MT7603_MAX_INTERFACES - 1)) - 1))); 178} 179 180void mt7603_beacon_set_timer(struct mt7603_dev *dev, int idx, int intval) 181{ 182 u32 pre_tbtt = MT7603_PRE_TBTT_TIME / 64; 183 184 if (idx >= 0) { 185 if (intval) 186 dev->mt76.beacon_mask |= BIT(idx); 187 else 188 dev->mt76.beacon_mask &= ~BIT(idx); 189 } 190 191 if (!dev->mt76.beacon_mask || (!intval && idx < 0)) { 192 mt7603_irq_disable(dev, MT_INT_MAC_IRQ3); 193 mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_BCNQ_OPMODE_MASK); 194 mt76_wr(dev, MT_HW_INT_MASK(3), 0); 195 return; 196 } 197 198 if (intval) 199 dev->mt76.beacon_int = intval; 200 mt76_wr(dev, MT_TBTT, 201 FIELD_PREP(MT_TBTT_PERIOD, intval) | MT_TBTT_CAL_ENABLE); 202 203 mt76_wr(dev, MT_TBTT_TIMER_CFG, 0x99); /* start timer */ 204 205 mt76_rmw_field(dev, MT_ARB_SCR, MT_ARB_SCR_BCNQ_OPMODE_MASK, 206 MT_BCNQ_OPMODE_AP); 207 mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_TBTT_BCN_PRIO); 208 mt76_set(dev, MT_ARB_SCR, MT_ARB_SCR_TBTT_BCAST_PRIO); 209 210 mt76_wr(dev, MT_PRE_TBTT, pre_tbtt); 211 212 mt76_set(dev, MT_HW_INT_MASK(3), 213 MT_HW_INT3_PRE_TBTT0 | MT_HW_INT3_TBTT0); 214 215 mt76_set(dev, MT_WF_ARB_BCN_START, 216 MT_WF_ARB_BCN_START_BSSn(0) | 217 ((dev->mt76.beacon_mask >> 1) * 218 MT_WF_ARB_BCN_START_BSS0n(1))); 219 mt7603_irq_enable(dev, MT_INT_MAC_IRQ3); 220 221 if (dev->mt76.beacon_mask & ~BIT(0)) 222 mt76_set(dev, MT_LPON_SBTOR(0), MT_LPON_SBTOR_SUB_BSS_EN); 223 else 224 mt76_clear(dev, MT_LPON_SBTOR(0), MT_LPON_SBTOR_SUB_BSS_EN); 225} 226