1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* 3 * Copyright (C) 2018-2024 Intel Corporation 4 */ 5#include <linux/firmware.h> 6#include "iwl-drv.h" 7#include "iwl-trans.h" 8#include "iwl-dbg-tlv.h" 9#include "fw/dbg.h" 10#include "fw/runtime.h" 11 12/** 13 * enum iwl_dbg_tlv_type - debug TLV types 14 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV 15 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV 16 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV 17 * @IWL_DBG_TLV_TYPE_REGION: region TLV 18 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV 19 * @IWL_DBG_TLV_TYPE_CONF_SET: conf set TLV 20 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs 21 */ 22enum iwl_dbg_tlv_type { 23 IWL_DBG_TLV_TYPE_DEBUG_INFO = 24 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE, 25 IWL_DBG_TLV_TYPE_BUF_ALLOC, 26 IWL_DBG_TLV_TYPE_HCMD, 27 IWL_DBG_TLV_TYPE_REGION, 28 IWL_DBG_TLV_TYPE_TRIGGER, 29 IWL_DBG_TLV_TYPE_CONF_SET, 30 IWL_DBG_TLV_TYPE_NUM, 31}; 32 33/** 34 * struct iwl_dbg_tlv_ver_data - debug TLV version struct 35 * @min_ver: min version supported 36 * @max_ver: max version supported 37 */ 38struct iwl_dbg_tlv_ver_data { 39 int min_ver; 40 int max_ver; 41}; 42 43/** 44 * struct iwl_dbg_tlv_timer_node - timer node struct 45 * @list: list of &struct iwl_dbg_tlv_timer_node 46 * @timer: timer 47 * @fwrt: &struct iwl_fw_runtime 48 * @tlv: TLV attach to the timer node 49 */ 50struct iwl_dbg_tlv_timer_node { 51 struct list_head list; 52 struct timer_list timer; 53 struct iwl_fw_runtime *fwrt; 54 struct iwl_ucode_tlv *tlv; 55}; 56 57static const struct iwl_dbg_tlv_ver_data 58dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = { 59 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,}, 60 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,}, 61 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,}, 62 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 3,}, 63 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,}, 64 [IWL_DBG_TLV_TYPE_CONF_SET] = {.min_ver = 1, .max_ver = 1,}, 65}; 66 67static int iwl_dbg_tlv_add(const struct iwl_ucode_tlv *tlv, 68 struct list_head *list) 69{ 70 u32 len = le32_to_cpu(tlv->length); 71 struct iwl_dbg_tlv_node *node; 72 73 node = kzalloc(sizeof(*node) + len, GFP_KERNEL); 74 if (!node) 75 return -ENOMEM; 76 77 memcpy(&node->tlv, tlv, sizeof(node->tlv)); 78 memcpy(node->tlv.data, tlv->data, len); 79 list_add_tail(&node->list, list); 80 81 return 0; 82} 83 84static bool iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv *tlv) 85{ 86 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; 87 u32 type = le32_to_cpu(tlv->type); 88 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 89 u32 ver = le32_to_cpu(hdr->version); 90 91 if (ver < dbg_ver_table[tlv_idx].min_ver || 92 ver > dbg_ver_table[tlv_idx].max_ver) 93 return false; 94 95 return true; 96} 97 98static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans, 99 const struct iwl_ucode_tlv *tlv) 100{ 101 const struct iwl_fw_ini_debug_info_tlv *debug_info = (const void *)tlv->data; 102 103 if (le32_to_cpu(tlv->length) != sizeof(*debug_info)) 104 return -EINVAL; 105 106 /* we use this as a string, ensure input was NUL terminated */ 107 if (strnlen(debug_info->debug_cfg_name, 108 sizeof(debug_info->debug_cfg_name)) == 109 sizeof(debug_info->debug_cfg_name)) 110 return -EINVAL; 111 112 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n", 113 debug_info->debug_cfg_name); 114 115 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list); 116} 117 118static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans, 119 const struct iwl_ucode_tlv *tlv) 120{ 121 const struct iwl_fw_ini_allocation_tlv *alloc = (const void *)tlv->data; 122 u32 buf_location; 123 u32 alloc_id; 124 125 if (le32_to_cpu(tlv->length) != sizeof(*alloc)) 126 return -EINVAL; 127 128 buf_location = le32_to_cpu(alloc->buf_location); 129 alloc_id = le32_to_cpu(alloc->alloc_id); 130 131 if (buf_location == IWL_FW_INI_LOCATION_INVALID || 132 buf_location >= IWL_FW_INI_LOCATION_NUM) 133 goto err; 134 135 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID || 136 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 137 goto err; 138 139 if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH && 140 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 141 goto err; 142 143 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH && 144 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 145 goto err; 146 147 if (buf_location == IWL_FW_INI_LOCATION_DRAM_PATH && 148 alloc->req_size == 0) { 149 IWL_ERR(trans, "WRT: Invalid DRAM buffer allocation requested size (0)\n"); 150 return -EINVAL; 151 } 152 153 trans->dbg.fw_mon_cfg[alloc_id] = *alloc; 154 155 return 0; 156err: 157 IWL_ERR(trans, 158 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n", 159 alloc_id, buf_location); 160 return -EINVAL; 161} 162 163static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans, 164 const struct iwl_ucode_tlv *tlv) 165{ 166 const struct iwl_fw_ini_hcmd_tlv *hcmd = (const void *)tlv->data; 167 u32 tp = le32_to_cpu(hcmd->time_point); 168 169 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd)) 170 return -EINVAL; 171 172 /* Host commands can not be sent in early time point since the FW 173 * is not ready 174 */ 175 if (tp == IWL_FW_INI_TIME_POINT_INVALID || 176 tp >= IWL_FW_INI_TIME_POINT_NUM || 177 tp == IWL_FW_INI_TIME_POINT_EARLY) { 178 IWL_ERR(trans, 179 "WRT: Invalid time point %u for host command TLV\n", 180 tp); 181 return -EINVAL; 182 } 183 184 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list); 185} 186 187static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans, 188 const struct iwl_ucode_tlv *tlv) 189{ 190 const struct iwl_fw_ini_region_tlv *reg = (const void *)tlv->data; 191 struct iwl_ucode_tlv **active_reg; 192 u32 id = le32_to_cpu(reg->id); 193 u8 type = reg->type; 194 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length); 195 196 /* 197 * The higher part of the ID from version 2 is debug policy. 198 * The id will be only lsb 16 bits, so mask it out. 199 */ 200 if (le32_to_cpu(reg->hdr.version) >= 2) 201 id &= IWL_FW_INI_REGION_ID_MASK; 202 203 if (le32_to_cpu(tlv->length) < sizeof(*reg)) 204 return -EINVAL; 205 206 /* for safe use of a string from FW, limit it to IWL_FW_INI_MAX_NAME */ 207 IWL_DEBUG_FW(trans, "WRT: parsing region: %.*s\n", 208 IWL_FW_INI_MAX_NAME, reg->name); 209 210 if (id >= IWL_FW_INI_MAX_REGION_ID) { 211 IWL_ERR(trans, "WRT: Invalid region id %u\n", id); 212 return -EINVAL; 213 } 214 215 if (type <= IWL_FW_INI_REGION_INVALID || 216 type >= IWL_FW_INI_REGION_NUM) { 217 IWL_ERR(trans, "WRT: Invalid region type %u\n", type); 218 return -EINVAL; 219 } 220 221 if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG && 222 !trans->ops->read_config32) { 223 IWL_ERR(trans, "WRT: Unsupported region type %u\n", type); 224 return -EOPNOTSUPP; 225 } 226 227 if (type == IWL_FW_INI_REGION_INTERNAL_BUFFER) { 228 trans->dbg.imr_data.sram_addr = 229 le32_to_cpu(reg->internal_buffer.base_addr); 230 trans->dbg.imr_data.sram_size = 231 le32_to_cpu(reg->internal_buffer.size); 232 } 233 234 235 active_reg = &trans->dbg.active_regions[id]; 236 if (*active_reg) { 237 IWL_WARN(trans, "WRT: Overriding region id %u\n", id); 238 239 kfree(*active_reg); 240 } 241 242 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL); 243 if (!*active_reg) 244 return -ENOMEM; 245 246 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type); 247 248 return 0; 249} 250 251static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans, 252 const struct iwl_ucode_tlv *tlv) 253{ 254 const struct iwl_fw_ini_trigger_tlv *trig = (const void *)tlv->data; 255 struct iwl_fw_ini_trigger_tlv *dup_trig; 256 u32 tp = le32_to_cpu(trig->time_point); 257 u32 rf = le32_to_cpu(trig->reset_fw); 258 struct iwl_ucode_tlv *dup = NULL; 259 int ret; 260 261 if (le32_to_cpu(tlv->length) < sizeof(*trig)) 262 return -EINVAL; 263 264 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 265 tp >= IWL_FW_INI_TIME_POINT_NUM) { 266 IWL_ERR(trans, 267 "WRT: Invalid time point %u for trigger TLV\n", 268 tp); 269 return -EINVAL; 270 } 271 272 IWL_DEBUG_FW(trans, 273 "WRT: time point %u for trigger TLV with reset_fw %u\n", 274 tp, rf); 275 trans->dbg.last_tp_resetfw = 0xFF; 276 if (!le32_to_cpu(trig->occurrences)) { 277 dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length), 278 GFP_KERNEL); 279 if (!dup) 280 return -ENOMEM; 281 dup_trig = (void *)dup->data; 282 dup_trig->occurrences = cpu_to_le32(-1); 283 tlv = dup; 284 } 285 286 ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list); 287 kfree(dup); 288 289 return ret; 290} 291 292static int iwl_dbg_tlv_config_set(struct iwl_trans *trans, 293 const struct iwl_ucode_tlv *tlv) 294{ 295 const struct iwl_fw_ini_conf_set_tlv *conf_set = (const void *)tlv->data; 296 u32 tp = le32_to_cpu(conf_set->time_point); 297 u32 type = le32_to_cpu(conf_set->set_type); 298 299 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 300 tp >= IWL_FW_INI_TIME_POINT_NUM) { 301 IWL_DEBUG_FW(trans, 302 "WRT: Invalid time point %u for config set TLV\n", tp); 303 return -EINVAL; 304 } 305 306 if (type <= IWL_FW_INI_CONFIG_SET_TYPE_INVALID || 307 type >= IWL_FW_INI_CONFIG_SET_TYPE_MAX_NUM) { 308 IWL_DEBUG_FW(trans, 309 "WRT: Invalid config set type %u for config set TLV\n", type); 310 return -EINVAL; 311 } 312 313 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].config_list); 314} 315 316static int (*dbg_tlv_alloc[])(struct iwl_trans *trans, 317 const struct iwl_ucode_tlv *tlv) = { 318 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info, 319 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc, 320 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd, 321 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region, 322 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger, 323 [IWL_DBG_TLV_TYPE_CONF_SET] = iwl_dbg_tlv_config_set, 324}; 325 326void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv, 327 bool ext) 328{ 329 enum iwl_ini_cfg_state *cfg_state = ext ? 330 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg; 331 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; 332 u32 type; 333 u32 tlv_idx; 334 u32 domain; 335 int ret; 336 337 if (le32_to_cpu(tlv->length) < sizeof(*hdr)) 338 return; 339 340 type = le32_to_cpu(tlv->type); 341 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 342 domain = le32_to_cpu(hdr->domain); 343 344 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON && 345 !(domain & trans->dbg.domains_bitmap)) { 346 IWL_DEBUG_FW(trans, 347 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n", 348 domain, trans->dbg.domains_bitmap); 349 return; 350 } 351 352 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) { 353 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type); 354 goto out_err; 355 } 356 357 if (!iwl_dbg_tlv_ver_support(tlv)) { 358 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type, 359 le32_to_cpu(hdr->version)); 360 goto out_err; 361 } 362 363 ret = dbg_tlv_alloc[tlv_idx](trans, tlv); 364 if (ret) { 365 IWL_WARN(trans, 366 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n", 367 type, ret, ext); 368 goto out_err; 369 } 370 371 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED) 372 *cfg_state = IWL_INI_CFG_STATE_LOADED; 373 374 return; 375 376out_err: 377 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED; 378} 379 380void iwl_dbg_tlv_del_timers(struct iwl_trans *trans) 381{ 382 struct list_head *timer_list = &trans->dbg.periodic_trig_list; 383 struct iwl_dbg_tlv_timer_node *node, *tmp; 384 385 list_for_each_entry_safe(node, tmp, timer_list, list) { 386 timer_shutdown_sync(&node->timer); 387 list_del(&node->list); 388 kfree(node); 389 } 390} 391IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers); 392 393static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans, 394 enum iwl_fw_ini_allocation_id alloc_id) 395{ 396 struct iwl_fw_mon *fw_mon; 397 int i; 398 399 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || 400 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 401 return; 402 403 fw_mon = &trans->dbg.fw_mon_ini[alloc_id]; 404 405 for (i = 0; i < fw_mon->num_frags; i++) { 406 struct iwl_dram_data *frag = &fw_mon->frags[i]; 407 408 dma_free_coherent(trans->dev, frag->size, frag->block, 409 frag->physical); 410 411 frag->physical = 0; 412 frag->block = NULL; 413 frag->size = 0; 414 } 415 416 kfree(fw_mon->frags); 417 fw_mon->frags = NULL; 418 fw_mon->num_frags = 0; 419} 420 421void iwl_dbg_tlv_free(struct iwl_trans *trans) 422{ 423 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp; 424 int i; 425 426 iwl_dbg_tlv_del_timers(trans); 427 428 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) { 429 struct iwl_ucode_tlv **active_reg = 430 &trans->dbg.active_regions[i]; 431 432 kfree(*active_reg); 433 *active_reg = NULL; 434 } 435 436 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 437 &trans->dbg.debug_info_tlv_list, list) { 438 list_del(&tlv_node->list); 439 kfree(tlv_node); 440 } 441 442 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 443 struct iwl_dbg_tlv_time_point_data *tp = 444 &trans->dbg.time_point[i]; 445 446 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list, 447 list) { 448 list_del(&tlv_node->list); 449 kfree(tlv_node); 450 } 451 452 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list, 453 list) { 454 list_del(&tlv_node->list); 455 kfree(tlv_node); 456 } 457 458 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 459 &tp->active_trig_list, list) { 460 list_del(&tlv_node->list); 461 kfree(tlv_node); 462 } 463 464 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 465 &tp->config_list, list) { 466 list_del(&tlv_node->list); 467 kfree(tlv_node); 468 } 469 470 } 471 472 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++) 473 iwl_dbg_tlv_fragments_free(trans, i); 474} 475 476static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data, 477 size_t len) 478{ 479 const struct iwl_ucode_tlv *tlv; 480 u32 tlv_len; 481 482 while (len >= sizeof(*tlv)) { 483 len -= sizeof(*tlv); 484 tlv = (const void *)data; 485 486 tlv_len = le32_to_cpu(tlv->length); 487 488 if (len < tlv_len) { 489 IWL_ERR(trans, "invalid TLV len: %zd/%u\n", 490 len, tlv_len); 491 return -EINVAL; 492 } 493 len -= ALIGN(tlv_len, 4); 494 data += sizeof(*tlv) + ALIGN(tlv_len, 4); 495 496 iwl_dbg_tlv_alloc(trans, tlv, true); 497 } 498 499 return 0; 500} 501 502void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans) 503{ 504 const struct firmware *fw; 505 const char *yoyo_bin = "iwl-debug-yoyo.bin"; 506 int res; 507 508 if (!iwlwifi_mod_params.enable_ini || 509 trans->trans_cfg->device_family <= IWL_DEVICE_FAMILY_8000) 510 return; 511 512 res = firmware_request_nowarn(&fw, yoyo_bin, dev); 513 IWL_DEBUG_FW(trans, "%s %s\n", res ? "didn't load" : "loaded", yoyo_bin); 514 515 if (res) 516 return; 517 518 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size); 519 520 release_firmware(fw); 521} 522 523void iwl_dbg_tlv_init(struct iwl_trans *trans) 524{ 525 int i; 526 527 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list); 528 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list); 529 530 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 531 struct iwl_dbg_tlv_time_point_data *tp = 532 &trans->dbg.time_point[i]; 533 534 INIT_LIST_HEAD(&tp->trig_list); 535 INIT_LIST_HEAD(&tp->hcmd_list); 536 INIT_LIST_HEAD(&tp->active_trig_list); 537 INIT_LIST_HEAD(&tp->config_list); 538 } 539} 540 541static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt, 542 struct iwl_dram_data *frag, u32 pages) 543{ 544 void *block = NULL; 545 dma_addr_t physical; 546 547 if (!frag || frag->size || !pages) 548 return -EIO; 549 550 /* 551 * We try to allocate as many pages as we can, starting with 552 * the requested amount and going down until we can allocate 553 * something. Because of DIV_ROUND_UP(), pages will never go 554 * down to 0 and stop the loop, so stop when pages reaches 1, 555 * which is too small anyway. 556 */ 557 while (pages > 1) { 558 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE, 559 &physical, 560 GFP_KERNEL | __GFP_NOWARN); 561 if (block) 562 break; 563 564 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n", 565 pages * PAGE_SIZE); 566 567 pages = DIV_ROUND_UP(pages, 2); 568 } 569 570 if (!block) 571 return -ENOMEM; 572 573 frag->physical = physical; 574 frag->block = block; 575 frag->size = pages * PAGE_SIZE; 576 577 return pages; 578} 579 580static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt, 581 enum iwl_fw_ini_allocation_id alloc_id) 582{ 583 struct iwl_fw_mon *fw_mon; 584 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 585 u32 num_frags, remain_pages, frag_pages; 586 int i; 587 588 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 589 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 590 return -EIO; 591 592 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id]; 593 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 594 595 if (fw_mon->num_frags) { 596 for (i = 0; i < fw_mon->num_frags; i++) 597 memset(fw_mon->frags[i].block, 0, 598 fw_mon->frags[i].size); 599 return 0; 600 } 601 602 if (fw_mon_cfg->buf_location != 603 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH)) 604 return 0; 605 606 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num); 607 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) { 608 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 609 return -EIO; 610 num_frags = 1; 611 } else if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_BZ && 612 alloc_id > IWL_FW_INI_ALLOCATION_ID_DBGC3) { 613 return -EIO; 614 } 615 616 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size), 617 PAGE_SIZE); 618 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS); 619 num_frags = min_t(u32, num_frags, remain_pages); 620 frag_pages = DIV_ROUND_UP(remain_pages, num_frags); 621 622 fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL); 623 if (!fw_mon->frags) 624 return -ENOMEM; 625 626 for (i = 0; i < num_frags; i++) { 627 int pages = min_t(u32, frag_pages, remain_pages); 628 629 IWL_DEBUG_FW(fwrt, 630 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n", 631 alloc_id, i, pages * PAGE_SIZE); 632 633 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i], 634 pages); 635 if (pages < 0) { 636 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) - 637 (remain_pages * PAGE_SIZE); 638 639 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) { 640 iwl_dbg_tlv_fragments_free(fwrt->trans, 641 alloc_id); 642 return pages; 643 } 644 break; 645 } 646 647 remain_pages -= pages; 648 fw_mon->num_frags++; 649 } 650 651 return 0; 652} 653 654static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt, 655 enum iwl_fw_ini_allocation_id alloc_id) 656{ 657 struct iwl_fw_mon *fw_mon; 658 u32 remain_frags, num_commands; 659 int i, fw_mon_idx = 0; 660 661 if (!fw_has_capa(&fwrt->fw->ucode_capa, 662 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) 663 return 0; 664 665 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 666 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 667 return -EIO; 668 669 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 670 IWL_FW_INI_LOCATION_DRAM_PATH) 671 return 0; 672 673 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 674 675 /* the first fragment of DBGC1 is given to the FW via register 676 * or context info 677 */ 678 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 679 fw_mon_idx++; 680 681 remain_frags = fw_mon->num_frags - fw_mon_idx; 682 if (!remain_frags) 683 return 0; 684 685 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 686 687 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n", 688 alloc_id); 689 690 for (i = 0; i < num_commands; i++) { 691 u32 num_frags = min_t(u32, remain_frags, 692 BUF_ALLOC_MAX_NUM_FRAGS); 693 struct iwl_buf_alloc_cmd data = { 694 .alloc_id = cpu_to_le32(alloc_id), 695 .num_frags = cpu_to_le32(num_frags), 696 .buf_location = 697 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH), 698 }; 699 struct iwl_host_cmd hcmd = { 700 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION), 701 .data[0] = &data, 702 .len[0] = sizeof(data), 703 .flags = CMD_SEND_IN_RFKILL, 704 }; 705 int ret, j; 706 707 for (j = 0; j < num_frags; j++) { 708 struct iwl_buf_alloc_frag *frag = &data.frags[j]; 709 struct iwl_dram_data *fw_mon_frag = 710 &fw_mon->frags[fw_mon_idx++]; 711 712 frag->addr = cpu_to_le64(fw_mon_frag->physical); 713 frag->size = cpu_to_le32(fw_mon_frag->size); 714 } 715 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 716 if (ret) 717 return ret; 718 719 remain_frags -= num_frags; 720 } 721 722 return 0; 723} 724 725static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt) 726{ 727 int ret, i; 728 729 if (fw_has_capa(&fwrt->fw->ucode_capa, 730 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT)) 731 return; 732 733 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 734 ret = iwl_dbg_tlv_apply_buffer(fwrt, i); 735 if (ret) 736 IWL_WARN(fwrt, 737 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n", 738 i, ret); 739 } 740} 741 742static int iwl_dbg_tlv_update_dram(struct iwl_fw_runtime *fwrt, 743 enum iwl_fw_ini_allocation_id alloc_id, 744 struct iwl_dram_info *dram_info) 745{ 746 struct iwl_fw_mon *fw_mon; 747 u32 remain_frags, num_frags; 748 int j, fw_mon_idx = 0; 749 struct iwl_buf_alloc_cmd *data; 750 751 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 752 IWL_FW_INI_LOCATION_DRAM_PATH) { 753 IWL_DEBUG_FW(fwrt, "WRT: alloc_id %u location is not in DRAM_PATH\n", 754 alloc_id); 755 return -1; 756 } 757 758 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 759 760 /* the first fragment of DBGC1 is given to the FW via register 761 * or context info 762 */ 763 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 764 fw_mon_idx++; 765 766 remain_frags = fw_mon->num_frags - fw_mon_idx; 767 if (!remain_frags) 768 return -1; 769 770 num_frags = min_t(u32, remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 771 data = &dram_info->dram_frags[alloc_id - 1]; 772 data->alloc_id = cpu_to_le32(alloc_id); 773 data->num_frags = cpu_to_le32(num_frags); 774 data->buf_location = cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH); 775 776 IWL_DEBUG_FW(fwrt, "WRT: DRAM buffer details alloc_id=%u, num_frags=%u\n", 777 cpu_to_le32(alloc_id), cpu_to_le32(num_frags)); 778 779 for (j = 0; j < num_frags; j++) { 780 struct iwl_buf_alloc_frag *frag = &data->frags[j]; 781 struct iwl_dram_data *fw_mon_frag = &fw_mon->frags[fw_mon_idx++]; 782 783 frag->addr = cpu_to_le64(fw_mon_frag->physical); 784 frag->size = cpu_to_le32(fw_mon_frag->size); 785 IWL_DEBUG_FW(fwrt, "WRT: DRAM fragment details\n"); 786 IWL_DEBUG_FW(fwrt, "frag=%u, addr=0x%016llx, size=0x%x)\n", 787 j, cpu_to_le64(fw_mon_frag->physical), 788 cpu_to_le32(fw_mon_frag->size)); 789 } 790 return 0; 791} 792 793static void iwl_dbg_tlv_update_drams(struct iwl_fw_runtime *fwrt) 794{ 795 int ret, i; 796 bool dram_alloc = false; 797 struct iwl_dram_data *frags = 798 &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0]; 799 struct iwl_dram_info *dram_info; 800 801 if (!frags || !frags->block) 802 return; 803 804 dram_info = frags->block; 805 806 if (!fw_has_capa(&fwrt->fw->ucode_capa, 807 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT)) 808 return; 809 810 memset(dram_info, 0, sizeof(*dram_info)); 811 812 for (i = IWL_FW_INI_ALLOCATION_ID_DBGC1; 813 i < IWL_FW_INI_ALLOCATION_NUM; i++) { 814 if (fwrt->trans->dbg.fw_mon_cfg[i].buf_location == 815 IWL_FW_INI_LOCATION_INVALID) 816 continue; 817 818 ret = iwl_dbg_tlv_update_dram(fwrt, i, dram_info); 819 if (!ret) 820 dram_alloc = true; 821 else 822 IWL_INFO(fwrt, 823 "WRT: Failed to set DRAM buffer for alloc id %d, ret=%d\n", 824 i, ret); 825 } 826 827 if (dram_alloc) { 828 dram_info->first_word = cpu_to_le32(DRAM_INFO_FIRST_MAGIC_WORD); 829 dram_info->second_word = cpu_to_le32(DRAM_INFO_SECOND_MAGIC_WORD); 830 } 831} 832 833static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt, 834 struct list_head *hcmd_list) 835{ 836 struct iwl_dbg_tlv_node *node; 837 838 list_for_each_entry(node, hcmd_list, list) { 839 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data; 840 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd; 841 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd); 842 struct iwl_host_cmd cmd = { 843 .id = WIDE_ID(hcmd_data->group, hcmd_data->id), 844 .len = { hcmd_len, }, 845 .data = { hcmd_data->data, }, 846 }; 847 848 iwl_trans_send_cmd(fwrt->trans, &cmd); 849 } 850} 851 852static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt, 853 struct list_head *conf_list) 854{ 855 struct iwl_dbg_tlv_node *node; 856 857 list_for_each_entry(node, conf_list, list) { 858 struct iwl_fw_ini_conf_set_tlv *config_list = (void *)node->tlv.data; 859 u32 count, address, value; 860 u32 len = (le32_to_cpu(node->tlv.length) - sizeof(*config_list)) / 8; 861 u32 type = le32_to_cpu(config_list->set_type); 862 u32 offset = le32_to_cpu(config_list->addr_offset); 863 864 switch (type) { 865 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_PERIPHERY_MAC: { 866 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 867 IWL_DEBUG_FW(fwrt, "WRT: failed to get nic access\n"); 868 IWL_DEBUG_FW(fwrt, "WRT: skipping MAC PERIPHERY config\n"); 869 continue; 870 } 871 IWL_DEBUG_FW(fwrt, "WRT: MAC PERIPHERY config len: len %u\n", len); 872 for (count = 0; count < len; count++) { 873 address = le32_to_cpu(config_list->addr_val[count].address); 874 value = le32_to_cpu(config_list->addr_val[count].value); 875 iwl_trans_write_prph(fwrt->trans, address + offset, value); 876 } 877 iwl_trans_release_nic_access(fwrt->trans); 878 break; 879 } 880 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_MEMORY: { 881 for (count = 0; count < len; count++) { 882 address = le32_to_cpu(config_list->addr_val[count].address); 883 value = le32_to_cpu(config_list->addr_val[count].value); 884 iwl_trans_write_mem32(fwrt->trans, address + offset, value); 885 IWL_DEBUG_FW(fwrt, "WRT: DEV_MEM: count %u, add: %u val: %u\n", 886 count, address, value); 887 } 888 break; 889 } 890 case IWL_FW_INI_CONFIG_SET_TYPE_CSR: { 891 for (count = 0; count < len; count++) { 892 address = le32_to_cpu(config_list->addr_val[count].address); 893 value = le32_to_cpu(config_list->addr_val[count].value); 894 iwl_write32(fwrt->trans, address + offset, value); 895 IWL_DEBUG_FW(fwrt, "WRT: CSR: count %u, add: %u val: %u\n", 896 count, address, value); 897 } 898 break; 899 } 900 case IWL_FW_INI_CONFIG_SET_TYPE_DBGC_DRAM_ADDR: { 901 struct iwl_dbgc1_info dram_info = {}; 902 struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0]; 903 __le64 dram_base_addr; 904 __le32 dram_size; 905 u64 dram_addr; 906 u32 ret; 907 908 if (!frags) 909 break; 910 911 dram_base_addr = cpu_to_le64(frags->physical); 912 dram_size = cpu_to_le32(frags->size); 913 dram_addr = le64_to_cpu(dram_base_addr); 914 915 IWL_DEBUG_FW(fwrt, "WRT: dram_base_addr 0x%016llx, dram_size 0x%x\n", 916 dram_base_addr, dram_size); 917 IWL_DEBUG_FW(fwrt, "WRT: config_list->addr_offset: %u\n", 918 le32_to_cpu(config_list->addr_offset)); 919 for (count = 0; count < len; count++) { 920 address = le32_to_cpu(config_list->addr_val[count].address); 921 dram_info.dbgc1_add_lsb = 922 cpu_to_le32((dram_addr & 0x00000000FFFFFFFFULL) + 0x400); 923 dram_info.dbgc1_add_msb = 924 cpu_to_le32((dram_addr & 0xFFFFFFFF00000000ULL) >> 32); 925 dram_info.dbgc1_size = cpu_to_le32(le32_to_cpu(dram_size) - 0x400); 926 ret = iwl_trans_write_mem(fwrt->trans, 927 address + offset, &dram_info, 4); 928 if (ret) { 929 IWL_ERR(fwrt, "Failed to write dram_info to HW_SMEM\n"); 930 break; 931 } 932 } 933 break; 934 } 935 case IWL_FW_INI_CONFIG_SET_TYPE_PERIPH_SCRATCH_HWM: { 936 u32 debug_token_config = 937 le32_to_cpu(config_list->addr_val[0].value); 938 939 IWL_DEBUG_FW(fwrt, "WRT: Setting HWM debug token config: %u\n", 940 debug_token_config); 941 fwrt->trans->dbg.ucode_preset = debug_token_config; 942 break; 943 } 944 default: 945 break; 946 } 947 } 948} 949 950static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t) 951{ 952 struct iwl_dbg_tlv_timer_node *timer_node = 953 from_timer(timer_node, t, timer); 954 struct iwl_fwrt_dump_data dump_data = { 955 .trig = (void *)timer_node->tlv->data, 956 }; 957 int ret; 958 959 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data, false); 960 if (!ret || ret == -EBUSY) { 961 u32 occur = le32_to_cpu(dump_data.trig->occurrences); 962 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]); 963 964 if (!occur) 965 return; 966 967 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval)); 968 } 969} 970 971static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt) 972{ 973 struct iwl_dbg_tlv_node *node; 974 struct list_head *trig_list = 975 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list; 976 977 list_for_each_entry(node, trig_list, list) { 978 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data; 979 struct iwl_dbg_tlv_timer_node *timer_node; 980 u32 occur = le32_to_cpu(trig->occurrences), collect_interval; 981 u32 min_interval = 100; 982 983 if (!occur) 984 continue; 985 986 /* make sure there is at least one dword of data for the 987 * interval value 988 */ 989 if (le32_to_cpu(node->tlv.length) < 990 sizeof(*trig) + sizeof(__le32)) { 991 IWL_ERR(fwrt, 992 "WRT: Invalid periodic trigger data was not given\n"); 993 continue; 994 } 995 996 if (le32_to_cpu(trig->data[0]) < min_interval) { 997 IWL_WARN(fwrt, 998 "WRT: Override min interval from %u to %u msec\n", 999 le32_to_cpu(trig->data[0]), min_interval); 1000 trig->data[0] = cpu_to_le32(min_interval); 1001 } 1002 1003 collect_interval = le32_to_cpu(trig->data[0]); 1004 1005 timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL); 1006 if (!timer_node) { 1007 IWL_ERR(fwrt, 1008 "WRT: Failed to allocate periodic trigger\n"); 1009 continue; 1010 } 1011 1012 timer_node->fwrt = fwrt; 1013 timer_node->tlv = &node->tlv; 1014 timer_setup(&timer_node->timer, 1015 iwl_dbg_tlv_periodic_trig_handler, 0); 1016 1017 list_add_tail(&timer_node->list, 1018 &fwrt->trans->dbg.periodic_trig_list); 1019 1020 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n"); 1021 1022 mod_timer(&timer_node->timer, 1023 jiffies + msecs_to_jiffies(collect_interval)); 1024 } 1025} 1026 1027static bool is_trig_data_contained(const struct iwl_ucode_tlv *new, 1028 const struct iwl_ucode_tlv *old) 1029{ 1030 const struct iwl_fw_ini_trigger_tlv *new_trig = (const void *)new->data; 1031 const struct iwl_fw_ini_trigger_tlv *old_trig = (const void *)old->data; 1032 const __le32 *new_data = new_trig->data, *old_data = old_trig->data; 1033 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data); 1034 u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data); 1035 int i, j; 1036 1037 for (i = 0; i < new_dwords_num; i++) { 1038 bool match = false; 1039 1040 for (j = 0; j < old_dwords_num; j++) { 1041 if (new_data[i] == old_data[j]) { 1042 match = true; 1043 break; 1044 } 1045 } 1046 if (!match) 1047 return false; 1048 } 1049 1050 return true; 1051} 1052 1053static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt, 1054 struct iwl_ucode_tlv *trig_tlv, 1055 struct iwl_dbg_tlv_node *node) 1056{ 1057 struct iwl_ucode_tlv *node_tlv = &node->tlv; 1058 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data; 1059 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 1060 u32 policy = le32_to_cpu(trig->apply_policy); 1061 u32 size = le32_to_cpu(trig_tlv->length); 1062 u32 trig_data_len = size - sizeof(*trig); 1063 u32 offset = 0; 1064 1065 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) { 1066 u32 data_len = le32_to_cpu(node_tlv->length) - 1067 sizeof(*node_trig); 1068 1069 IWL_DEBUG_FW(fwrt, 1070 "WRT: Appending trigger data (time point %u)\n", 1071 le32_to_cpu(trig->time_point)); 1072 1073 offset += data_len; 1074 size += data_len; 1075 } else { 1076 IWL_DEBUG_FW(fwrt, 1077 "WRT: Overriding trigger data (time point %u)\n", 1078 le32_to_cpu(trig->time_point)); 1079 } 1080 1081 if (size != le32_to_cpu(node_tlv->length)) { 1082 struct list_head *prev = node->list.prev; 1083 struct iwl_dbg_tlv_node *tmp; 1084 1085 list_del(&node->list); 1086 1087 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL); 1088 if (!tmp) { 1089 IWL_WARN(fwrt, 1090 "WRT: No memory to override trigger (time point %u)\n", 1091 le32_to_cpu(trig->time_point)); 1092 1093 list_add(&node->list, prev); 1094 1095 return -ENOMEM; 1096 } 1097 1098 list_add(&tmp->list, prev); 1099 node_tlv = &tmp->tlv; 1100 node_trig = (void *)node_tlv->data; 1101 } 1102 1103 memcpy((u8 *)node_trig->data + offset, trig->data, trig_data_len); 1104 node_tlv->length = cpu_to_le32(size); 1105 1106 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) { 1107 IWL_DEBUG_FW(fwrt, 1108 "WRT: Overriding trigger configuration (time point %u)\n", 1109 le32_to_cpu(trig->time_point)); 1110 1111 /* the first 11 dwords are configuration related */ 1112 memcpy(node_trig, trig, sizeof(__le32) * 11); 1113 } 1114 1115 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) { 1116 IWL_DEBUG_FW(fwrt, 1117 "WRT: Overriding trigger regions (time point %u)\n", 1118 le32_to_cpu(trig->time_point)); 1119 1120 node_trig->regions_mask = trig->regions_mask; 1121 } else { 1122 IWL_DEBUG_FW(fwrt, 1123 "WRT: Appending trigger regions (time point %u)\n", 1124 le32_to_cpu(trig->time_point)); 1125 1126 node_trig->regions_mask |= trig->regions_mask; 1127 } 1128 1129 return 0; 1130} 1131 1132static int 1133iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt, 1134 struct list_head *trig_list, 1135 struct iwl_ucode_tlv *trig_tlv) 1136{ 1137 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 1138 struct iwl_dbg_tlv_node *node, *match = NULL; 1139 u32 policy = le32_to_cpu(trig->apply_policy); 1140 1141 list_for_each_entry(node, trig_list, list) { 1142 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT)) 1143 break; 1144 1145 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) || 1146 is_trig_data_contained(trig_tlv, &node->tlv)) { 1147 match = node; 1148 break; 1149 } 1150 } 1151 1152 if (!match) { 1153 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n", 1154 le32_to_cpu(trig->time_point)); 1155 return iwl_dbg_tlv_add(trig_tlv, trig_list); 1156 } 1157 1158 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match); 1159} 1160 1161static void 1162iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt, 1163 struct iwl_dbg_tlv_time_point_data *tp) 1164{ 1165 struct iwl_dbg_tlv_node *node; 1166 struct list_head *trig_list = &tp->trig_list; 1167 struct list_head *active_trig_list = &tp->active_trig_list; 1168 1169 list_for_each_entry(node, trig_list, list) { 1170 struct iwl_ucode_tlv *tlv = &node->tlv; 1171 1172 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv); 1173 } 1174} 1175 1176static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt, 1177 struct iwl_fwrt_dump_data *dump_data, 1178 union iwl_dbg_tlv_tp_data *tp_data, 1179 u32 trig_data) 1180{ 1181 struct iwl_rx_packet *pkt = tp_data->fw_pkt; 1182 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data; 1183 1184 if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd && 1185 pkt->hdr.group_id == wanted_hdr->group_id)) { 1186 struct iwl_rx_packet *fw_pkt = 1187 kmemdup(pkt, 1188 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt), 1189 GFP_ATOMIC); 1190 1191 if (!fw_pkt) 1192 return false; 1193 1194 dump_data->fw_pkt = fw_pkt; 1195 1196 return true; 1197 } 1198 1199 return false; 1200} 1201 1202static int 1203iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, bool sync, 1204 struct list_head *active_trig_list, 1205 union iwl_dbg_tlv_tp_data *tp_data, 1206 bool (*data_check)(struct iwl_fw_runtime *fwrt, 1207 struct iwl_fwrt_dump_data *dump_data, 1208 union iwl_dbg_tlv_tp_data *tp_data, 1209 u32 trig_data)) 1210{ 1211 struct iwl_dbg_tlv_node *node; 1212 1213 list_for_each_entry(node, active_trig_list, list) { 1214 struct iwl_fwrt_dump_data dump_data = { 1215 .trig = (void *)node->tlv.data, 1216 }; 1217 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig, 1218 data); 1219 int ret, i; 1220 u32 tp = le32_to_cpu(dump_data.trig->time_point); 1221 1222 1223 if (!num_data) { 1224 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync); 1225 if (ret) 1226 return ret; 1227 } 1228 1229 for (i = 0; i < num_data; i++) { 1230 if (!data_check || 1231 data_check(fwrt, &dump_data, tp_data, 1232 le32_to_cpu(dump_data.trig->data[i]))) { 1233 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync); 1234 if (ret) 1235 return ret; 1236 1237 break; 1238 } 1239 } 1240 1241 fwrt->trans->dbg.restart_required = FALSE; 1242 IWL_DEBUG_FW(fwrt, "WRT: tp %d, reset_fw %d\n", 1243 tp, dump_data.trig->reset_fw); 1244 IWL_DEBUG_FW(fwrt, 1245 "WRT: restart_required %d, last_tp_resetfw %d\n", 1246 fwrt->trans->dbg.restart_required, 1247 fwrt->trans->dbg.last_tp_resetfw); 1248 1249 if (fwrt->trans->trans_cfg->device_family == 1250 IWL_DEVICE_FAMILY_9000) { 1251 fwrt->trans->dbg.restart_required = TRUE; 1252 } else if (tp == IWL_FW_INI_TIME_POINT_FW_ASSERT && 1253 fwrt->trans->dbg.last_tp_resetfw == 1254 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) { 1255 fwrt->trans->dbg.restart_required = FALSE; 1256 fwrt->trans->dbg.last_tp_resetfw = 0xFF; 1257 IWL_DEBUG_FW(fwrt, "WRT: FW_ASSERT due to reset_fw_mode-no restart\n"); 1258 } else if (le32_to_cpu(dump_data.trig->reset_fw) == 1259 IWL_FW_INI_RESET_FW_MODE_STOP_AND_RELOAD_FW) { 1260 IWL_DEBUG_FW(fwrt, "WRT: stop and reload firmware\n"); 1261 fwrt->trans->dbg.restart_required = TRUE; 1262 } else if (le32_to_cpu(dump_data.trig->reset_fw) == 1263 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) { 1264 IWL_DEBUG_FW(fwrt, 1265 "WRT: stop only and no reload firmware\n"); 1266 fwrt->trans->dbg.restart_required = FALSE; 1267 fwrt->trans->dbg.last_tp_resetfw = 1268 le32_to_cpu(dump_data.trig->reset_fw); 1269 } else if (le32_to_cpu(dump_data.trig->reset_fw) == 1270 IWL_FW_INI_RESET_FW_MODE_NOTHING) { 1271 IWL_DEBUG_FW(fwrt, 1272 "WRT: nothing need to be done after debug collection\n"); 1273 } else { 1274 IWL_ERR(fwrt, "WRT: wrong resetfw %d\n", 1275 le32_to_cpu(dump_data.trig->reset_fw)); 1276 } 1277 } 1278 return 0; 1279} 1280 1281static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt) 1282{ 1283 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest; 1284 int ret, i; 1285 u32 failed_alloc = 0; 1286 1287 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) { 1288 IWL_DEBUG_FW(fwrt, 1289 "WRT: Generating active triggers list, domain 0x%x\n", 1290 fwrt->trans->dbg.domains_bitmap); 1291 1292 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) { 1293 struct iwl_dbg_tlv_time_point_data *tp = 1294 &fwrt->trans->dbg.time_point[i]; 1295 1296 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp); 1297 } 1298 } else if (*ini_dest != IWL_FW_INI_LOCATION_DRAM_PATH) { 1299 /* For DRAM, go through the loop below to clear all the buffers 1300 * properly on restart, otherwise garbage may be left there and 1301 * leak into new debug dumps. 1302 */ 1303 return; 1304 } 1305 1306 *ini_dest = IWL_FW_INI_LOCATION_INVALID; 1307 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 1308 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 1309 &fwrt->trans->dbg.fw_mon_cfg[i]; 1310 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location); 1311 1312 if (dest == IWL_FW_INI_LOCATION_INVALID) { 1313 failed_alloc |= BIT(i); 1314 continue; 1315 } 1316 1317 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) 1318 *ini_dest = dest; 1319 1320 if (dest != *ini_dest) 1321 continue; 1322 1323 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i); 1324 1325 if (ret) { 1326 IWL_WARN(fwrt, 1327 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n", 1328 i, ret); 1329 failed_alloc |= BIT(i); 1330 } 1331 } 1332 1333 if (!failed_alloc) 1334 return; 1335 1336 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) { 1337 struct iwl_fw_ini_region_tlv *reg; 1338 struct iwl_ucode_tlv **active_reg = 1339 &fwrt->trans->dbg.active_regions[i]; 1340 u32 reg_type; 1341 1342 if (!*active_reg) { 1343 fwrt->trans->dbg.unsupported_region_msk |= BIT(i); 1344 continue; 1345 } 1346 1347 reg = (void *)(*active_reg)->data; 1348 reg_type = reg->type; 1349 1350 if (reg_type != IWL_FW_INI_REGION_DRAM_BUFFER || 1351 !(BIT(le32_to_cpu(reg->dram_alloc_id)) & failed_alloc)) 1352 continue; 1353 1354 IWL_DEBUG_FW(fwrt, 1355 "WRT: removing allocation id %d from region id %d\n", 1356 le32_to_cpu(reg->dram_alloc_id), i); 1357 1358 failed_alloc &= ~BIT(le32_to_cpu(reg->dram_alloc_id)); 1359 fwrt->trans->dbg.unsupported_region_msk |= BIT(i); 1360 1361 kfree(*active_reg); 1362 *active_reg = NULL; 1363 } 1364} 1365 1366void _iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt, 1367 enum iwl_fw_ini_time_point tp_id, 1368 union iwl_dbg_tlv_tp_data *tp_data, 1369 bool sync) 1370{ 1371 struct list_head *hcmd_list, *trig_list, *conf_list; 1372 1373 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 1374 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 1375 tp_id >= IWL_FW_INI_TIME_POINT_NUM) 1376 return; 1377 1378 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list; 1379 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list; 1380 conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list; 1381 1382 switch (tp_id) { 1383 case IWL_FW_INI_TIME_POINT_EARLY: 1384 iwl_dbg_tlv_init_cfg(fwrt); 1385 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1386 iwl_dbg_tlv_update_drams(fwrt); 1387 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1388 break; 1389 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE: 1390 iwl_dbg_tlv_apply_buffers(fwrt); 1391 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1392 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1393 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1394 break; 1395 case IWL_FW_INI_TIME_POINT_PERIODIC: 1396 iwl_dbg_tlv_set_periodic_trigs(fwrt); 1397 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1398 break; 1399 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF: 1400 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS: 1401 case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION: 1402 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1403 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1404 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, 1405 iwl_dbg_tlv_check_fw_pkt); 1406 break; 1407 default: 1408 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1409 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1410 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1411 break; 1412 } 1413} 1414IWL_EXPORT_SYMBOL(_iwl_dbg_tlv_time_point); 1415