1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* 3 * Copyright (C) 2018, 2020-2022 Intel Corporation 4 */ 5#ifndef __iwl_context_info_file_gen3_h__ 6#define __iwl_context_info_file_gen3_h__ 7 8#include "iwl-context-info.h" 9 10#define CSR_CTXT_INFO_BOOT_CTRL 0x0 11#define CSR_CTXT_INFO_ADDR 0x118 12#define CSR_IML_DATA_ADDR 0x120 13#define CSR_IML_SIZE_ADDR 0x128 14#define CSR_IML_RESP_ADDR 0x12c 15 16#define UNFRAGMENTED_PNVM_PAYLOADS_NUMBER 2 17 18/* Set bit for enabling automatic function boot */ 19#define CSR_AUTO_FUNC_BOOT_ENA BIT(1) 20/* Set bit for initiating function boot */ 21#define CSR_AUTO_FUNC_INIT BIT(7) 22 23/** 24 * enum iwl_prph_scratch_mtr_format - tfd size configuration 25 * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd 26 * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd 27 * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd 28 * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd 29 */ 30enum iwl_prph_scratch_mtr_format { 31 IWL_PRPH_MTR_FORMAT_16B = 0x0, 32 IWL_PRPH_MTR_FORMAT_32B = 0x40000, 33 IWL_PRPH_MTR_FORMAT_64B = 0x80000, 34 IWL_PRPH_MTR_FORMAT_256B = 0xC0000, 35}; 36 37/** 38 * enum iwl_prph_scratch_flags - PRPH scratch control flags 39 * @IWL_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug 40 * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf 41 * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated 42 * in hwm config. 43 * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM 44 * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for 45 * multicomm. 46 * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW 47 * @IWL_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K) 48 * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for 49 * completion descriptor, 1 for responses (legacy) 50 * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd. 51 * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit, 52 * 3: 256 bit. 53 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored 54 * by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K 55 * appropriately; use the below values for this. 56 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size 57 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size 58 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size 59 */ 60enum iwl_prph_scratch_flags { 61 IWL_PRPH_SCRATCH_IMR_DEBUG_EN = BIT(1), 62 IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4), 63 IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8), 64 IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9), 65 IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER = BIT(10), 66 IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF = BIT(11), 67 IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16), 68 IWL_PRPH_SCRATCH_MTR_MODE = BIT(17), 69 IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19), 70 IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK = 0xf << 20, 71 IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K = 8 << 20, 72 IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K = 9 << 20, 73 IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K = 10 << 20, 74}; 75 76/* 77 * struct iwl_prph_scratch_version - version structure 78 * @mac_id: SKU and revision id 79 * @version: prph scratch information version id 80 * @size: the size of the context information in DWs 81 * @reserved: reserved 82 */ 83struct iwl_prph_scratch_version { 84 __le16 mac_id; 85 __le16 version; 86 __le16 size; 87 __le16 reserved; 88} __packed; /* PERIPH_SCRATCH_VERSION_S */ 89 90/* 91 * struct iwl_prph_scratch_control - control structure 92 * @control_flags: context information flags see &enum iwl_prph_scratch_flags 93 * @reserved: reserved 94 */ 95struct iwl_prph_scratch_control { 96 __le32 control_flags; 97 __le32 reserved; 98} __packed; /* PERIPH_SCRATCH_CONTROL_S */ 99 100/* 101 * struct iwl_prph_scratch_pnvm_cfg - PNVM scratch 102 * @pnvm_base_addr: PNVM start address 103 * @pnvm_size: the size of the PNVM image in bytes 104 * @reserved: reserved 105 */ 106struct iwl_prph_scratch_pnvm_cfg { 107 __le64 pnvm_base_addr; 108 __le32 pnvm_size; 109 __le32 reserved; 110} __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */ 111 112/** 113 * struct iwl_prph_scrath_mem_desc_addr_array 114 * @mem_descs: array of dram addresses. 115 * Each address is the beggining of a pnvm payload. 116 */ 117struct iwl_prph_scrath_mem_desc_addr_array { 118 __le64 mem_descs[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 119} __packed; /* PERIPH_SCRATCH_MEM_DESC_ADDR_ARRAY_S_VER_1 */ 120/* 121 * struct iwl_prph_scratch_hwm_cfg - hwm config 122 * @hwm_base_addr: hwm start address 123 * @hwm_size: hwm size in DWs 124 * @debug_token_config: debug preset 125 */ 126struct iwl_prph_scratch_hwm_cfg { 127 __le64 hwm_base_addr; 128 __le32 hwm_size; 129 __le32 debug_token_config; 130} __packed; /* PERIPH_SCRATCH_HWM_CFG_S */ 131 132/* 133 * struct iwl_prph_scratch_rbd_cfg - RBDs configuration 134 * @free_rbd_addr: default queue free RB CB base address 135 * @reserved: reserved 136 */ 137struct iwl_prph_scratch_rbd_cfg { 138 __le64 free_rbd_addr; 139 __le32 reserved; 140} __packed; /* PERIPH_SCRATCH_RBD_CFG_S */ 141 142/* 143 * struct iwl_prph_scratch_uefi_cfg - prph scratch reduce power table 144 * @base_addr: reduce power table address 145 * @size: the size of the entire power table image 146 */ 147struct iwl_prph_scratch_uefi_cfg { 148 __le64 base_addr; 149 __le32 size; 150 __le32 reserved; 151} __packed; /* PERIPH_SCRATCH_UEFI_CFG_S */ 152 153/* 154 * struct iwl_prph_scratch_step_cfg - prph scratch step configuration 155 * @mbx_addr_0: [0:7] revision, 156 * [8:15] cnvi_to_cnvr length, 157 * [16:23] cnvr_to_cnvi channel length, 158 * [24:31] radio1 reserved 159 * @mbx_addr_1: [0:7] radio2 reserved 160 */ 161 162struct iwl_prph_scratch_step_cfg { 163 __le32 mbx_addr_0; 164 __le32 mbx_addr_1; 165} __packed; 166 167/* 168 * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config 169 * @version: version information of context info and HW 170 * @control: control flags of FH configurations 171 * @pnvm_cfg: ror configuration 172 * @hwm_cfg: hwm configuration 173 * @rbd_cfg: default RX queue configuration 174 * @step_cfg: step configuration 175 */ 176struct iwl_prph_scratch_ctrl_cfg { 177 struct iwl_prph_scratch_version version; 178 struct iwl_prph_scratch_control control; 179 struct iwl_prph_scratch_pnvm_cfg pnvm_cfg; 180 struct iwl_prph_scratch_hwm_cfg hwm_cfg; 181 struct iwl_prph_scratch_rbd_cfg rbd_cfg; 182 struct iwl_prph_scratch_uefi_cfg reduce_power_cfg; 183 struct iwl_prph_scratch_step_cfg step_cfg; 184} __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */ 185 186/* 187 * struct iwl_prph_scratch - peripheral scratch mapping 188 * @ctrl_cfg: control and configuration of prph scratch 189 * @dram: firmware images addresses in DRAM 190 * @reserved: reserved 191 */ 192struct iwl_prph_scratch { 193 struct iwl_prph_scratch_ctrl_cfg ctrl_cfg; 194 __le32 reserved[10]; 195 struct iwl_context_info_dram dram; 196} __packed; /* PERIPH_SCRATCH_S */ 197 198/* 199 * struct iwl_prph_info - peripheral information 200 * @boot_stage_mirror: reflects the value in the Boot Stage CSR register 201 * @ipc_status_mirror: reflects the value in the IPC Status CSR register 202 * @sleep_notif: indicates the peripheral sleep status 203 * @reserved: reserved 204 */ 205struct iwl_prph_info { 206 __le32 boot_stage_mirror; 207 __le32 ipc_status_mirror; 208 __le32 sleep_notif; 209 __le32 reserved; 210} __packed; /* PERIPH_INFO_S */ 211 212/* 213 * struct iwl_context_info_gen3 - device INIT configuration 214 * @version: version of the context information 215 * @size: size of context information in DWs 216 * @config: context in which the peripheral would execute - a subset of 217 * capability csr register published by the peripheral 218 * @prph_info_base_addr: the peripheral information structure start address 219 * @cr_head_idx_arr_base_addr: the completion ring head index array 220 * start address 221 * @tr_tail_idx_arr_base_addr: the transfer ring tail index array 222 * start address 223 * @cr_tail_idx_arr_base_addr: the completion ring tail index array 224 * start address 225 * @tr_head_idx_arr_base_addr: the transfer ring head index array 226 * start address 227 * @cr_idx_arr_size: number of entries in the completion ring index array 228 * @tr_idx_arr_size: number of entries in the transfer ring index array 229 * @mtr_base_addr: the message transfer ring start address 230 * @mcr_base_addr: the message completion ring start address 231 * @mtr_size: number of entries which the message transfer ring can hold 232 * @mcr_size: number of entries which the message completion ring can hold 233 * @mtr_doorbell_vec: the doorbell vector associated with the message 234 * transfer ring 235 * @mcr_doorbell_vec: the doorbell vector associated with the message 236 * completion ring 237 * @mtr_msi_vec: the MSI which shall be generated by the peripheral after 238 * completing a transfer descriptor in the message transfer ring 239 * @mcr_msi_vec: the MSI which shall be generated by the peripheral after 240 * completing a completion descriptor in the message completion ring 241 * @mtr_opt_header_size: the size of the optional header in the transfer 242 * descriptor associated with the message transfer ring in DWs 243 * @mtr_opt_footer_size: the size of the optional footer in the transfer 244 * descriptor associated with the message transfer ring in DWs 245 * @mcr_opt_header_size: the size of the optional header in the completion 246 * descriptor associated with the message completion ring in DWs 247 * @mcr_opt_footer_size: the size of the optional footer in the completion 248 * descriptor associated with the message completion ring in DWs 249 * @msg_rings_ctrl_flags: message rings control flags 250 * @prph_info_msi_vec: the MSI which shall be generated by the peripheral 251 * after updating the Peripheral Information structure 252 * @prph_scratch_base_addr: the peripheral scratch structure start address 253 * @prph_scratch_size: the size of the peripheral scratch structure in DWs 254 * @reserved: reserved 255 */ 256struct iwl_context_info_gen3 { 257 __le16 version; 258 __le16 size; 259 __le32 config; 260 __le64 prph_info_base_addr; 261 __le64 cr_head_idx_arr_base_addr; 262 __le64 tr_tail_idx_arr_base_addr; 263 __le64 cr_tail_idx_arr_base_addr; 264 __le64 tr_head_idx_arr_base_addr; 265 __le16 cr_idx_arr_size; 266 __le16 tr_idx_arr_size; 267 __le64 mtr_base_addr; 268 __le64 mcr_base_addr; 269 __le16 mtr_size; 270 __le16 mcr_size; 271 __le16 mtr_doorbell_vec; 272 __le16 mcr_doorbell_vec; 273 __le16 mtr_msi_vec; 274 __le16 mcr_msi_vec; 275 u8 mtr_opt_header_size; 276 u8 mtr_opt_footer_size; 277 u8 mcr_opt_header_size; 278 u8 mcr_opt_footer_size; 279 __le16 msg_rings_ctrl_flags; 280 __le16 prph_info_msi_vec; 281 __le64 prph_scratch_base_addr; 282 __le32 prph_scratch_size; 283 __le32 reserved; 284} __packed; /* IPC_CONTEXT_INFO_S */ 285 286int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 287 const struct fw_img *fw); 288void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive); 289 290int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans, 291 const struct iwl_pnvm_image *pnvm_payloads, 292 const struct iwl_ucode_capabilities *capa); 293void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 294 const struct iwl_ucode_capabilities *capa); 295int 296iwl_trans_pcie_ctx_info_gen3_load_reduce_power(struct iwl_trans *trans, 297 const struct iwl_pnvm_image *payloads, 298 const struct iwl_ucode_capabilities *capa); 299void 300iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans, 301 const struct iwl_ucode_capabilities *capa); 302int iwl_trans_pcie_ctx_info_gen3_set_step(struct iwl_trans *trans, 303 u32 mbx_addr_0_step, u32 mbx_addr_1_step); 304#endif /* __iwl_context_info_file_gen3_h__ */ 305