1/* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/dma-mapping.h> 18#include "ath9k.h" 19#include "ar9003_mac.h" 20 21#define BITS_PER_BYTE 8 22#define OFDM_PLCP_BITS 22 23#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) 24#define L_STF 8 25#define L_LTF 8 26#define L_SIG 4 27#define HT_SIG 8 28#define HT_STF 4 29#define HT_LTF(_ns) (4 * (_ns)) 30#define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ 31#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ 32#define TIME_SYMBOLS(t) ((t) >> 2) 33#define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18) 34#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) 35#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) 36 37/* Shifts in ar5008_phy.c and ar9003_phy.c are equal for all revisions */ 38#define ATH9K_PWRTBL_11NA_OFDM_SHIFT 0 39#define ATH9K_PWRTBL_11NG_OFDM_SHIFT 4 40#define ATH9K_PWRTBL_11NA_HT_SHIFT 8 41#define ATH9K_PWRTBL_11NG_HT_SHIFT 12 42 43 44static u16 bits_per_symbol[][2] = { 45 /* 20MHz 40MHz */ 46 { 26, 54 }, /* 0: BPSK */ 47 { 52, 108 }, /* 1: QPSK 1/2 */ 48 { 78, 162 }, /* 2: QPSK 3/4 */ 49 { 104, 216 }, /* 3: 16-QAM 1/2 */ 50 { 156, 324 }, /* 4: 16-QAM 3/4 */ 51 { 208, 432 }, /* 5: 64-QAM 2/3 */ 52 { 234, 486 }, /* 6: 64-QAM 3/4 */ 53 { 260, 540 }, /* 7: 64-QAM 5/6 */ 54}; 55 56static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 57 struct ath_atx_tid *tid, struct sk_buff *skb); 58static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 59 int tx_flags, struct ath_txq *txq, 60 struct ieee80211_sta *sta); 61static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 62 struct ath_txq *txq, struct list_head *bf_q, 63 struct ieee80211_sta *sta, 64 struct ath_tx_status *ts, int txok); 65static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 66 struct list_head *head, bool internal); 67static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 68 struct ath_tx_status *ts, int nframes, int nbad, 69 int txok); 70static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 71 struct ath_buf *bf); 72static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 73 struct ath_txq *txq, 74 struct ath_atx_tid *tid, 75 struct sk_buff *skb); 76static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb, 77 struct ath_tx_control *txctl); 78 79enum { 80 MCS_HT20, 81 MCS_HT20_SGI, 82 MCS_HT40, 83 MCS_HT40_SGI, 84}; 85 86/*********************/ 87/* Aggregation logic */ 88/*********************/ 89 90static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb) 91{ 92 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 93 struct ieee80211_sta *sta = info->status.status_driver_data[0]; 94 95 if (info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS | 96 IEEE80211_TX_STATUS_EOSP)) { 97 ieee80211_tx_status(hw, skb); 98 return; 99 } 100 101 if (sta) 102 ieee80211_tx_status_noskb(hw, sta, info); 103 104 dev_kfree_skb(skb); 105} 106 107void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq) 108 __releases(&txq->axq_lock) 109{ 110 struct ieee80211_hw *hw = sc->hw; 111 struct sk_buff_head q; 112 struct sk_buff *skb; 113 114 __skb_queue_head_init(&q); 115 skb_queue_splice_init(&txq->complete_q, &q); 116 spin_unlock_bh(&txq->axq_lock); 117 118 while ((skb = __skb_dequeue(&q))) 119 ath_tx_status(hw, skb); 120} 121 122void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 123{ 124 struct ieee80211_txq *queue = 125 container_of((void *)tid, struct ieee80211_txq, drv_priv); 126 127 ieee80211_schedule_txq(sc->hw, queue); 128} 129 130void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue) 131{ 132 struct ath_softc *sc = hw->priv; 133 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 134 struct ath_atx_tid *tid = (struct ath_atx_tid *) queue->drv_priv; 135 struct ath_txq *txq = tid->txq; 136 137 ath_dbg(common, QUEUE, "Waking TX queue: %pM (%d)\n", 138 queue->sta ? queue->sta->addr : queue->vif->addr, 139 tid->tidno); 140 141 ath_txq_lock(sc, txq); 142 ath_txq_schedule(sc, txq); 143 ath_txq_unlock(sc, txq); 144} 145 146static struct ath_frame_info *get_frame_info(struct sk_buff *skb) 147{ 148 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 149 BUILD_BUG_ON(sizeof(struct ath_frame_info) > 150 sizeof(tx_info->status.status_driver_data)); 151 return (struct ath_frame_info *) &tx_info->status.status_driver_data[0]; 152} 153 154static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno) 155{ 156 if (!tid->an->sta) 157 return; 158 159 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno, 160 seqno << IEEE80211_SEQ_SEQ_SHIFT); 161} 162 163static bool ath_merge_ratetbl(struct ieee80211_sta *sta, struct ath_buf *bf, 164 struct ieee80211_tx_info *tx_info) 165{ 166 struct ieee80211_sta_rates *ratetbl; 167 u8 i; 168 169 if (!sta) 170 return false; 171 172 ratetbl = rcu_dereference(sta->rates); 173 if (!ratetbl) 174 return false; 175 176 if (tx_info->control.rates[0].idx < 0 || 177 tx_info->control.rates[0].count == 0) 178 { 179 i = 0; 180 } else { 181 bf->rates[0] = tx_info->control.rates[0]; 182 i = 1; 183 } 184 185 for ( ; i < IEEE80211_TX_MAX_RATES; i++) { 186 bf->rates[i].idx = ratetbl->rate[i].idx; 187 bf->rates[i].flags = ratetbl->rate[i].flags; 188 if (tx_info->control.use_rts) 189 bf->rates[i].count = ratetbl->rate[i].count_rts; 190 else if (tx_info->control.use_cts_prot) 191 bf->rates[i].count = ratetbl->rate[i].count_cts; 192 else 193 bf->rates[i].count = ratetbl->rate[i].count; 194 } 195 196 return true; 197} 198 199static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta, 200 struct ath_buf *bf) 201{ 202 struct ieee80211_tx_info *tx_info; 203 204 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 205 206 if (!ath_merge_ratetbl(sta, bf, tx_info)) 207 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates, 208 ARRAY_SIZE(bf->rates)); 209} 210 211static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq, 212 struct sk_buff *skb) 213{ 214 struct ath_frame_info *fi = get_frame_info(skb); 215 int q = fi->txq; 216 217 if (q < 0) 218 return; 219 220 txq = sc->tx.txq_map[q]; 221 if (WARN_ON(--txq->pending_frames < 0)) 222 txq->pending_frames = 0; 223 224} 225 226static struct ath_atx_tid * 227ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb) 228{ 229 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 230 return ATH_AN_2_TID(an, tidno); 231} 232 233static int 234ath_tid_pull(struct ath_atx_tid *tid, struct sk_buff **skbuf) 235{ 236 struct ieee80211_txq *txq = container_of((void*)tid, struct ieee80211_txq, drv_priv); 237 struct ath_softc *sc = tid->an->sc; 238 struct ieee80211_hw *hw = sc->hw; 239 struct ath_tx_control txctl = { 240 .txq = tid->txq, 241 .sta = tid->an->sta, 242 }; 243 struct sk_buff *skb; 244 struct ath_frame_info *fi; 245 int q, ret; 246 247 skb = ieee80211_tx_dequeue(hw, txq); 248 if (!skb) 249 return -ENOENT; 250 251 ret = ath_tx_prepare(hw, skb, &txctl); 252 if (ret) { 253 ieee80211_free_txskb(hw, skb); 254 return ret; 255 } 256 257 q = skb_get_queue_mapping(skb); 258 if (tid->txq == sc->tx.txq_map[q]) { 259 fi = get_frame_info(skb); 260 fi->txq = q; 261 ++tid->txq->pending_frames; 262 } 263 264 *skbuf = skb; 265 return 0; 266} 267 268static int ath_tid_dequeue(struct ath_atx_tid *tid, 269 struct sk_buff **skb) 270{ 271 int ret = 0; 272 *skb = __skb_dequeue(&tid->retry_q); 273 if (!*skb) 274 ret = ath_tid_pull(tid, skb); 275 276 return ret; 277} 278 279static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 280{ 281 struct ath_txq *txq = tid->txq; 282 struct sk_buff *skb; 283 struct ath_buf *bf; 284 struct list_head bf_head; 285 struct ath_tx_status ts; 286 struct ath_frame_info *fi; 287 bool sendbar = false; 288 289 INIT_LIST_HEAD(&bf_head); 290 291 memset(&ts, 0, sizeof(ts)); 292 293 while ((skb = __skb_dequeue(&tid->retry_q))) { 294 fi = get_frame_info(skb); 295 bf = fi->bf; 296 if (!bf) { 297 ath_txq_skb_done(sc, txq, skb); 298 ieee80211_free_txskb(sc->hw, skb); 299 continue; 300 } 301 302 if (fi->baw_tracked) { 303 ath_tx_update_baw(sc, tid, bf); 304 sendbar = true; 305 } 306 307 list_add_tail(&bf->list, &bf_head); 308 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); 309 } 310 311 if (sendbar) { 312 ath_txq_unlock(sc, txq); 313 ath_send_bar(tid, tid->seq_start); 314 ath_txq_lock(sc, txq); 315 } 316} 317 318static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 319 struct ath_buf *bf) 320{ 321 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 322 u16 seqno = bf->bf_state.seqno; 323 int index, cindex; 324 325 if (!fi->baw_tracked) 326 return; 327 328 index = ATH_BA_INDEX(tid->seq_start, seqno); 329 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 330 331 __clear_bit(cindex, tid->tx_buf); 332 333 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) { 334 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 335 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 336 if (tid->bar_index >= 0) 337 tid->bar_index--; 338 } 339} 340 341static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 342 struct ath_buf *bf) 343{ 344 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 345 u16 seqno = bf->bf_state.seqno; 346 int index, cindex; 347 348 if (fi->baw_tracked) 349 return; 350 351 index = ATH_BA_INDEX(tid->seq_start, seqno); 352 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 353 __set_bit(cindex, tid->tx_buf); 354 fi->baw_tracked = 1; 355 356 if (index >= ((tid->baw_tail - tid->baw_head) & 357 (ATH_TID_MAX_BUFS - 1))) { 358 tid->baw_tail = cindex; 359 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 360 } 361} 362 363static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, 364 struct ath_atx_tid *tid) 365 366{ 367 struct sk_buff *skb; 368 struct ath_buf *bf; 369 struct list_head bf_head; 370 struct ath_tx_status ts; 371 struct ath_frame_info *fi; 372 int ret; 373 374 memset(&ts, 0, sizeof(ts)); 375 INIT_LIST_HEAD(&bf_head); 376 377 while ((ret = ath_tid_dequeue(tid, &skb)) == 0) { 378 fi = get_frame_info(skb); 379 bf = fi->bf; 380 381 if (!bf) { 382 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL); 383 continue; 384 } 385 386 list_add_tail(&bf->list, &bf_head); 387 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); 388 } 389} 390 391static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, 392 struct sk_buff *skb, int count) 393{ 394 struct ath_frame_info *fi = get_frame_info(skb); 395 struct ath_buf *bf = fi->bf; 396 struct ieee80211_hdr *hdr; 397 int prev = fi->retries; 398 399 TX_STAT_INC(sc, txq->axq_qnum, a_retries); 400 fi->retries += count; 401 402 if (prev > 0) 403 return; 404 405 hdr = (struct ieee80211_hdr *)skb->data; 406 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); 407 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 408 sizeof(*hdr), DMA_TO_DEVICE); 409} 410 411static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) 412{ 413 struct ath_buf *bf = NULL; 414 415 spin_lock_bh(&sc->tx.txbuflock); 416 417 if (unlikely(list_empty(&sc->tx.txbuf))) { 418 spin_unlock_bh(&sc->tx.txbuflock); 419 return NULL; 420 } 421 422 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 423 list_del(&bf->list); 424 425 spin_unlock_bh(&sc->tx.txbuflock); 426 427 return bf; 428} 429 430static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf) 431{ 432 spin_lock_bh(&sc->tx.txbuflock); 433 list_add_tail(&bf->list, &sc->tx.txbuf); 434 spin_unlock_bh(&sc->tx.txbuflock); 435} 436 437static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) 438{ 439 struct ath_buf *tbf; 440 441 tbf = ath_tx_get_buffer(sc); 442 if (WARN_ON(!tbf)) 443 return NULL; 444 445 ATH_TXBUF_RESET(tbf); 446 447 tbf->bf_mpdu = bf->bf_mpdu; 448 tbf->bf_buf_addr = bf->bf_buf_addr; 449 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); 450 tbf->bf_state = bf->bf_state; 451 tbf->bf_state.stale = false; 452 453 return tbf; 454} 455 456static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf, 457 struct ath_tx_status *ts, int txok, 458 int *nframes, int *nbad) 459{ 460 u16 seq_st = 0; 461 u32 ba[WME_BA_BMP_SIZE >> 5]; 462 int ba_index; 463 int isaggr = 0; 464 465 *nbad = 0; 466 *nframes = 0; 467 468 isaggr = bf_isaggr(bf); 469 memset(ba, 0, WME_BA_BMP_SIZE >> 3); 470 471 if (isaggr) { 472 seq_st = ts->ts_seqnum; 473 memcpy(ba, &ts->ba, WME_BA_BMP_SIZE >> 3); 474 } 475 476 while (bf) { 477 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno); 478 479 (*nframes)++; 480 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) 481 (*nbad)++; 482 483 bf = bf->bf_next; 484 } 485} 486 487 488static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, 489 struct ath_buf *bf, struct list_head *bf_q, 490 struct ieee80211_sta *sta, 491 struct ath_atx_tid *tid, 492 struct ath_tx_status *ts, int txok) 493{ 494 struct ath_node *an = NULL; 495 struct sk_buff *skb; 496 struct ieee80211_tx_info *tx_info; 497 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 498 struct list_head bf_head; 499 struct sk_buff_head bf_pending; 500 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; 501 u32 ba[WME_BA_BMP_SIZE >> 5]; 502 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; 503 bool rc_update = true, isba; 504 struct ieee80211_tx_rate rates[4]; 505 struct ath_frame_info *fi; 506 int nframes; 507 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 508 int i, retries; 509 int bar_index = -1; 510 511 skb = bf->bf_mpdu; 512 tx_info = IEEE80211_SKB_CB(skb); 513 514 memcpy(rates, bf->rates, sizeof(rates)); 515 516 retries = ts->ts_longretry + 1; 517 for (i = 0; i < ts->ts_rateindex; i++) 518 retries += rates[i].count; 519 520 if (!sta) { 521 INIT_LIST_HEAD(&bf_head); 522 while (bf) { 523 bf_next = bf->bf_next; 524 525 if (!bf->bf_state.stale || bf_next != NULL) 526 list_move_tail(&bf->list, &bf_head); 527 528 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0); 529 530 bf = bf_next; 531 } 532 return; 533 } 534 535 an = (struct ath_node *)sta->drv_priv; 536 seq_first = tid->seq_start; 537 isba = ts->ts_flags & ATH9K_TX_BA; 538 539 /* 540 * The hardware occasionally sends a tx status for the wrong TID. 541 * In this case, the BA status cannot be considered valid and all 542 * subframes need to be retransmitted 543 * 544 * Only BlockAcks have a TID and therefore normal Acks cannot be 545 * checked 546 */ 547 if (isba && tid->tidno != ts->tid) 548 txok = false; 549 550 isaggr = bf_isaggr(bf); 551 memset(ba, 0, WME_BA_BMP_SIZE >> 3); 552 553 if (isaggr && txok) { 554 if (ts->ts_flags & ATH9K_TX_BA) { 555 seq_st = ts->ts_seqnum; 556 memcpy(ba, &ts->ba, WME_BA_BMP_SIZE >> 3); 557 } else { 558 /* 559 * AR5416 can become deaf/mute when BA 560 * issue happens. Chip needs to be reset. 561 * But AP code may have sychronization issues 562 * when perform internal reset in this routine. 563 * Only enable reset in STA mode for now. 564 */ 565 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) 566 needreset = 1; 567 } 568 } 569 570 __skb_queue_head_init(&bf_pending); 571 572 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad); 573 while (bf) { 574 u16 seqno = bf->bf_state.seqno; 575 576 txfail = txpending = sendbar = 0; 577 bf_next = bf->bf_next; 578 579 skb = bf->bf_mpdu; 580 tx_info = IEEE80211_SKB_CB(skb); 581 fi = get_frame_info(skb); 582 583 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) || 584 !tid->active) { 585 /* 586 * Outside of the current BlockAck window, 587 * maybe part of a previous session 588 */ 589 txfail = 1; 590 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) { 591 /* transmit completion, subframe is 592 * acked by block ack */ 593 acked_cnt++; 594 } else if (!isaggr && txok) { 595 /* transmit completion */ 596 acked_cnt++; 597 } else if (flush) { 598 txpending = 1; 599 } else if (fi->retries < ATH_MAX_SW_RETRIES) { 600 if (txok || !an->sleeping) 601 ath_tx_set_retry(sc, txq, bf->bf_mpdu, 602 retries); 603 604 txpending = 1; 605 } else { 606 txfail = 1; 607 txfail_cnt++; 608 bar_index = max_t(int, bar_index, 609 ATH_BA_INDEX(seq_first, seqno)); 610 } 611 612 /* 613 * Make sure the last desc is reclaimed if it 614 * not a holding desc. 615 */ 616 INIT_LIST_HEAD(&bf_head); 617 if (bf_next != NULL || !bf_last->bf_state.stale) 618 list_move_tail(&bf->list, &bf_head); 619 620 if (!txpending) { 621 /* 622 * complete the acked-ones/xretried ones; update 623 * block-ack window 624 */ 625 ath_tx_update_baw(sc, tid, bf); 626 627 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { 628 memcpy(tx_info->control.rates, rates, sizeof(rates)); 629 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok); 630 rc_update = false; 631 if (bf == bf->bf_lastbf) 632 ath_dynack_sample_tx_ts(sc->sc_ah, 633 bf->bf_mpdu, 634 ts, sta); 635 } 636 637 ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts, 638 !txfail); 639 } else { 640 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) { 641 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP; 642 ieee80211_sta_eosp(sta); 643 } 644 /* retry the un-acked ones */ 645 if (bf->bf_next == NULL && bf_last->bf_state.stale) { 646 struct ath_buf *tbf; 647 648 tbf = ath_clone_txbuf(sc, bf_last); 649 /* 650 * Update tx baw and complete the 651 * frame with failed status if we 652 * run out of tx buf. 653 */ 654 if (!tbf) { 655 ath_tx_update_baw(sc, tid, bf); 656 657 ath_tx_complete_buf(sc, bf, txq, 658 &bf_head, NULL, ts, 659 0); 660 bar_index = max_t(int, bar_index, 661 ATH_BA_INDEX(seq_first, seqno)); 662 break; 663 } 664 665 fi->bf = tbf; 666 } 667 668 /* 669 * Put this buffer to the temporary pending 670 * queue to retain ordering 671 */ 672 __skb_queue_tail(&bf_pending, skb); 673 } 674 675 bf = bf_next; 676 } 677 678 /* prepend un-acked frames to the beginning of the pending frame queue */ 679 if (!skb_queue_empty(&bf_pending)) { 680 if (an->sleeping) 681 ieee80211_sta_set_buffered(sta, tid->tidno, true); 682 683 skb_queue_splice_tail(&bf_pending, &tid->retry_q); 684 if (!an->sleeping) { 685 ath_tx_queue_tid(sc, tid); 686 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) 687 tid->clear_ps_filter = true; 688 } 689 } 690 691 if (bar_index >= 0) { 692 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index); 693 694 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq)) 695 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq); 696 697 ath_txq_unlock(sc, txq); 698 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1)); 699 ath_txq_lock(sc, txq); 700 } 701 702 if (needreset) 703 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR); 704} 705 706static bool bf_is_ampdu_not_probing(struct ath_buf *bf) 707{ 708 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu); 709 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 710} 711 712static void ath_tx_count_airtime(struct ath_softc *sc, 713 struct ieee80211_sta *sta, 714 struct ath_buf *bf, 715 struct ath_tx_status *ts, 716 u8 tid) 717{ 718 u32 airtime = 0; 719 int i; 720 721 airtime += ts->duration * (ts->ts_longretry + 1); 722 for(i = 0; i < ts->ts_rateindex; i++) { 723 int rate_dur = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, i); 724 airtime += rate_dur * bf->rates[i].count; 725 } 726 727 ieee80211_sta_register_airtime(sta, tid, airtime, 0); 728} 729 730static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq, 731 struct ath_tx_status *ts, struct ath_buf *bf, 732 struct list_head *bf_head) 733{ 734 struct ieee80211_hw *hw = sc->hw; 735 struct ieee80211_tx_info *info; 736 struct ieee80211_sta *sta; 737 struct ieee80211_hdr *hdr; 738 struct ath_atx_tid *tid = NULL; 739 bool txok, flush; 740 741 txok = !(ts->ts_status & ATH9K_TXERR_MASK); 742 flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 743 txq->axq_tx_inprogress = false; 744 745 txq->axq_depth--; 746 if (bf_is_ampdu_not_probing(bf)) 747 txq->axq_ampdu_depth--; 748 749 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, 750 ts->ts_rateindex); 751 752 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; 753 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); 754 if (sta) { 755 struct ath_node *an = (struct ath_node *)sta->drv_priv; 756 tid = ath_get_skb_tid(sc, an, bf->bf_mpdu); 757 ath_tx_count_airtime(sc, sta, bf, ts, tid->tidno); 758 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) 759 tid->clear_ps_filter = true; 760 } 761 762 if (!bf_isampdu(bf)) { 763 if (!flush) { 764 info = IEEE80211_SKB_CB(bf->bf_mpdu); 765 memcpy(info->control.rates, bf->rates, 766 sizeof(info->control.rates)); 767 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok); 768 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts, 769 sta); 770 } 771 ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok); 772 } else 773 ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok); 774 775 if (!flush) 776 ath_txq_schedule(sc, txq); 777} 778 779static bool ath_lookup_legacy(struct ath_buf *bf) 780{ 781 struct sk_buff *skb; 782 struct ieee80211_tx_info *tx_info; 783 struct ieee80211_tx_rate *rates; 784 int i; 785 786 skb = bf->bf_mpdu; 787 tx_info = IEEE80211_SKB_CB(skb); 788 rates = tx_info->control.rates; 789 790 for (i = 0; i < 4; i++) { 791 if (!rates[i].count || rates[i].idx < 0) 792 break; 793 794 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) 795 return true; 796 } 797 798 return false; 799} 800 801static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 802 struct ath_atx_tid *tid) 803{ 804 struct sk_buff *skb; 805 struct ieee80211_tx_info *tx_info; 806 struct ieee80211_tx_rate *rates; 807 u32 max_4ms_framelen, frmlen; 808 u16 aggr_limit, bt_aggr_limit, legacy = 0; 809 int q = tid->txq->mac80211_qnum; 810 int i; 811 812 skb = bf->bf_mpdu; 813 tx_info = IEEE80211_SKB_CB(skb); 814 rates = bf->rates; 815 816 /* 817 * Find the lowest frame length among the rate series that will have a 818 * 4ms (or TXOP limited) transmit duration. 819 */ 820 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; 821 822 for (i = 0; i < 4; i++) { 823 int modeidx; 824 825 if (!rates[i].count) 826 continue; 827 828 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { 829 legacy = 1; 830 break; 831 } 832 833 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 834 modeidx = MCS_HT40; 835 else 836 modeidx = MCS_HT20; 837 838 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 839 modeidx++; 840 841 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx]; 842 max_4ms_framelen = min(max_4ms_framelen, frmlen); 843 } 844 845 /* 846 * limit aggregate size by the minimum rate if rate selected is 847 * not a probe rate, if rate selected is a probe rate then 848 * avoid aggregation of this packet. 849 */ 850 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) 851 return 0; 852 853 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX); 854 855 /* 856 * Override the default aggregation limit for BTCOEX. 857 */ 858 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen); 859 if (bt_aggr_limit) 860 aggr_limit = bt_aggr_limit; 861 862 if (tid->an->maxampdu) 863 aggr_limit = min(aggr_limit, tid->an->maxampdu); 864 865 return aggr_limit; 866} 867 868/* 869 * Returns the number of delimiters to be added to 870 * meet the minimum required mpdudensity. 871 */ 872static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, 873 struct ath_buf *bf, u16 frmlen, 874 bool first_subfrm) 875{ 876#define FIRST_DESC_NDELIMS 60 877 u32 nsymbits, nsymbols; 878 u16 minlen; 879 u8 flags, rix; 880 int width, streams, half_gi, ndelim, mindelim; 881 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 882 883 /* Select standard number of delimiters based on frame length alone */ 884 ndelim = ATH_AGGR_GET_NDELIM(frmlen); 885 886 /* 887 * If encryption enabled, hardware requires some more padding between 888 * subframes. 889 * TODO - this could be improved to be dependent on the rate. 890 * The hardware can keep up at lower rates, but not higher rates 891 */ 892 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) && 893 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) 894 ndelim += ATH_AGGR_ENCRYPTDELIM; 895 896 /* 897 * Add delimiter when using RTS/CTS with aggregation 898 * and non enterprise AR9003 card 899 */ 900 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) && 901 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE)) 902 ndelim = max(ndelim, FIRST_DESC_NDELIMS); 903 904 /* 905 * Convert desired mpdu density from microeconds to bytes based 906 * on highest rate in rate series (i.e. first rate) to determine 907 * required minimum length for subframe. Take into account 908 * whether high rate is 20 or 40Mhz and half or full GI. 909 * 910 * If there is no mpdu density restriction, no further calculation 911 * is needed. 912 */ 913 914 if (tid->an->mpdudensity == 0) 915 return ndelim; 916 917 rix = bf->rates[0].idx; 918 flags = bf->rates[0].flags; 919 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; 920 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; 921 922 if (half_gi) 923 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); 924 else 925 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); 926 927 if (nsymbols == 0) 928 nsymbols = 1; 929 930 streams = HT_RC_2_STREAMS(rix); 931 nsymbits = bits_per_symbol[rix % 8][width] * streams; 932 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 933 934 if (frmlen < minlen) { 935 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; 936 ndelim = max(mindelim, ndelim); 937 } 938 939 return ndelim; 940} 941 942static int 943ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq, 944 struct ath_atx_tid *tid, struct ath_buf **buf) 945{ 946 struct ieee80211_tx_info *tx_info; 947 struct ath_frame_info *fi; 948 struct ath_buf *bf; 949 struct sk_buff *skb, *first_skb = NULL; 950 u16 seqno; 951 int ret; 952 953 while (1) { 954 ret = ath_tid_dequeue(tid, &skb); 955 if (ret < 0) 956 return ret; 957 958 fi = get_frame_info(skb); 959 bf = fi->bf; 960 if (!fi->bf) 961 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 962 else 963 bf->bf_state.stale = false; 964 965 if (!bf) { 966 ath_txq_skb_done(sc, txq, skb); 967 ieee80211_free_txskb(sc->hw, skb); 968 continue; 969 } 970 971 bf->bf_next = NULL; 972 bf->bf_lastbf = bf; 973 974 tx_info = IEEE80211_SKB_CB(skb); 975 tx_info->flags &= ~(IEEE80211_TX_CTL_CLEAR_PS_FILT | 976 IEEE80211_TX_STATUS_EOSP); 977 978 /* 979 * No aggregation session is running, but there may be frames 980 * from a previous session or a failed attempt in the queue. 981 * Send them out as normal data frames 982 */ 983 if (!tid->active) 984 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; 985 986 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 987 bf->bf_state.bf_type = 0; 988 break; 989 } 990 991 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR; 992 seqno = bf->bf_state.seqno; 993 994 /* do not step over block-ack window */ 995 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) { 996 __skb_queue_tail(&tid->retry_q, skb); 997 998 /* If there are other skbs in the retry q, they are 999 * probably within the BAW, so loop immediately to get 1000 * one of them. Otherwise the queue can get stuck. */ 1001 if (!skb_queue_is_first(&tid->retry_q, skb) && 1002 !WARN_ON(skb == first_skb)) { 1003 if(!first_skb) /* infinite loop prevention */ 1004 first_skb = skb; 1005 continue; 1006 } 1007 return -EINPROGRESS; 1008 } 1009 1010 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) { 1011 struct ath_tx_status ts = {}; 1012 struct list_head bf_head; 1013 1014 INIT_LIST_HEAD(&bf_head); 1015 list_add(&bf->list, &bf_head); 1016 ath_tx_update_baw(sc, tid, bf); 1017 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); 1018 continue; 1019 } 1020 1021 if (bf_isampdu(bf)) 1022 ath_tx_addto_baw(sc, tid, bf); 1023 1024 break; 1025 } 1026 1027 *buf = bf; 1028 return 0; 1029} 1030 1031static int 1032ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq, 1033 struct ath_atx_tid *tid, struct list_head *bf_q, 1034 struct ath_buf *bf_first) 1035{ 1036#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) 1037 struct ath_buf *bf = bf_first, *bf_prev = NULL; 1038 int nframes = 0, ndelim, ret; 1039 u16 aggr_limit = 0, al = 0, bpad = 0, 1040 al_delta, h_baw = tid->baw_size / 2; 1041 struct ieee80211_tx_info *tx_info; 1042 struct ath_frame_info *fi; 1043 struct sk_buff *skb; 1044 1045 1046 bf = bf_first; 1047 aggr_limit = ath_lookup_rate(sc, bf, tid); 1048 1049 while (bf) 1050 { 1051 skb = bf->bf_mpdu; 1052 fi = get_frame_info(skb); 1053 1054 /* do not exceed aggregation limit */ 1055 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen; 1056 if (nframes) { 1057 if (aggr_limit < al + bpad + al_delta || 1058 ath_lookup_legacy(bf) || nframes >= h_baw) 1059 goto stop; 1060 1061 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1062 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) || 1063 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) 1064 goto stop; 1065 } 1066 1067 /* add padding for previous frame to aggregation length */ 1068 al += bpad + al_delta; 1069 1070 /* 1071 * Get the delimiters needed to meet the MPDU 1072 * density for this node. 1073 */ 1074 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen, 1075 !nframes); 1076 bpad = PADBYTES(al_delta) + (ndelim << 2); 1077 1078 nframes++; 1079 bf->bf_next = NULL; 1080 1081 /* link buffers of this frame to the aggregate */ 1082 bf->bf_state.ndelim = ndelim; 1083 1084 list_add_tail(&bf->list, bf_q); 1085 if (bf_prev) 1086 bf_prev->bf_next = bf; 1087 1088 bf_prev = bf; 1089 1090 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf); 1091 if (ret < 0) 1092 break; 1093 } 1094 goto finish; 1095stop: 1096 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu); 1097finish: 1098 bf = bf_first; 1099 bf->bf_lastbf = bf_prev; 1100 1101 if (bf == bf_prev) { 1102 al = get_frame_info(bf->bf_mpdu)->framelen; 1103 bf->bf_state.bf_type = BUF_AMPDU; 1104 } else { 1105 TX_STAT_INC(sc, txq->axq_qnum, a_aggr); 1106 } 1107 1108 return al; 1109#undef PADBYTES 1110} 1111 1112/* 1113 * rix - rate index 1114 * pktlen - total bytes (delims + data + fcs + pads + pad delims) 1115 * width - 0 for 20 MHz, 1 for 40 MHz 1116 * half_gi - to use 4us v/s 3.6 us for symbol time 1117 */ 1118u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, 1119 int width, int half_gi, bool shortPreamble) 1120{ 1121 u32 nbits, nsymbits, duration, nsymbols; 1122 int streams; 1123 1124 /* find number of symbols: PLCP + data */ 1125 streams = HT_RC_2_STREAMS(rix); 1126 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 1127 nsymbits = bits_per_symbol[rix % 8][width] * streams; 1128 nsymbols = (nbits + nsymbits - 1) / nsymbits; 1129 1130 if (!half_gi) 1131 duration = SYMBOL_TIME(nsymbols); 1132 else 1133 duration = SYMBOL_TIME_HALFGI(nsymbols); 1134 1135 /* addup duration for legacy/ht training and signal fields */ 1136 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1137 1138 return duration; 1139} 1140 1141static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi) 1142{ 1143 int streams = HT_RC_2_STREAMS(mcs); 1144 int symbols, bits; 1145 int bytes = 0; 1146 1147 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1148 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec); 1149 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams; 1150 bits -= OFDM_PLCP_BITS; 1151 bytes = bits / 8; 1152 if (bytes > 65532) 1153 bytes = 65532; 1154 1155 return bytes; 1156} 1157 1158void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop) 1159{ 1160 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi; 1161 int mcs; 1162 1163 /* 4ms is the default (and maximum) duration */ 1164 if (!txop || txop > 4096) 1165 txop = 4096; 1166 1167 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20]; 1168 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI]; 1169 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40]; 1170 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI]; 1171 for (mcs = 0; mcs < 32; mcs++) { 1172 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false); 1173 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true); 1174 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false); 1175 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true); 1176 } 1177} 1178 1179static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf, 1180 u8 rateidx, bool is_40, bool is_cck, bool is_mcs) 1181{ 1182 u8 max_power; 1183 struct sk_buff *skb; 1184 struct ath_frame_info *fi; 1185 struct ieee80211_tx_info *info; 1186 struct ath_hw *ah = sc->sc_ah; 1187 bool is_2ghz, is_5ghz, use_stbc; 1188 1189 if (sc->tx99_state || !ah->tpc_enabled) 1190 return MAX_RATE_POWER; 1191 1192 skb = bf->bf_mpdu; 1193 fi = get_frame_info(skb); 1194 info = IEEE80211_SKB_CB(skb); 1195 1196 is_2ghz = info->band == NL80211_BAND_2GHZ; 1197 is_5ghz = info->band == NL80211_BAND_5GHZ; 1198 use_stbc = is_mcs && rateidx < 8 && (info->flags & 1199 IEEE80211_TX_CTL_STBC); 1200 1201 if (is_mcs) 1202 rateidx += is_5ghz ? ATH9K_PWRTBL_11NA_HT_SHIFT 1203 : ATH9K_PWRTBL_11NG_HT_SHIFT; 1204 else if (is_2ghz && !is_cck) 1205 rateidx += ATH9K_PWRTBL_11NG_OFDM_SHIFT; 1206 else 1207 rateidx += ATH9K_PWRTBL_11NA_OFDM_SHIFT; 1208 1209 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1210 int txpower = fi->tx_power; 1211 1212 if (is_40) { 1213 u8 power_ht40delta; 1214 struct ar5416_eeprom_def *eep = &ah->eeprom.def; 1215 u16 eeprom_rev = ah->eep_ops->get_eeprom_rev(ah); 1216 1217 if (eeprom_rev >= AR5416_EEP_MINOR_VER_2) { 1218 struct modal_eep_header *pmodal; 1219 1220 pmodal = &eep->modalHeader[is_2ghz]; 1221 power_ht40delta = pmodal->ht40PowerIncForPdadc; 1222 } else { 1223 power_ht40delta = 2; 1224 } 1225 txpower += power_ht40delta; 1226 } 1227 1228 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) || 1229 AR_SREV_9271(ah)) { 1230 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB; 1231 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 1232 s8 power_offset; 1233 1234 power_offset = ah->eep_ops->get_eeprom(ah, 1235 EEP_PWR_TABLE_OFFSET); 1236 txpower -= 2 * power_offset; 1237 } 1238 1239 if (OLC_FOR_AR9280_20_LATER(ah) && is_cck) 1240 txpower -= 2; 1241 1242 txpower = max(txpower, 0); 1243 max_power = min_t(u8, ah->tx_power[rateidx], txpower); 1244 1245 /* XXX: clamp minimum TX power at 1 for AR9160 since if 1246 * max_power is set to 0, frames are transmitted at max 1247 * TX power 1248 */ 1249 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah)) 1250 max_power = 1; 1251 } else if (!bf->bf_state.bfs_paprd) { 1252 if (use_stbc) 1253 max_power = min_t(u8, ah->tx_power_stbc[rateidx], 1254 fi->tx_power); 1255 else 1256 max_power = min_t(u8, ah->tx_power[rateidx], 1257 fi->tx_power); 1258 } else { 1259 max_power = ah->paprd_training_power; 1260 } 1261 1262 return max_power; 1263} 1264 1265static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, 1266 struct ath_tx_info *info, int len, bool rts) 1267{ 1268 struct ath_hw *ah = sc->sc_ah; 1269 struct ath_common *common = ath9k_hw_common(ah); 1270 struct sk_buff *skb; 1271 struct ieee80211_tx_info *tx_info; 1272 struct ieee80211_tx_rate *rates; 1273 const struct ieee80211_rate *rate; 1274 struct ieee80211_hdr *hdr; 1275 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 1276 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1277 int i; 1278 u8 rix = 0; 1279 1280 skb = bf->bf_mpdu; 1281 tx_info = IEEE80211_SKB_CB(skb); 1282 rates = bf->rates; 1283 hdr = (struct ieee80211_hdr *)skb->data; 1284 1285 /* set dur_update_en for l-sig computation except for PS-Poll frames */ 1286 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control); 1287 info->rtscts_rate = fi->rtscts_rate; 1288 1289 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) { 1290 bool is_40, is_sgi, is_sp, is_cck; 1291 int phy; 1292 1293 if (!rates[i].count || (rates[i].idx < 0)) 1294 break; 1295 1296 rix = rates[i].idx; 1297 info->rates[i].Tries = rates[i].count; 1298 1299 /* 1300 * Handle RTS threshold for unaggregated HT frames. 1301 */ 1302 if (bf_isampdu(bf) && !bf_isaggr(bf) && 1303 (rates[i].flags & IEEE80211_TX_RC_MCS) && 1304 unlikely(rts_thresh != (u32) -1)) { 1305 if (!rts_thresh || (len > rts_thresh)) 1306 rts = true; 1307 } 1308 1309 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { 1310 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1311 info->flags |= ATH9K_TXDESC_RTSENA; 1312 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 1313 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1314 info->flags |= ATH9K_TXDESC_CTSENA; 1315 } 1316 1317 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1318 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040; 1319 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 1320 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI; 1321 1322 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); 1323 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); 1324 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); 1325 1326 if (rates[i].flags & IEEE80211_TX_RC_MCS) { 1327 /* MCS rates */ 1328 info->rates[i].Rate = rix | 0x80; 1329 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1330 ah->txchainmask, info->rates[i].Rate); 1331 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len, 1332 is_40, is_sgi, is_sp); 1333 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) 1334 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC; 1335 if (rix >= 8 && fi->dyn_smps) { 1336 info->rates[i].RateFlags |= 1337 ATH9K_RATESERIES_RTS_CTS; 1338 info->flags |= ATH9K_TXDESC_CTSENA; 1339 } 1340 1341 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, 1342 is_40, false, true); 1343 continue; 1344 } 1345 1346 /* legacy rates */ 1347 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx]; 1348 if ((tx_info->band == NL80211_BAND_2GHZ) && 1349 !(rate->flags & IEEE80211_RATE_ERP_G)) 1350 phy = WLAN_RC_PHY_CCK; 1351 else 1352 phy = WLAN_RC_PHY_OFDM; 1353 1354 info->rates[i].Rate = rate->hw_value; 1355 if (rate->hw_value_short) { 1356 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1357 info->rates[i].Rate |= rate->hw_value_short; 1358 } else { 1359 is_sp = false; 1360 } 1361 1362 if (bf->bf_state.bfs_paprd) 1363 info->rates[i].ChSel = ah->txchainmask; 1364 else 1365 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1366 ah->txchainmask, info->rates[i].Rate); 1367 1368 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, 1369 phy, rate->bitrate * 100, len, rix, is_sp); 1370 1371 is_cck = IS_CCK_RATE(info->rates[i].Rate); 1372 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false, 1373 is_cck, false); 1374 } 1375 1376 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ 1377 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) 1378 info->flags &= ~ATH9K_TXDESC_RTSENA; 1379 1380 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ 1381 if (info->flags & ATH9K_TXDESC_RTSENA) 1382 info->flags &= ~ATH9K_TXDESC_CTSENA; 1383} 1384 1385static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) 1386{ 1387 struct ieee80211_hdr *hdr; 1388 enum ath9k_pkt_type htype; 1389 __le16 fc; 1390 1391 hdr = (struct ieee80211_hdr *)skb->data; 1392 fc = hdr->frame_control; 1393 1394 if (ieee80211_is_beacon(fc)) 1395 htype = ATH9K_PKT_TYPE_BEACON; 1396 else if (ieee80211_is_probe_resp(fc)) 1397 htype = ATH9K_PKT_TYPE_PROBE_RESP; 1398 else if (ieee80211_is_atim(fc)) 1399 htype = ATH9K_PKT_TYPE_ATIM; 1400 else if (ieee80211_is_pspoll(fc)) 1401 htype = ATH9K_PKT_TYPE_PSPOLL; 1402 else 1403 htype = ATH9K_PKT_TYPE_NORMAL; 1404 1405 return htype; 1406} 1407 1408static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf, 1409 struct ath_txq *txq, int len) 1410{ 1411 struct ath_hw *ah = sc->sc_ah; 1412 struct ath_buf *bf_first = NULL; 1413 struct ath_tx_info info; 1414 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1415 bool rts = false; 1416 1417 memset(&info, 0, sizeof(info)); 1418 info.is_first = true; 1419 info.is_last = true; 1420 info.qcu = txq->axq_qnum; 1421 1422 while (bf) { 1423 struct sk_buff *skb = bf->bf_mpdu; 1424 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1425 struct ath_frame_info *fi = get_frame_info(skb); 1426 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR); 1427 1428 info.type = get_hw_packet_type(skb); 1429 if (bf->bf_next) 1430 info.link = bf->bf_next->bf_daddr; 1431 else 1432 info.link = (sc->tx99_state) ? bf->bf_daddr : 0; 1433 1434 if (!bf_first) { 1435 bf_first = bf; 1436 1437 if (!sc->tx99_state) 1438 info.flags = ATH9K_TXDESC_INTREQ; 1439 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) || 1440 txq == sc->tx.uapsdq) 1441 info.flags |= ATH9K_TXDESC_CLRDMASK; 1442 1443 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 1444 info.flags |= ATH9K_TXDESC_NOACK; 1445 if (tx_info->flags & IEEE80211_TX_CTL_LDPC) 1446 info.flags |= ATH9K_TXDESC_LDPC; 1447 1448 if (bf->bf_state.bfs_paprd) 1449 info.flags |= (u32) bf->bf_state.bfs_paprd << 1450 ATH9K_TXDESC_PAPRD_S; 1451 1452 /* 1453 * mac80211 doesn't handle RTS threshold for HT because 1454 * the decision has to be taken based on AMPDU length 1455 * and aggregation is done entirely inside ath9k. 1456 * Set the RTS/CTS flag for the first subframe based 1457 * on the threshold. 1458 */ 1459 if (aggr && (bf == bf_first) && 1460 unlikely(rts_thresh != (u32) -1)) { 1461 /* 1462 * "len" is the size of the entire AMPDU. 1463 */ 1464 if (!rts_thresh || (len > rts_thresh)) 1465 rts = true; 1466 } 1467 1468 if (!aggr) 1469 len = fi->framelen; 1470 1471 ath_buf_set_rate(sc, bf, &info, len, rts); 1472 } 1473 1474 info.buf_addr[0] = bf->bf_buf_addr; 1475 info.buf_len[0] = skb->len; 1476 info.pkt_len = fi->framelen; 1477 info.keyix = fi->keyix; 1478 info.keytype = fi->keytype; 1479 1480 if (aggr) { 1481 if (bf == bf_first) 1482 info.aggr = AGGR_BUF_FIRST; 1483 else if (bf == bf_first->bf_lastbf) 1484 info.aggr = AGGR_BUF_LAST; 1485 else 1486 info.aggr = AGGR_BUF_MIDDLE; 1487 1488 info.ndelim = bf->bf_state.ndelim; 1489 info.aggr_len = len; 1490 } 1491 1492 if (bf == bf_first->bf_lastbf) 1493 bf_first = NULL; 1494 1495 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); 1496 bf = bf->bf_next; 1497 } 1498} 1499 1500static void 1501ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq, 1502 struct ath_atx_tid *tid, struct list_head *bf_q, 1503 struct ath_buf *bf_first) 1504{ 1505 struct ath_buf *bf = bf_first, *bf_prev = NULL; 1506 int nframes = 0, ret; 1507 1508 do { 1509 struct ieee80211_tx_info *tx_info; 1510 1511 nframes++; 1512 list_add_tail(&bf->list, bf_q); 1513 if (bf_prev) 1514 bf_prev->bf_next = bf; 1515 bf_prev = bf; 1516 1517 if (nframes >= 2) 1518 break; 1519 1520 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf); 1521 if (ret < 0) 1522 break; 1523 1524 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1525 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 1526 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu); 1527 break; 1528 } 1529 1530 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1531 } while (1); 1532} 1533 1534static int ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, 1535 struct ath_atx_tid *tid) 1536{ 1537 struct ath_buf *bf = NULL; 1538 struct ieee80211_tx_info *tx_info; 1539 struct list_head bf_q; 1540 int aggr_len = 0, ret; 1541 bool aggr; 1542 1543 INIT_LIST_HEAD(&bf_q); 1544 1545 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf); 1546 if (ret < 0) 1547 return ret; 1548 1549 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1550 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU); 1551 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) || 1552 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) { 1553 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu); 1554 return -EBUSY; 1555 } 1556 1557 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1558 if (aggr) 1559 aggr_len = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf); 1560 else 1561 ath_tx_form_burst(sc, txq, tid, &bf_q, bf); 1562 1563 if (list_empty(&bf_q)) 1564 return -EAGAIN; 1565 1566 if (tid->clear_ps_filter || tid->an->no_ps_filter) { 1567 tid->clear_ps_filter = false; 1568 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 1569 } 1570 1571 ath_tx_fill_desc(sc, bf, txq, aggr_len); 1572 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1573 return 0; 1574} 1575 1576int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 1577 u16 tid, u16 *ssn) 1578{ 1579 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1580 struct ath_atx_tid *txtid; 1581 struct ath_txq *txq; 1582 struct ath_node *an; 1583 u8 density; 1584 1585 ath_dbg(common, XMIT, "%s called\n", __func__); 1586 1587 an = (struct ath_node *)sta->drv_priv; 1588 txtid = ATH_AN_2_TID(an, tid); 1589 txq = txtid->txq; 1590 1591 ath_txq_lock(sc, txq); 1592 1593 /* update ampdu factor/density, they may have changed. This may happen 1594 * in HT IBSS when a beacon with HT-info is received after the station 1595 * has already been added. 1596 */ 1597 if (sta->deflink.ht_cap.ht_supported) { 1598 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 1599 sta->deflink.ht_cap.ampdu_factor)) - 1; 1600 density = ath9k_parse_mpdudensity(sta->deflink.ht_cap.ampdu_density); 1601 an->mpdudensity = density; 1602 } 1603 1604 txtid->active = true; 1605 *ssn = txtid->seq_start = txtid->seq_next; 1606 txtid->bar_index = -1; 1607 1608 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf)); 1609 txtid->baw_head = txtid->baw_tail = 0; 1610 1611 ath_txq_unlock_complete(sc, txq); 1612 1613 return 0; 1614} 1615 1616void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 1617{ 1618 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1619 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1620 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); 1621 struct ath_txq *txq = txtid->txq; 1622 1623 ath_dbg(common, XMIT, "%s called\n", __func__); 1624 1625 ath_txq_lock(sc, txq); 1626 txtid->active = false; 1627 ath_tx_flush_tid(sc, txtid); 1628 ath_txq_unlock_complete(sc, txq); 1629} 1630 1631void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 1632 struct ath_node *an) 1633{ 1634 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1635 struct ath_atx_tid *tid; 1636 int tidno; 1637 1638 ath_dbg(common, XMIT, "%s called\n", __func__); 1639 1640 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 1641 tid = ath_node_to_tid(an, tidno); 1642 1643 if (!skb_queue_empty(&tid->retry_q)) 1644 ieee80211_sta_set_buffered(sta, tid->tidno, true); 1645 1646 } 1647} 1648 1649void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an) 1650{ 1651 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1652 struct ath_atx_tid *tid; 1653 struct ath_txq *txq; 1654 int tidno; 1655 1656 ath_dbg(common, XMIT, "%s called\n", __func__); 1657 1658 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 1659 tid = ath_node_to_tid(an, tidno); 1660 txq = tid->txq; 1661 1662 ath_txq_lock(sc, txq); 1663 tid->clear_ps_filter = true; 1664 if (!skb_queue_empty(&tid->retry_q)) { 1665 ath_tx_queue_tid(sc, tid); 1666 ath_txq_schedule(sc, txq); 1667 } 1668 ath_txq_unlock_complete(sc, txq); 1669 1670 } 1671} 1672 1673 1674static void 1675ath9k_set_moredata(struct ath_softc *sc, struct ath_buf *bf, bool val) 1676{ 1677 struct ieee80211_hdr *hdr; 1678 u16 mask = cpu_to_le16(IEEE80211_FCTL_MOREDATA); 1679 u16 mask_val = mask * val; 1680 1681 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; 1682 if ((hdr->frame_control & mask) != mask_val) { 1683 hdr->frame_control = (hdr->frame_control & ~mask) | mask_val; 1684 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 1685 sizeof(*hdr), DMA_TO_DEVICE); 1686 } 1687} 1688 1689void ath9k_release_buffered_frames(struct ieee80211_hw *hw, 1690 struct ieee80211_sta *sta, 1691 u16 tids, int nframes, 1692 enum ieee80211_frame_release_type reason, 1693 bool more_data) 1694{ 1695 struct ath_softc *sc = hw->priv; 1696 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1697 struct ath_txq *txq = sc->tx.uapsdq; 1698 struct ieee80211_tx_info *info; 1699 struct list_head bf_q; 1700 struct ath_buf *bf_tail = NULL, *bf = NULL; 1701 int i, ret; 1702 1703 INIT_LIST_HEAD(&bf_q); 1704 for (i = 0; tids && nframes; i++, tids >>= 1) { 1705 struct ath_atx_tid *tid; 1706 1707 if (!(tids & 1)) 1708 continue; 1709 1710 tid = ATH_AN_2_TID(an, i); 1711 1712 ath_txq_lock(sc, tid->txq); 1713 while (nframes > 0) { 1714 ret = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, 1715 tid, &bf); 1716 if (ret < 0) 1717 break; 1718 1719 ath9k_set_moredata(sc, bf, true); 1720 list_add_tail(&bf->list, &bf_q); 1721 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1722 if (bf_isampdu(bf)) 1723 bf->bf_state.bf_type &= ~BUF_AGGR; 1724 if (bf_tail) 1725 bf_tail->bf_next = bf; 1726 1727 bf_tail = bf; 1728 nframes--; 1729 TX_STAT_INC(sc, txq->axq_qnum, a_queued_hw); 1730 1731 if (an->sta && skb_queue_empty(&tid->retry_q)) 1732 ieee80211_sta_set_buffered(an->sta, i, false); 1733 } 1734 ath_txq_unlock_complete(sc, tid->txq); 1735 } 1736 1737 if (list_empty(&bf_q)) 1738 return; 1739 1740 if (!more_data) 1741 ath9k_set_moredata(sc, bf_tail, false); 1742 1743 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu); 1744 info->flags |= IEEE80211_TX_STATUS_EOSP; 1745 1746 bf = list_first_entry(&bf_q, struct ath_buf, list); 1747 ath_txq_lock(sc, txq); 1748 ath_tx_fill_desc(sc, bf, txq, 0); 1749 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1750 ath_txq_unlock(sc, txq); 1751} 1752 1753/********************/ 1754/* Queue Management */ 1755/********************/ 1756 1757struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 1758{ 1759 struct ath_hw *ah = sc->sc_ah; 1760 struct ath9k_tx_queue_info qi; 1761 static const int subtype_txq_to_hwq[] = { 1762 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE, 1763 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK, 1764 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI, 1765 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO, 1766 }; 1767 int axq_qnum, i; 1768 1769 memset(&qi, 0, sizeof(qi)); 1770 qi.tqi_subtype = subtype_txq_to_hwq[subtype]; 1771 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; 1772 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; 1773 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; 1774 qi.tqi_physCompBuf = 0; 1775 1776 /* 1777 * Enable interrupts only for EOL and DESC conditions. 1778 * We mark tx descriptors to receive a DESC interrupt 1779 * when a tx queue gets deep; otherwise waiting for the 1780 * EOL to reap descriptors. Note that this is done to 1781 * reduce interrupt load and this only defers reaping 1782 * descriptors, never transmitting frames. Aside from 1783 * reducing interrupts this also permits more concurrency. 1784 * The only potential downside is if the tx queue backs 1785 * up in which case the top half of the kernel may backup 1786 * due to a lack of tx descriptors. 1787 * 1788 * The UAPSD queue is an exception, since we take a desc- 1789 * based intr on the EOSP frames. 1790 */ 1791 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1792 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; 1793 } else { 1794 if (qtype == ATH9K_TX_QUEUE_UAPSD) 1795 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 1796 else 1797 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | 1798 TXQ_FLAG_TXDESCINT_ENABLE; 1799 } 1800 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); 1801 if (axq_qnum == -1) { 1802 /* 1803 * NB: don't print a message, this happens 1804 * normally on parts with too few tx queues 1805 */ 1806 return NULL; 1807 } 1808 if (!ATH_TXQ_SETUP(sc, axq_qnum)) { 1809 struct ath_txq *txq = &sc->tx.txq[axq_qnum]; 1810 1811 txq->axq_qnum = axq_qnum; 1812 txq->mac80211_qnum = -1; 1813 txq->axq_link = NULL; 1814 __skb_queue_head_init(&txq->complete_q); 1815 INIT_LIST_HEAD(&txq->axq_q); 1816 spin_lock_init(&txq->axq_lock); 1817 txq->axq_depth = 0; 1818 txq->axq_ampdu_depth = 0; 1819 txq->axq_tx_inprogress = false; 1820 sc->tx.txqsetup |= 1<<axq_qnum; 1821 1822 txq->txq_headidx = txq->txq_tailidx = 0; 1823 for (i = 0; i < ATH_TXFIFO_DEPTH; i++) 1824 INIT_LIST_HEAD(&txq->txq_fifo[i]); 1825 } 1826 return &sc->tx.txq[axq_qnum]; 1827} 1828 1829int ath_txq_update(struct ath_softc *sc, int qnum, 1830 struct ath9k_tx_queue_info *qinfo) 1831{ 1832 struct ath_hw *ah = sc->sc_ah; 1833 int error = 0; 1834 struct ath9k_tx_queue_info qi; 1835 1836 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); 1837 1838 ath9k_hw_get_txq_props(ah, qnum, &qi); 1839 qi.tqi_aifs = qinfo->tqi_aifs; 1840 qi.tqi_cwmin = qinfo->tqi_cwmin; 1841 qi.tqi_cwmax = qinfo->tqi_cwmax; 1842 qi.tqi_burstTime = qinfo->tqi_burstTime; 1843 qi.tqi_readyTime = qinfo->tqi_readyTime; 1844 1845 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 1846 ath_err(ath9k_hw_common(sc->sc_ah), 1847 "Unable to update hardware queue %u!\n", qnum); 1848 error = -EIO; 1849 } else { 1850 ath9k_hw_resettxqueue(ah, qnum); 1851 } 1852 1853 return error; 1854} 1855 1856int ath_cabq_update(struct ath_softc *sc) 1857{ 1858 struct ath9k_tx_queue_info qi; 1859 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon; 1860 int qnum = sc->beacon.cabq->axq_qnum; 1861 1862 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); 1863 1864 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) * 1865 ATH_CABQ_READY_TIME) / 100; 1866 ath_txq_update(sc, qnum, &qi); 1867 1868 return 0; 1869} 1870 1871static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq, 1872 struct list_head *list) 1873{ 1874 struct ath_buf *bf, *lastbf; 1875 struct list_head bf_head; 1876 struct ath_tx_status ts; 1877 1878 memset(&ts, 0, sizeof(ts)); 1879 ts.ts_status = ATH9K_TX_FLUSH; 1880 INIT_LIST_HEAD(&bf_head); 1881 1882 while (!list_empty(list)) { 1883 bf = list_first_entry(list, struct ath_buf, list); 1884 1885 if (bf->bf_state.stale) { 1886 list_del(&bf->list); 1887 1888 ath_tx_return_buffer(sc, bf); 1889 continue; 1890 } 1891 1892 lastbf = bf->bf_lastbf; 1893 list_cut_position(&bf_head, list, &lastbf->list); 1894 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 1895 } 1896} 1897 1898/* 1899 * Drain a given TX queue (could be Beacon or Data) 1900 * 1901 * This assumes output has been stopped and 1902 * we do not need to block ath_tx_tasklet. 1903 */ 1904void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq) 1905{ 1906 rcu_read_lock(); 1907 ath_txq_lock(sc, txq); 1908 1909 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1910 int idx = txq->txq_tailidx; 1911 1912 while (!list_empty(&txq->txq_fifo[idx])) { 1913 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]); 1914 1915 INCR(idx, ATH_TXFIFO_DEPTH); 1916 } 1917 txq->txq_tailidx = idx; 1918 } 1919 1920 txq->axq_link = NULL; 1921 txq->axq_tx_inprogress = false; 1922 ath_drain_txq_list(sc, txq, &txq->axq_q); 1923 1924 ath_txq_unlock_complete(sc, txq); 1925 rcu_read_unlock(); 1926} 1927 1928bool ath_drain_all_txq(struct ath_softc *sc) 1929{ 1930 struct ath_hw *ah = sc->sc_ah; 1931 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1932 struct ath_txq *txq; 1933 int i; 1934 u32 npend = 0; 1935 1936 if (test_bit(ATH_OP_INVALID, &common->op_flags)) 1937 return true; 1938 1939 ath9k_hw_abort_tx_dma(ah); 1940 1941 /* Check if any queue remains active */ 1942 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1943 if (!ATH_TXQ_SETUP(sc, i)) 1944 continue; 1945 1946 if (!sc->tx.txq[i].axq_depth) 1947 continue; 1948 1949 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum)) 1950 npend |= BIT(i); 1951 } 1952 1953 if (npend) { 1954 RESET_STAT_INC(sc, RESET_TX_DMA_ERROR); 1955 ath_dbg(common, RESET, 1956 "Failed to stop TX DMA, queues=0x%03x!\n", npend); 1957 } 1958 1959 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1960 if (!ATH_TXQ_SETUP(sc, i)) 1961 continue; 1962 1963 txq = &sc->tx.txq[i]; 1964 ath_draintxq(sc, txq); 1965 } 1966 1967 return !npend; 1968} 1969 1970void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 1971{ 1972 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); 1973 sc->tx.txqsetup &= ~(1<<txq->axq_qnum); 1974} 1975 1976/* For each acq entry, for each tid, try to schedule packets 1977 * for transmit until ampdu_depth has reached min Q depth. 1978 */ 1979void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) 1980{ 1981 struct ieee80211_hw *hw = sc->hw; 1982 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1983 struct ieee80211_txq *queue; 1984 struct ath_atx_tid *tid; 1985 int ret; 1986 1987 if (txq->mac80211_qnum < 0) 1988 return; 1989 1990 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 1991 return; 1992 1993 ieee80211_txq_schedule_start(hw, txq->mac80211_qnum); 1994 spin_lock_bh(&sc->chan_lock); 1995 rcu_read_lock(); 1996 1997 if (sc->cur_chan->stopped) 1998 goto out; 1999 2000 while ((queue = ieee80211_next_txq(hw, txq->mac80211_qnum))) { 2001 bool force; 2002 2003 tid = (struct ath_atx_tid *)queue->drv_priv; 2004 2005 ret = ath_tx_sched_aggr(sc, txq, tid); 2006 ath_dbg(common, QUEUE, "ath_tx_sched_aggr returned %d\n", ret); 2007 2008 force = !skb_queue_empty(&tid->retry_q); 2009 ieee80211_return_txq(hw, queue, force); 2010 } 2011 2012out: 2013 rcu_read_unlock(); 2014 spin_unlock_bh(&sc->chan_lock); 2015 ieee80211_txq_schedule_end(hw, txq->mac80211_qnum); 2016} 2017 2018void ath_txq_schedule_all(struct ath_softc *sc) 2019{ 2020 struct ath_txq *txq; 2021 int i; 2022 2023 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 2024 txq = sc->tx.txq_map[i]; 2025 2026 spin_lock_bh(&txq->axq_lock); 2027 ath_txq_schedule(sc, txq); 2028 spin_unlock_bh(&txq->axq_lock); 2029 } 2030} 2031 2032/***********/ 2033/* TX, DMA */ 2034/***********/ 2035 2036/* 2037 * Insert a chain of ath_buf (descriptors) on a txq and 2038 * assume the descriptors are already chained together by caller. 2039 */ 2040static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 2041 struct list_head *head, bool internal) 2042{ 2043 struct ath_hw *ah = sc->sc_ah; 2044 struct ath_common *common = ath9k_hw_common(ah); 2045 struct ath_buf *bf, *bf_last; 2046 bool puttxbuf = false; 2047 bool edma; 2048 2049 /* 2050 * Insert the frame on the outbound list and 2051 * pass it on to the hardware. 2052 */ 2053 2054 if (list_empty(head)) 2055 return; 2056 2057 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2058 bf = list_first_entry(head, struct ath_buf, list); 2059 bf_last = list_entry(head->prev, struct ath_buf, list); 2060 2061 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n", 2062 txq->axq_qnum, txq->axq_depth); 2063 2064 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { 2065 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); 2066 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); 2067 puttxbuf = true; 2068 } else { 2069 list_splice_tail_init(head, &txq->axq_q); 2070 2071 if (txq->axq_link) { 2072 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); 2073 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n", 2074 txq->axq_qnum, txq->axq_link, 2075 ito64(bf->bf_daddr), bf->bf_desc); 2076 } else if (!edma) 2077 puttxbuf = true; 2078 2079 txq->axq_link = bf_last->bf_desc; 2080 } 2081 2082 if (puttxbuf) { 2083 TX_STAT_INC(sc, txq->axq_qnum, puttxbuf); 2084 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 2085 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n", 2086 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 2087 } 2088 2089 if (!edma || sc->tx99_state) { 2090 TX_STAT_INC(sc, txq->axq_qnum, txstart); 2091 ath9k_hw_txstart(ah, txq->axq_qnum); 2092 } 2093 2094 if (!internal) { 2095 while (bf) { 2096 txq->axq_depth++; 2097 if (bf_is_ampdu_not_probing(bf)) 2098 txq->axq_ampdu_depth++; 2099 2100 bf_last = bf->bf_lastbf; 2101 bf = bf_last->bf_next; 2102 bf_last->bf_next = NULL; 2103 } 2104 } 2105} 2106 2107static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 2108 struct ath_atx_tid *tid, struct sk_buff *skb) 2109{ 2110 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2111 struct ath_frame_info *fi = get_frame_info(skb); 2112 struct list_head bf_head; 2113 struct ath_buf *bf = fi->bf; 2114 2115 INIT_LIST_HEAD(&bf_head); 2116 list_add_tail(&bf->list, &bf_head); 2117 bf->bf_state.bf_type = 0; 2118 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 2119 bf->bf_state.bf_type = BUF_AMPDU; 2120 ath_tx_addto_baw(sc, tid, bf); 2121 } 2122 2123 bf->bf_next = NULL; 2124 bf->bf_lastbf = bf; 2125 ath_tx_fill_desc(sc, bf, txq, fi->framelen); 2126 ath_tx_txqaddbuf(sc, txq, &bf_head, false); 2127 TX_STAT_INC(sc, txq->axq_qnum, queued); 2128} 2129 2130static void setup_frame_info(struct ieee80211_hw *hw, 2131 struct ieee80211_sta *sta, 2132 struct sk_buff *skb, 2133 int framelen) 2134{ 2135 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2136 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; 2137 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2138 const struct ieee80211_rate *rate; 2139 struct ath_frame_info *fi = get_frame_info(skb); 2140 struct ath_node *an = NULL; 2141 enum ath9k_key_type keytype; 2142 bool short_preamble = false; 2143 u8 txpower; 2144 2145 /* 2146 * We check if Short Preamble is needed for the CTS rate by 2147 * checking the BSS's global flag. 2148 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. 2149 */ 2150 if (tx_info->control.vif && 2151 tx_info->control.vif->bss_conf.use_short_preamble) 2152 short_preamble = true; 2153 2154 rate = ieee80211_get_rts_cts_rate(hw, tx_info); 2155 keytype = ath9k_cmn_get_hw_crypto_keytype(skb); 2156 2157 if (sta) 2158 an = (struct ath_node *) sta->drv_priv; 2159 2160 if (tx_info->control.vif) { 2161 struct ieee80211_vif *vif = tx_info->control.vif; 2162 if (vif->bss_conf.txpower == INT_MIN) 2163 goto nonvifpower; 2164 txpower = 2 * vif->bss_conf.txpower; 2165 } else { 2166 struct ath_softc *sc; 2167 nonvifpower: 2168 sc = hw->priv; 2169 2170 txpower = sc->cur_chan->cur_txpower; 2171 } 2172 2173 memset(fi, 0, sizeof(*fi)); 2174 fi->txq = -1; 2175 if (hw_key) 2176 fi->keyix = hw_key->hw_key_idx; 2177 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0) 2178 fi->keyix = an->ps_key; 2179 else 2180 fi->keyix = ATH9K_TXKEYIX_INVALID; 2181 fi->dyn_smps = sta && sta->deflink.smps_mode == IEEE80211_SMPS_DYNAMIC; 2182 fi->keytype = keytype; 2183 fi->framelen = framelen; 2184 fi->tx_power = txpower; 2185 2186 if (!rate) 2187 return; 2188 fi->rtscts_rate = rate->hw_value; 2189 if (short_preamble) 2190 fi->rtscts_rate |= rate->hw_value_short; 2191} 2192 2193u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) 2194{ 2195 struct ath_hw *ah = sc->sc_ah; 2196 struct ath9k_channel *curchan = ah->curchan; 2197 2198 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) && 2199 (chainmask == 0x7) && (rate < 0x90)) 2200 return 0x3; 2201 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) && 2202 IS_CCK_RATE(rate)) 2203 return 0x2; 2204 else 2205 return chainmask; 2206} 2207 2208/* 2209 * Assign a descriptor (and sequence number if necessary, 2210 * and map buffer for DMA. Frees skb on error 2211 */ 2212static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 2213 struct ath_txq *txq, 2214 struct ath_atx_tid *tid, 2215 struct sk_buff *skb) 2216{ 2217 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2218 struct ath_frame_info *fi = get_frame_info(skb); 2219 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2220 struct ath_buf *bf; 2221 int fragno; 2222 u16 seqno; 2223 2224 bf = ath_tx_get_buffer(sc); 2225 if (!bf) { 2226 ath_dbg(common, XMIT, "TX buffers are full\n"); 2227 return NULL; 2228 } 2229 2230 ATH_TXBUF_RESET(bf); 2231 2232 if (tid && ieee80211_is_data_present(hdr->frame_control)) { 2233 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 2234 seqno = tid->seq_next; 2235 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); 2236 2237 if (fragno) 2238 hdr->seq_ctrl |= cpu_to_le16(fragno); 2239 2240 if (!ieee80211_has_morefrags(hdr->frame_control)) 2241 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 2242 2243 bf->bf_state.seqno = seqno; 2244 } 2245 2246 bf->bf_mpdu = skb; 2247 2248 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 2249 skb->len, DMA_TO_DEVICE); 2250 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 2251 bf->bf_mpdu = NULL; 2252 bf->bf_buf_addr = 0; 2253 ath_err(ath9k_hw_common(sc->sc_ah), 2254 "dma_mapping_error() on TX\n"); 2255 ath_tx_return_buffer(sc, bf); 2256 return NULL; 2257 } 2258 2259 fi->bf = bf; 2260 2261 return bf; 2262} 2263 2264void ath_assign_seq(struct ath_common *common, struct sk_buff *skb) 2265{ 2266 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2267 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2268 struct ieee80211_vif *vif = info->control.vif; 2269 struct ath_vif *avp; 2270 2271 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)) 2272 return; 2273 2274 if (!vif) 2275 return; 2276 2277 avp = (struct ath_vif *)vif->drv_priv; 2278 2279 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 2280 avp->seq_no += 0x10; 2281 2282 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 2283 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no); 2284} 2285 2286static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb, 2287 struct ath_tx_control *txctl) 2288{ 2289 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2290 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2291 struct ieee80211_sta *sta = txctl->sta; 2292 struct ieee80211_vif *vif = info->control.vif; 2293 struct ath_vif *avp; 2294 struct ath_softc *sc = hw->priv; 2295 int frmlen = skb->len + FCS_LEN; 2296 int padpos, padsize; 2297 2298 /* NOTE: sta can be NULL according to net/mac80211.h */ 2299 if (sta) 2300 txctl->an = (struct ath_node *)sta->drv_priv; 2301 else if (vif && ieee80211_is_data(hdr->frame_control)) { 2302 avp = (void *)vif->drv_priv; 2303 txctl->an = &avp->mcast_node; 2304 } 2305 2306 if (info->control.hw_key) 2307 frmlen += info->control.hw_key->icv_len; 2308 2309 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb); 2310 2311 if ((vif && vif->type != NL80211_IFTYPE_AP && 2312 vif->type != NL80211_IFTYPE_AP_VLAN) || 2313 !ieee80211_is_data(hdr->frame_control)) 2314 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 2315 2316 /* Add the padding after the header if this is not already done */ 2317 padpos = ieee80211_hdrlen(hdr->frame_control); 2318 padsize = padpos & 3; 2319 if (padsize && skb->len > padpos) { 2320 if (skb_headroom(skb) < padsize) 2321 return -ENOMEM; 2322 2323 skb_push(skb, padsize); 2324 memmove(skb->data, skb->data + padsize, padpos); 2325 } 2326 2327 setup_frame_info(hw, sta, skb, frmlen); 2328 return 0; 2329} 2330 2331 2332/* Upon failure caller should free skb */ 2333int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 2334 struct ath_tx_control *txctl) 2335{ 2336 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2337 struct ieee80211_sta *sta = txctl->sta; 2338 struct ieee80211_vif *vif = info->control.vif; 2339 struct ath_frame_info *fi = get_frame_info(skb); 2340 struct ath_softc *sc = hw->priv; 2341 struct ath_txq *txq = txctl->txq; 2342 struct ath_atx_tid *tid = NULL; 2343 struct ath_node *an = NULL; 2344 struct ath_buf *bf; 2345 bool ps_resp; 2346 int q, ret; 2347 2348 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE); 2349 2350 ret = ath_tx_prepare(hw, skb, txctl); 2351 if (ret) 2352 return ret; 2353 2354 /* 2355 * At this point, the vif, hw_key and sta pointers in the tx control 2356 * info are no longer valid (overwritten by the ath_frame_info data. 2357 */ 2358 2359 q = skb_get_queue_mapping(skb); 2360 2361 if (ps_resp) 2362 txq = sc->tx.uapsdq; 2363 2364 if (txctl->sta) { 2365 an = (struct ath_node *) sta->drv_priv; 2366 tid = ath_get_skb_tid(sc, an, skb); 2367 } 2368 2369 ath_txq_lock(sc, txq); 2370 if (txq == sc->tx.txq_map[q]) { 2371 fi->txq = q; 2372 ++txq->pending_frames; 2373 } 2374 2375 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 2376 if (!bf) { 2377 ath_txq_skb_done(sc, txq, skb); 2378 if (txctl->paprd) 2379 dev_kfree_skb_any(skb); 2380 else 2381 ieee80211_free_txskb(sc->hw, skb); 2382 goto out; 2383 } 2384 2385 bf->bf_state.bfs_paprd = txctl->paprd; 2386 2387 if (txctl->paprd) 2388 bf->bf_state.bfs_paprd_timestamp = jiffies; 2389 2390 ath_set_rates(vif, sta, bf); 2391 ath_tx_send_normal(sc, txq, tid, skb); 2392 2393out: 2394 ath_txq_unlock(sc, txq); 2395 2396 return 0; 2397} 2398 2399void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2400 struct sk_buff *skb) 2401{ 2402 struct ath_softc *sc = hw->priv; 2403 struct ath_tx_control txctl = { 2404 .txq = sc->beacon.cabq 2405 }; 2406 struct ath_tx_info info = {}; 2407 struct ath_buf *bf_tail = NULL; 2408 struct ath_buf *bf; 2409 LIST_HEAD(bf_q); 2410 int duration = 0; 2411 int max_duration; 2412 2413 max_duration = 2414 sc->cur_chan->beacon.beacon_interval * 1000 * 2415 sc->cur_chan->beacon.dtim_period / ATH_BCBUF; 2416 2417 do { 2418 struct ath_frame_info *fi = get_frame_info(skb); 2419 2420 if (ath_tx_prepare(hw, skb, &txctl)) 2421 break; 2422 2423 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb); 2424 if (!bf) 2425 break; 2426 2427 bf->bf_lastbf = bf; 2428 ath_set_rates(vif, NULL, bf); 2429 ath_buf_set_rate(sc, bf, &info, fi->framelen, false); 2430 duration += info.rates[0].PktDuration; 2431 if (bf_tail) 2432 bf_tail->bf_next = bf; 2433 2434 list_add_tail(&bf->list, &bf_q); 2435 bf_tail = bf; 2436 skb = NULL; 2437 2438 if (duration > max_duration) 2439 break; 2440 2441 skb = ieee80211_get_buffered_bc(hw, vif); 2442 } while(skb); 2443 2444 if (skb) 2445 ieee80211_free_txskb(hw, skb); 2446 2447 if (list_empty(&bf_q)) 2448 return; 2449 2450 bf = list_last_entry(&bf_q, struct ath_buf, list); 2451 ath9k_set_moredata(sc, bf, false); 2452 2453 bf = list_first_entry(&bf_q, struct ath_buf, list); 2454 ath_txq_lock(sc, txctl.txq); 2455 ath_tx_fill_desc(sc, bf, txctl.txq, 0); 2456 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false); 2457 TX_STAT_INC(sc, txctl.txq->axq_qnum, queued); 2458 ath_txq_unlock(sc, txctl.txq); 2459} 2460 2461/*****************/ 2462/* TX Completion */ 2463/*****************/ 2464 2465static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 2466 int tx_flags, struct ath_txq *txq, 2467 struct ieee80211_sta *sta) 2468{ 2469 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2470 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2471 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 2472 int padpos, padsize; 2473 unsigned long flags; 2474 2475 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); 2476 2477 if (sc->sc_ah->caldata) 2478 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags); 2479 2480 if (!(tx_flags & ATH_TX_ERROR)) { 2481 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 2482 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 2483 else 2484 tx_info->flags |= IEEE80211_TX_STAT_ACK; 2485 } 2486 2487 if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) { 2488 padpos = ieee80211_hdrlen(hdr->frame_control); 2489 padsize = padpos & 3; 2490 if (padsize && skb->len>padpos+padsize) { 2491 /* 2492 * Remove MAC header padding before giving the frame back to 2493 * mac80211. 2494 */ 2495 memmove(skb->data + padsize, skb->data, padpos); 2496 skb_pull(skb, padsize); 2497 } 2498 } 2499 2500 spin_lock_irqsave(&sc->sc_pm_lock, flags); 2501 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { 2502 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; 2503 ath_dbg(common, PS, 2504 "Going back to sleep after having received TX status (0x%lx)\n", 2505 sc->ps_flags & (PS_WAIT_FOR_BEACON | 2506 PS_WAIT_FOR_CAB | 2507 PS_WAIT_FOR_PSPOLL_DATA | 2508 PS_WAIT_FOR_TX_ACK)); 2509 } 2510 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 2511 2512 ath_txq_skb_done(sc, txq, skb); 2513 tx_info->status.status_driver_data[0] = sta; 2514 __skb_queue_tail(&txq->complete_q, skb); 2515} 2516 2517static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 2518 struct ath_txq *txq, struct list_head *bf_q, 2519 struct ieee80211_sta *sta, 2520 struct ath_tx_status *ts, int txok) 2521{ 2522 struct sk_buff *skb = bf->bf_mpdu; 2523 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2524 unsigned long flags; 2525 int tx_flags = 0; 2526 2527 if (!txok) 2528 tx_flags |= ATH_TX_ERROR; 2529 2530 if (ts->ts_status & ATH9K_TXERR_FILT) 2531 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 2532 2533 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); 2534 bf->bf_buf_addr = 0; 2535 if (sc->tx99_state) 2536 goto skip_tx_complete; 2537 2538 if (bf->bf_state.bfs_paprd) { 2539 if (time_after(jiffies, 2540 bf->bf_state.bfs_paprd_timestamp + 2541 msecs_to_jiffies(ATH_PAPRD_TIMEOUT))) 2542 dev_kfree_skb_any(skb); 2543 else 2544 complete(&sc->paprd_complete); 2545 } else { 2546 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags); 2547 ath_tx_complete(sc, skb, tx_flags, txq, sta); 2548 } 2549skip_tx_complete: 2550 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't 2551 * accidentally reference it later. 2552 */ 2553 bf->bf_mpdu = NULL; 2554 2555 /* 2556 * Return the list of ath_buf of this mpdu to free queue 2557 */ 2558 spin_lock_irqsave(&sc->tx.txbuflock, flags); 2559 list_splice_tail_init(bf_q, &sc->tx.txbuf); 2560 spin_unlock_irqrestore(&sc->tx.txbuflock, flags); 2561} 2562 2563static void ath_clear_tx_status(struct ieee80211_tx_info *tx_info) 2564{ 2565 void *ptr = &tx_info->status; 2566 2567 memset(ptr + sizeof(tx_info->status.rates), 0, 2568 sizeof(tx_info->status) - 2569 sizeof(tx_info->status.rates) - 2570 sizeof(tx_info->status.status_driver_data)); 2571} 2572 2573static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 2574 struct ath_tx_status *ts, int nframes, int nbad, 2575 int txok) 2576{ 2577 struct sk_buff *skb = bf->bf_mpdu; 2578 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2579 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2580 struct ieee80211_hw *hw = sc->hw; 2581 struct ath_hw *ah = sc->sc_ah; 2582 u8 i, tx_rateindex; 2583 2584 ath_clear_tx_status(tx_info); 2585 2586 if (txok) 2587 tx_info->status.ack_signal = ts->ts_rssi; 2588 2589 tx_rateindex = ts->ts_rateindex; 2590 WARN_ON(tx_rateindex >= hw->max_rates); 2591 2592 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 2593 tx_info->flags |= IEEE80211_TX_STAT_AMPDU; 2594 2595 BUG_ON(nbad > nframes); 2596 } 2597 tx_info->status.ampdu_len = nframes; 2598 tx_info->status.ampdu_ack_len = nframes - nbad; 2599 2600 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; 2601 2602 for (i = tx_rateindex + 1; i < hw->max_rates; i++) { 2603 tx_info->status.rates[i].count = 0; 2604 tx_info->status.rates[i].idx = -1; 2605 } 2606 2607 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && 2608 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) { 2609 /* 2610 * If an underrun error is seen assume it as an excessive 2611 * retry only if max frame trigger level has been reached 2612 * (2 KB for single stream, and 4 KB for dual stream). 2613 * Adjust the long retry as if the frame was tried 2614 * hw->max_rate_tries times to affect how rate control updates 2615 * PER for the failed rate. 2616 * In case of congestion on the bus penalizing this type of 2617 * underruns should help hardware actually transmit new frames 2618 * successfully by eventually preferring slower rates. 2619 * This itself should also alleviate congestion on the bus. 2620 */ 2621 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | 2622 ATH9K_TX_DELIM_UNDERRUN)) && 2623 ieee80211_is_data(hdr->frame_control) && 2624 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) 2625 tx_info->status.rates[tx_rateindex].count = 2626 hw->max_rate_tries; 2627 } 2628} 2629 2630static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 2631{ 2632 struct ath_hw *ah = sc->sc_ah; 2633 struct ath_common *common = ath9k_hw_common(ah); 2634 struct ath_buf *bf, *lastbf, *bf_held = NULL; 2635 struct list_head bf_head; 2636 struct ath_desc *ds; 2637 struct ath_tx_status ts; 2638 int status; 2639 2640 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n", 2641 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 2642 txq->axq_link); 2643 2644 ath_txq_lock(sc, txq); 2645 for (;;) { 2646 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2647 break; 2648 2649 if (list_empty(&txq->axq_q)) { 2650 txq->axq_link = NULL; 2651 ath_txq_schedule(sc, txq); 2652 break; 2653 } 2654 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 2655 2656 /* 2657 * There is a race condition that a BH gets scheduled 2658 * after sw writes TxE and before hw re-load the last 2659 * descriptor to get the newly chained one. 2660 * Software must keep the last DONE descriptor as a 2661 * holding descriptor - software does so by marking 2662 * it with the STALE flag. 2663 */ 2664 bf_held = NULL; 2665 if (bf->bf_state.stale) { 2666 bf_held = bf; 2667 if (list_is_last(&bf_held->list, &txq->axq_q)) 2668 break; 2669 2670 bf = list_entry(bf_held->list.next, struct ath_buf, 2671 list); 2672 } 2673 2674 lastbf = bf->bf_lastbf; 2675 ds = lastbf->bf_desc; 2676 2677 memset(&ts, 0, sizeof(ts)); 2678 status = ath9k_hw_txprocdesc(ah, ds, &ts); 2679 if (status == -EINPROGRESS) 2680 break; 2681 2682 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc); 2683 2684 /* 2685 * Remove ath_buf's of the same transmit unit from txq, 2686 * however leave the last descriptor back as the holding 2687 * descriptor for hw. 2688 */ 2689 lastbf->bf_state.stale = true; 2690 INIT_LIST_HEAD(&bf_head); 2691 if (!list_is_singular(&lastbf->list)) 2692 list_cut_position(&bf_head, 2693 &txq->axq_q, lastbf->list.prev); 2694 2695 if (bf_held) { 2696 list_del(&bf_held->list); 2697 ath_tx_return_buffer(sc, bf_held); 2698 } 2699 2700 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2701 } 2702 ath_txq_unlock_complete(sc, txq); 2703} 2704 2705void ath_tx_tasklet(struct ath_softc *sc) 2706{ 2707 struct ath_hw *ah = sc->sc_ah; 2708 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs; 2709 int i; 2710 2711 rcu_read_lock(); 2712 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2713 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) 2714 ath_tx_processq(sc, &sc->tx.txq[i]); 2715 } 2716 rcu_read_unlock(); 2717} 2718 2719void ath_tx_edma_tasklet(struct ath_softc *sc) 2720{ 2721 struct ath_tx_status ts; 2722 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2723 struct ath_hw *ah = sc->sc_ah; 2724 struct ath_txq *txq; 2725 struct ath_buf *bf, *lastbf; 2726 struct list_head bf_head; 2727 struct list_head *fifo_list; 2728 int status; 2729 2730 rcu_read_lock(); 2731 for (;;) { 2732 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2733 break; 2734 2735 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); 2736 if (status == -EINPROGRESS) 2737 break; 2738 if (status == -EIO) { 2739 ath_dbg(common, XMIT, "Error processing tx status\n"); 2740 break; 2741 } 2742 2743 /* Process beacon completions separately */ 2744 if (ts.qid == sc->beacon.beaconq) { 2745 sc->beacon.tx_processed = true; 2746 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2747 2748 if (ath9k_is_chanctx_enabled()) { 2749 ath_chanctx_event(sc, NULL, 2750 ATH_CHANCTX_EVENT_BEACON_SENT); 2751 } 2752 2753 ath9k_csa_update(sc); 2754 continue; 2755 } 2756 2757 txq = &sc->tx.txq[ts.qid]; 2758 2759 ath_txq_lock(sc, txq); 2760 2761 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc); 2762 2763 fifo_list = &txq->txq_fifo[txq->txq_tailidx]; 2764 if (list_empty(fifo_list)) { 2765 ath_txq_unlock(sc, txq); 2766 break; 2767 } 2768 2769 bf = list_first_entry(fifo_list, struct ath_buf, list); 2770 if (bf->bf_state.stale) { 2771 list_del(&bf->list); 2772 ath_tx_return_buffer(sc, bf); 2773 bf = list_first_entry(fifo_list, struct ath_buf, list); 2774 } 2775 2776 lastbf = bf->bf_lastbf; 2777 2778 INIT_LIST_HEAD(&bf_head); 2779 if (list_is_last(&lastbf->list, fifo_list)) { 2780 list_splice_tail_init(fifo_list, &bf_head); 2781 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); 2782 2783 if (!list_empty(&txq->axq_q)) { 2784 struct list_head bf_q; 2785 2786 INIT_LIST_HEAD(&bf_q); 2787 txq->axq_link = NULL; 2788 list_splice_tail_init(&txq->axq_q, &bf_q); 2789 ath_tx_txqaddbuf(sc, txq, &bf_q, true); 2790 } 2791 } else { 2792 lastbf->bf_state.stale = true; 2793 if (bf != lastbf) 2794 list_cut_position(&bf_head, fifo_list, 2795 lastbf->list.prev); 2796 } 2797 2798 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2799 ath_txq_unlock_complete(sc, txq); 2800 } 2801 rcu_read_unlock(); 2802} 2803 2804/*****************/ 2805/* Init, Cleanup */ 2806/*****************/ 2807 2808static int ath_txstatus_setup(struct ath_softc *sc, int size) 2809{ 2810 struct ath_descdma *dd = &sc->txsdma; 2811 u8 txs_len = sc->sc_ah->caps.txs_len; 2812 2813 dd->dd_desc_len = size * txs_len; 2814 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 2815 &dd->dd_desc_paddr, GFP_KERNEL); 2816 if (!dd->dd_desc) 2817 return -ENOMEM; 2818 2819 return 0; 2820} 2821 2822static int ath_tx_edma_init(struct ath_softc *sc) 2823{ 2824 int err; 2825 2826 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); 2827 if (!err) 2828 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, 2829 sc->txsdma.dd_desc_paddr, 2830 ATH_TXSTATUS_RING_SIZE); 2831 2832 return err; 2833} 2834 2835int ath_tx_init(struct ath_softc *sc, int nbufs) 2836{ 2837 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2838 int error = 0; 2839 2840 spin_lock_init(&sc->tx.txbuflock); 2841 2842 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2843 "tx", nbufs, 1, 1); 2844 if (error != 0) { 2845 ath_err(common, 2846 "Failed to allocate tx descriptors: %d\n", error); 2847 return error; 2848 } 2849 2850 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2851 "beacon", ATH_BCBUF, 1, 1); 2852 if (error != 0) { 2853 ath_err(common, 2854 "Failed to allocate beacon descriptors: %d\n", error); 2855 return error; 2856 } 2857 2858 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 2859 error = ath_tx_edma_init(sc); 2860 2861 return error; 2862} 2863 2864void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) 2865{ 2866 struct ath_atx_tid *tid; 2867 int tidno, acno; 2868 2869 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 2870 tid = ath_node_to_tid(an, tidno); 2871 tid->an = an; 2872 tid->tidno = tidno; 2873 tid->seq_start = tid->seq_next = 0; 2874 tid->baw_size = WME_MAX_BA; 2875 tid->baw_head = tid->baw_tail = 0; 2876 tid->active = false; 2877 tid->clear_ps_filter = true; 2878 __skb_queue_head_init(&tid->retry_q); 2879 INIT_LIST_HEAD(&tid->list); 2880 acno = TID_TO_WME_AC(tidno); 2881 tid->txq = sc->tx.txq_map[acno]; 2882 2883 if (!an->sta) 2884 break; /* just one multicast ath_atx_tid */ 2885 } 2886} 2887 2888void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) 2889{ 2890 struct ath_atx_tid *tid; 2891 struct ath_txq *txq; 2892 int tidno; 2893 2894 rcu_read_lock(); 2895 2896 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 2897 tid = ath_node_to_tid(an, tidno); 2898 txq = tid->txq; 2899 2900 ath_txq_lock(sc, txq); 2901 2902 if (!list_empty(&tid->list)) 2903 list_del_init(&tid->list); 2904 2905 ath_tid_drain(sc, txq, tid); 2906 tid->active = false; 2907 2908 ath_txq_unlock(sc, txq); 2909 2910 if (!an->sta) 2911 break; /* just one multicast ath_atx_tid */ 2912 } 2913 2914 rcu_read_unlock(); 2915} 2916 2917#ifdef CONFIG_ATH9K_TX99 2918 2919int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, 2920 struct ath_tx_control *txctl) 2921{ 2922 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2923 struct ath_frame_info *fi = get_frame_info(skb); 2924 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2925 struct ath_buf *bf; 2926 int padpos, padsize; 2927 2928 padpos = ieee80211_hdrlen(hdr->frame_control); 2929 padsize = padpos & 3; 2930 2931 if (padsize && skb->len > padpos) { 2932 if (skb_headroom(skb) < padsize) { 2933 ath_dbg(common, XMIT, 2934 "tx99 padding failed\n"); 2935 return -EINVAL; 2936 } 2937 2938 skb_push(skb, padsize); 2939 memmove(skb->data, skb->data + padsize, padpos); 2940 } 2941 2942 fi->keyix = ATH9K_TXKEYIX_INVALID; 2943 fi->framelen = skb->len + FCS_LEN; 2944 fi->keytype = ATH9K_KEY_TYPE_CLEAR; 2945 2946 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb); 2947 if (!bf) { 2948 ath_dbg(common, XMIT, "tx99 buffer setup failed\n"); 2949 return -EINVAL; 2950 } 2951 2952 ath_set_rates(sc->tx99_vif, NULL, bf); 2953 2954 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr); 2955 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum); 2956 2957 ath_tx_send_normal(sc, txctl->txq, NULL, skb); 2958 2959 return 0; 2960} 2961 2962#endif /* CONFIG_ATH9K_TX99 */ 2963